diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md
index 53575c1c7..b0a769682 100644
--- a/proposals/simd/BinarySIMD.md
+++ b/proposals/simd/BinarySIMD.md
@@ -170,5 +170,7 @@ The `v8x16.shuffle2_imm` instruction has 16 bytes after `simdop`.
 | `i8x8.sxload`             |    `0xb4`| m:memarg           |
 | `i16x4.zxload`            |    `0xb5`| m:memarg           |
 | `i16x4.sxload`            |    `0xb6`| m:memarg           |
+| `i32x2.zxload`            |    `0xb7`| m:memarg           |
+| `i32x2.sxload`            |    `0xb8`| m:memarg           |
 | `v8x16.shuffle1`          |    `0xc0`| -                  |
 | `v8x16.shuffle2_imm`      |    `0xc1`| s:LaneIdx32[16]    |
diff --git a/proposals/simd/ImplementationStatus.md b/proposals/simd/ImplementationStatus.md
index 1b050e7e4..fb2a3ac30 100644
--- a/proposals/simd/ImplementationStatus.md
+++ b/proposals/simd/ImplementationStatus.md
@@ -143,6 +143,8 @@
 | `i8x8.sxload`             |                           |                    |                    |                    |
 | `i16x4.zxload`            |                           |                    |                    |                    |
 | `i16x4.sxload`            |                           |                    |                    |                    |
+| `i32x2.zxload`            |                           |                    |                    |                    |
+| `i32x2.sxload`            |                           |                    |                    |                    |
 | `v8x16.shuffle1`          |                           |                    | :heavy_check_mark: |                    |
 | `v8x16.shuffle2_imm`      |                           |                    | :heavy_check_mark: | :heavy_check_mark: |
 
diff --git a/proposals/simd/SIMD.md b/proposals/simd/SIMD.md
index 94806c4ec..40e4eabd3 100644
--- a/proposals/simd/SIMD.md
+++ b/proposals/simd/SIMD.md
@@ -672,6 +672,8 @@ Extended loads:
 * `i8x8.sxload(memarg) -> v128`: load eight 8-bit integers and sign extend each one to a 16-bit lane
 * `i16x4.zxload(memarg) -> v128`: load four 16-bit integers and zero extend each one to a 32-bit lane
 * `i16x4.sxload(memarg) -> v128`: load four 16-bit integers and sign extend each one to a 32-bit lane
+* `i32x2.zxload(memarg) -> v128`: load two 32-bit integers and zero extend each one to a 64-bit lane
+* `i32x2.sxload(memarg) -> v128`: load two 32-bit integers and sign extend each one to a 64-bit lane
 
 ### Store