From d120418f871d579fcf92ce79ef08f953fd326721 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 25 Nov 2020 16:14:25 +0100 Subject: [PATCH] Revert "Agesa bootblock" --- src/cpu/x86/lapic/Makefile.inc | 1 - src/drivers/amd/agesa/Makefile.inc | 3 - src/drivers/amd/agesa/bootblock.c | 45 +--- src/drivers/amd/agesa/romstage.c | 39 ++- src/drivers/amd/agesa/state_machine.c | 19 +- src/mainboard/pcengines/apu2/Kconfig | 11 +- src/mainboard/pcengines/apu2/Makefile.inc | 6 - src/mainboard/pcengines/apu2/bootblock.c | 221 ----------------- src/mainboard/pcengines/apu2/romstage.c | 226 ++++++++++++++++++ src/mainboard/pcengines/apu2/vboot-rw-ab.fmd | 30 +-- .../amd/agesa/family14/Makefile.inc | 1 - .../amd/agesa/family15tn/Makefile.inc | 1 - .../amd/agesa/family16kb/Makefile.inc | 1 - src/northbridge/amd/pi/00730F01/Makefile.inc | 1 - src/southbridge/amd/pi/hudson/Kconfig | 1 - src/southbridge/amd/pi/hudson/Makefile.inc | 1 - src/southbridge/amd/pi/hudson/bootblock.c | 8 - src/southbridge/amd/pi/hudson/spi.c | 75 +++--- src/vendorcode/amd/pi/Makefile.inc | 1 - 19 files changed, 337 insertions(+), 354 deletions(-) create mode 100644 src/mainboard/pcengines/apu2/romstage.c diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 2581e60d125..ea160148cfc 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -5,7 +5,6 @@ bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -verstage_x86-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c verstage_x86-y += boot_cpu.c romstage-y += boot_cpu.c diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index e39e93a8c23..6d80c4c6c30 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -10,9 +10,6 @@ ramstage-y += state_machine.c bootblock-y += bootblock.c bootblock-y += cache_as_ram.S -bootblock-y += state_machine.c -bootblock-y += def_callouts.c -bootblock-y += eventlog.c postcar-y += exit_car.S diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 7058451dbe7..df9876a84ab 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -2,21 +2,15 @@ #include #include -#include -#include #include +#include #include -#include #include #include #include -#include -#include #define EARLY_VMTRR_FLASH 6 -void __weak board_BeforeAgesa(struct sysinfo *cb) { } - static void set_early_mtrrs(void) { /* Cache the ROM to speed up booting */ @@ -29,39 +23,6 @@ void bootblock_soc_early_init(void) bootblock_early_southbridge_init(); } -static void fill_sysinfo(struct sysinfo *cb) -{ - memset(cb, 0, sizeof(*cb)); - cb->s3resume = acpi_is_wakeup_s3(); - - agesa_set_interface(cb); -} - -void bootblock_soc_init(void) -{ - struct sysinfo bootblock_state; - struct sysinfo *cb = &bootblock_state; - u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); - - fill_sysinfo(cb); - - if (initial_apic_id == 0) { - board_BeforeAgesa(cb); - console_init(); - } - - printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", - initial_apic_id, cpuid_eax(1)); - - agesa_execute_state(cb, AMD_INIT_RESET); - - agesa_execute_state(cb, AMD_INIT_EARLY); - - /* APs shall not get here */ - if (initial_apic_id != 0) - halt(); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { enable_pci_mmconf(); @@ -81,5 +42,7 @@ asmlinkage void ap_bootblock_c_entry(void) if (CONFIG(UDELAY_LAPIC)) enable_lapic(); - bootblock_soc_init(); + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); + ap_romstage_entry(); /* execution does not return */ + halt(); } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 6ac8e482b9d..29423ef1ba8 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -15,6 +15,8 @@ #include #include +void __weak board_BeforeAgesa(struct sysinfo *cb) { } + static void fill_sysinfo(struct sysinfo *cb) { memset(cb, 0, sizeof(*cb)); @@ -23,6 +25,11 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } +/* APs will enter directly here from bootblock, bypassing verstage + * and potential fallback / normal bootflow detection. + */ +static void ap_romstage_main(void); + static void romstage_main(void) { struct postcar_frame pcf; @@ -33,8 +40,23 @@ static void romstage_main(void) fill_sysinfo(cb); - if (initial_apic_id == 0) + if (initial_apic_id == 0) { + + timestamp_add_now(TS_START_ROMSTAGE); + + board_BeforeAgesa(cb); + console_init(); + } + + printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", + initial_apic_id, cpuid_eax(1)); + + set_ap_entry_ptr(ap_romstage_main); + + agesa_execute_state(cb, AMD_INIT_RESET); + + agesa_execute_state(cb, AMD_INIT_EARLY); timestamp_add_now(TS_BEFORE_INITRAM); @@ -66,6 +88,21 @@ static void romstage_main(void) /* We do not return. */ } +static void ap_romstage_main(void) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + + fill_sysinfo(cb); + + agesa_execute_state(cb, AMD_INIT_RESET); + + agesa_execute_state(cb, AMD_INIT_EARLY); + + /* Not reached. */ + halt(); +} + asmlinkage void car_stage_entry(void) { romstage_main(); diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index bfe4e202ce1..606a66f5cb3 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -29,22 +29,9 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader) const char ModuleIdentifier[] = AGESA_ID; const void *agesa, *image; size_t file_size; - uint32_t cbfs_type = CBFS_TYPE_RAW; - struct cbfsf fh; - - if (CONFIG(VBOOT)) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", - (const char *)CONFIG_AGESA_CBFS_NAME, - &cbfs_type) < 0) { - die("AGESA not found!"); - } - file_size = region_device_sz(&fh.data); - agesa = rdev_mmap_full(&fh.data); - } else { - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); - } + agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, + CBFS_TYPE_RAW, &file_size); if (agesa == NULL) return; @@ -276,7 +263,7 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id) timestamp_add_now(task.ts_entry_id); - if (ENV_ROMSTAGE || ENV_BOOTBLOCK) + if (ENV_ROMSTAGE) final = romstage_dispatch(cb, func, StdHeader); if (ENV_RAMSTAGE) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 72c1d67829b..3b1939e6b17 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -119,18 +119,19 @@ config FMDFILE config CBFS_SIZE hex + default 0x0020C000 if VBOOT default 0x00800000 config VBOOT - select VBOOT_VBNV_FLASH + select VBOOT_VBNV_CMOS select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP select RTC - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_ROMSTAGE + select AMDFW_OUTSIDE_CBFS config VBOOT_MEASURED_BOOT_RUNTIME_DATA string @@ -138,11 +139,11 @@ config VBOOT_MEASURED_BOOT_RUNTIME_DATA config VBOOT_VBNV_OFFSET hex - default 0x2D8 if VBOOT_VBNV_CMOS + default 0x2D8 if VBOOT config RO_REGION_ONLY string - default "AGESA apu/amdfw" if VBOOT + default "spd.bin AGESA" if VBOOT config AGESA_USE_1_0_0_4_HEADER bool diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index eb8b065f98e..f69983fc18e 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -3,12 +3,6 @@ bootblock-y += pmutil.c bootblock-y += bootblock.c bootblock-y += bios_knobs.c -bootblock-y += BiosCallOuts.c -bootblock-y += OemCustomize.c -bootblock-y += gpio_ftns.c - -verstage-y += pmutil.c -verstage-y += bios_knobs.c romstage-y += bios_knobs.c romstage-y += BiosCallOuts.c diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c index 815b1aa7d67..464b3c6035a 100644 --- a/src/mainboard/pcengines/apu2/bootblock.c +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -1,38 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include -#include #include #include #include -#include -#include -#include "gpio_ftns.h" #include "bios_knobs.h" #define SIO_PORT 0x2e #define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) #define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) -static void early_lpc_init(void); -static void print_sign_of_life(void); -static void lpc_mcu_msg(void); -extern char coreboot_dmi_date[]; -extern char coreboot_version[]; - void bootblock_mainboard_early_init(void) { hudson_lpc_port80(); @@ -45,203 +24,3 @@ void bootblock_mainboard_early_init(void) if ((check_com2() || (CONFIG_UART_FOR_CONSOLE == 1))) nuvoton_enable_serial(SERIAL2_DEV, 0x2f8); } - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u32 val; - - pm_write8(FCH_PMIOA_REGC5, 0); - - early_lpc_init(); - - /* Disable SVI2 controller to wait for command completion */ - val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); - if (!(val & (1 << 30))) { - val |= (1 << 30); - pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); - } - - /* Release GPIO32/33 for other uses. */ - pm_write8(0xea, 1); -} - -static void early_lpc_init(void) -{ - u32 setting = 0x0; - - // - // Configure output disabled, value low, pull up/down disabled - // - if (CONFIG(BOARD_PCENGINES_APU5)) { - configure_gpio(GPIO_22, Function0, setting); - } - - if (CONFIG(BOARD_PCENGINES_APU2) || CONFIG(BOARD_PCENGINES_APU3) || - CONFIG(BOARD_PCENGINES_APU4) || CONFIG(BOARD_PCENGINES_APU6)) { - configure_gpio(GPIO_32, Function0, setting); - } - - configure_gpio(GPIO_49, Function2, setting); - configure_gpio(GPIO_50, Function2, setting); - configure_gpio(GPIO_71, Function0, setting); - - // - // Configure output enabled, value low, pull up/down disabled - // - setting = GPIO_OUTPUT_ENABLE; - if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4) || - CONFIG(BOARD_PCENGINES_APU6)) { - configure_gpio(GPIO_33, Function0, setting); - } - - configure_gpio(GPIO_57, Function1, setting); - configure_gpio(GPIO_58, Function1, setting); - configure_gpio(GPIO_59, Function3, setting); - - // - // Configure output enabled, value high, pull up/down disabled - // - setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE; - - if (CONFIG(BOARD_PCENGINES_APU5)) { - configure_gpio(GPIO_32, Function0, setting); - configure_gpio(GPIO_33, Function0, setting); - } - - configure_gpio(GPIO_51, Function2, setting); - configure_gpio(GPIO_55, Function3, setting); - - /* W_DIS# pins are connected directly to the SoC GPIOs without - * any external pull-ups. This causes issues with certain mPCIe - * modems. Configure pull-ups and output high in order to - * prevent disabling WLAN on the modules. APU5 has hardware - * pull-ups on the PCB. - */ - if (!CONFIG(BOARD_PCENGINES_APU5)) - setting = GPIO_PULL_UP_ENABLE | GPIO_OUTPUT_VALUE; - - configure_gpio(GPIO_64, Function2, setting); - configure_gpio(GPIO_68, Function0, setting); -} - -static const char *mainboard_bios_version(void) -{ - if (strlen(CONFIG_LOCALVERSION)) - return CONFIG_LOCALVERSION; - else - return coreboot_version; -} - -static void print_sign_of_life() -{ - char tmp[9]; - strncpy(tmp, coreboot_dmi_date+6, 4); - strncpy(tmp+4, coreboot_dmi_date+3, 2); - strncpy(tmp+6, coreboot_dmi_date, 2); - tmp[8] = '\0'; - printk(BIOS_ALERT, CONFIG_MAINBOARD_VENDOR " " - CONFIG_MAINBOARD_PART_NUMBER "\n"); - printk(BIOS_ALERT, "coreboot build %s\n", tmp); - printk(BIOS_ALERT, "BIOS version %s\n", mainboard_bios_version()); -} - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - u32 val, data; - - if (boot_cpu()) { - pm_write8(FCH_PMIOA_REGC5, 0); - - /* Check if cold boot was requested */ - val = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x6C); - if (val & (1 << 4)) { - printk(BIOS_ALERT, "Forcing cold boot path\n"); - val &= ~(0x630); // ColdRstDet[4], BiosRstDet[10:9, 5] - pci_write_config32(PCI_DEV(0, 0x18, 0), 0x6C, val); - - pm_write32(0xc0, 0x3fff003f); // Write-1-to-clear resets - - /* FullRst, SysRst, RstCmd */ - pm_write8(FCH_PMIOA_REGC5, 0xe); - printk(BIOS_ALERT, "Did not reset (yet)\n"); - } - - // do not print SOL if reset will take place in FchInit - if (!(pm_read32(0xc0) & FCH_PMIOxC0_S5ResetStatus_All_Status)) { - if (check_console()) - print_sign_of_life(); - - lpc_mcu_msg(); - } - - if ((check_mpcie2_clk() || CONFIG(FORCE_MPCIE2_CLK)) && - CONFIG(BOARD_PCENGINES_APU2)) { - // make GFXCLK to ignore CLKREQ# input - // force it to be always on - data = misc_read32(FCH_MISC_REG04); - data &= 0xFFFFFF0F; - data |= 0xF << (1 * 4); // CLKREQ GFX to GFXCLK - misc_write32(FCH_MISC_REG04, data); - printk(BIOS_DEBUG, "force mPCIe clock enabled\n"); - } - } -} - -static void lpc_mcu_msg(void) -{ - unsigned int i, timeout; - const char *post_msg = "BIOSBOOT"; - unsigned char sync_byte = 0; - - if (!CONFIG(BOARD_PCENGINES_APU5)) - return; - - uart_init(1); - - for (i = 0; i < 4; i++) { - uart_tx_byte(1, 0xe1); - uart_tx_flush(1); - timeout = 10; - while (sync_byte != 0xe1) { - sync_byte = uart_rx_byte(1); - if (timeout == 0) { - uart_init(CONFIG_UART_FOR_CONSOLE); - udelay(10000); - printk(BIOS_ERR, "Failed to sync with LPC" - " MCU, number of retries %d\n", 3 - i); - udelay(10000); - uart_init(1); - udelay(10000); - break; - } - udelay(100); - timeout--; - } - if (sync_byte == 0xe1) - break; - } - - if (sync_byte != 0xe1) - return; - - uart_init(1); - timeout = 10; - - for (i = 0; i < strlen(post_msg); i++) - uart_tx_byte(1, *(post_msg + i)); - - uart_tx_byte(1, 0xe1); - uart_tx_flush(1); - - while (uart_rx_byte(1) != 0xe1) { - if (timeout == 0) { - uart_init(CONFIG_UART_FOR_CONSOLE); - printk(BIOS_ERR, "Did not receive response to BIOSBOOT\n"); - return; - } - udelay(100); - timeout--; - } - - uart_init(CONFIG_UART_FOR_CONSOLE); -} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c new file mode 100644 index 00000000000..3b63c67b40b --- /dev/null +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bios_knobs.h" +#include "gpio_ftns.h" + +static void early_lpc_init(void); +static void print_sign_of_life(void); +static void lpc_mcu_msg(void); +extern char coreboot_dmi_date[]; +extern char coreboot_version[]; + +void board_BeforeAgesa(struct sysinfo *cb) +{ + u32 val; + + pm_write8(FCH_PMIOA_REGC5, 0); + + early_lpc_init(); + + /* Disable SVI2 controller to wait for command completion */ + val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); + if (!(val & (1 << 30))) { + val |= (1 << 30); + pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); + } + + /* Release GPIO32/33 for other uses. */ + pm_write8(0xea, 1); +} + +static void early_lpc_init(void) +{ + u32 setting = 0x0; + + // + // Configure output disabled, value low, pull up/down disabled + // + if (CONFIG(BOARD_PCENGINES_APU5)) { + configure_gpio(GPIO_22, Function0, setting); + } + + if (CONFIG(BOARD_PCENGINES_APU2) || CONFIG(BOARD_PCENGINES_APU3) || + CONFIG(BOARD_PCENGINES_APU4) || CONFIG(BOARD_PCENGINES_APU6)) { + configure_gpio(GPIO_32, Function0, setting); + } + + configure_gpio(GPIO_49, Function2, setting); + configure_gpio(GPIO_50, Function2, setting); + configure_gpio(GPIO_71, Function0, setting); + + // + // Configure output enabled, value low, pull up/down disabled + // + setting = GPIO_OUTPUT_ENABLE; + if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4) || + CONFIG(BOARD_PCENGINES_APU6)) { + configure_gpio(GPIO_33, Function0, setting); + } + + configure_gpio(GPIO_57, Function1, setting); + configure_gpio(GPIO_58, Function1, setting); + configure_gpio(GPIO_59, Function3, setting); + + // + // Configure output enabled, value high, pull up/down disabled + // + setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE; + + if (CONFIG(BOARD_PCENGINES_APU5)) { + configure_gpio(GPIO_32, Function0, setting); + configure_gpio(GPIO_33, Function0, setting); + } + + configure_gpio(GPIO_51, Function2, setting); + configure_gpio(GPIO_55, Function3, setting); + + /* W_DIS# pins are connected directly to the SoC GPIOs without + * any external pull-ups. This causes issues with certain mPCIe + * modems. Configure pull-ups and output high in order to + * prevent disabling WLAN on the modules. APU5 has hardware + * pull-ups on the PCB. + */ + if (!CONFIG(BOARD_PCENGINES_APU5)) + setting = GPIO_PULL_UP_ENABLE | GPIO_OUTPUT_VALUE; + + configure_gpio(GPIO_64, Function2, setting); + configure_gpio(GPIO_68, Function0, setting); +} + +static const char *mainboard_bios_version(void) +{ + if (strlen(CONFIG_LOCALVERSION)) + return CONFIG_LOCALVERSION; + else + return coreboot_version; +} + +static void print_sign_of_life() +{ + char tmp[9]; + strncpy(tmp, coreboot_dmi_date+6, 4); + strncpy(tmp+4, coreboot_dmi_date+3, 2); + strncpy(tmp+6, coreboot_dmi_date, 2); + tmp[8] = '\0'; + printk(BIOS_ALERT, CONFIG_MAINBOARD_VENDOR " " + CONFIG_MAINBOARD_PART_NUMBER "\n"); + printk(BIOS_ALERT, "coreboot build %s\n", tmp); + printk(BIOS_ALERT, "BIOS version %s\n", mainboard_bios_version()); +} + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + u32 val, data; + + if (boot_cpu()) { + pm_write8(FCH_PMIOA_REGC5, 0); + + /* Check if cold boot was requested */ + val = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x6C); + if (val & (1 << 4)) { + printk(BIOS_ALERT, "Forcing cold boot path\n"); + val &= ~(0x630); // ColdRstDet[4], BiosRstDet[10:9, 5] + pci_write_config32(PCI_DEV(0, 0x18, 0), 0x6C, val); + + pm_write32(0xc0, 0x3fff003f); // Write-1-to-clear resets + + /* FullRst, SysRst, RstCmd */ + pm_write8(FCH_PMIOA_REGC5, 0xe); + printk(BIOS_ALERT, "Did not reset (yet)\n"); + } + + // do not print SOL if reset will take place in FchInit + if (!(pm_read32(0xc0) & FCH_PMIOxC0_S5ResetStatus_All_Status)) { + if (check_console()) + print_sign_of_life(); + + lpc_mcu_msg(); + } + + if ((check_mpcie2_clk() || CONFIG(FORCE_MPCIE2_CLK)) && + CONFIG(BOARD_PCENGINES_APU2)) { + // make GFXCLK to ignore CLKREQ# input + // force it to be always on + data = misc_read32(FCH_MISC_REG04); + data &= 0xFFFFFF0F; + data |= 0xF << (1 * 4); // CLKREQ GFX to GFXCLK + misc_write32(FCH_MISC_REG04, data); + printk(BIOS_DEBUG, "force mPCIe clock enabled\n"); + } + } +} + +static void lpc_mcu_msg(void) +{ + unsigned int i, timeout; + const char *post_msg = "BIOSBOOT"; + unsigned char sync_byte = 0; + + if (!CONFIG(BOARD_PCENGINES_APU5)) + return; + + uart_init(1); + + for (i = 0; i < 4; i++) { + uart_tx_byte(1, 0xe1); + uart_tx_flush(1); + timeout = 10; + while (sync_byte != 0xe1) { + sync_byte = uart_rx_byte(1); + if (timeout == 0) { + uart_init(CONFIG_UART_FOR_CONSOLE); + udelay(10000); + printk(BIOS_ERR, "Failed to sync with LPC" + " MCU, number of retries %d\n", 3 - i); + udelay(10000); + uart_init(1); + udelay(10000); + break; + } + udelay(100); + timeout--; + } + if (sync_byte == 0xe1) + break; + } + + if (sync_byte != 0xe1) + return; + + uart_init(1); + timeout = 10; + + for (i = 0; i < strlen(post_msg); i++) + uart_tx_byte(1, *(post_msg + i)); + + uart_tx_byte(1, 0xe1); + uart_tx_flush(1); + + while (uart_rx_byte(1) != 0xe1) { + if (timeout == 0) { + uart_init(CONFIG_UART_FOR_CONSOLE); + printk(BIOS_ERR, "Did not receive response to BIOSBOOT\n"); + return; + } + udelay(100); + timeout--; + } + + uart_init(CONFIG_UART_FOR_CONSOLE); +} diff --git a/src/mainboard/pcengines/apu2/vboot-rw-ab.fmd b/src/mainboard/pcengines/apu2/vboot-rw-ab.fmd index 0bc93f11be7..c17402e6160 100644 --- a/src/mainboard/pcengines/apu2/vboot-rw-ab.fmd +++ b/src/mainboard/pcengines/apu2/vboot-rw-ab.fmd @@ -1,32 +1,28 @@ FLASH 8M { SI_BIOS@0x0 0x800000 { - RW_MISC@0x0 0x10000 { - RW_SHARED@0x0 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x4000 0x2000 - RW_NVRAM(PRESERVE)@0x6000 0x6000 - RW_ELOG(PRESERVE)@0xc000 0x4000 + MISC_RW@0x0 0xa0000 { + RW_UNUSED@0x0 0x1c000 + RW_VPD@0x1c000 0x4000 + PSPDIR@0x20000 0x80000 } - RW_SECTION_A@0x10000 0x1f8000 { + RW_SECTION_A@0xa0000 0x230000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x1e7fc0 - RW_FWID_A@0x1f7fc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x21ffc0 + RW_FWID_A@0x22ffc0 0x40 } - RW_SECTION_B@0x208000 0x1f8000 { + RW_SECTION_B@0x2d0000 0x230000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x1e7fc0 - RW_FWID_B@0x1f7fc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x21ffc0 + RW_FWID_B@0x22ffc0 0x40 } - WP_RO@0x400000 0x400000{ + WP_RO@0x500000 0x300000{ RO_VPD@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000{ + RO_SECTION@0x4000 0x2fc000{ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x30c000 + COREBOOT(CBFS)@0xf0000 0x20c000 } } } diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index 5ddfd8cfba0..adcb86b34fb 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -4,6 +4,5 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c -bootblock-y += state_machine.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index d943f13f10b..a865929d876 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -5,6 +5,5 @@ romstage-y += dimmSpd.c ramstage-y += iommu.c ramstage-y += northbridge.c -bootblock-y += state_machine.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index 5ddfd8cfba0..adcb86b34fb 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -4,6 +4,5 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c -bootblock-y += state_machine.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index 274e46b4d5e..b97b335b70d 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -5,6 +5,5 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c ramstage-y += iommu.c -bootblock-y += state_machine.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 398f31cc943..89dcad60860 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,7 +19,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO - select BOOT_DEVICE_SUPPORTS_WRITES config EHCI_BAR hex diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 811675286e3..feb930de283 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -36,7 +36,6 @@ romstage-y += smbus_spd.c romstage-$(CONFIG_HUDSON_UART) += uart.c verstage-y += early_setup.c -verstage-$(CONFIG_SPI_FLASH) += spi.c verstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index 88fa41243bc..a31b45b820d 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -2,18 +2,10 @@ #include #include -#include -#include #include #include #include -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - return (int)tmp; -} /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. * diff --git a/src/southbridge/amd/pi/hudson/spi.c b/src/southbridge/amd/pi/hudson/spi.c index e7deffc54f6..6e0ed5709e8 100644 --- a/src/southbridge/amd/pi/hudson/spi.c +++ b/src/southbridge/amd/pi/hudson/spi.c @@ -31,11 +31,13 @@ #define CNTRL02_EXEC_OPCODE (1 << 0) #define SPI_REG_CNTRL03 0x3 #define CNTRL03_SPIBUSY (1 << 7) -#define SPI_CMD_CODE 0x45 -#define SPI_TX_BYTE_COUNT 0x48 -#define SPI_RX_BYTE_COUNT 0x4b - -#define SPI_FIFO 0x80 +#define SPI_REG_FIFO 0xc +#define SPI_REG_CNTRL11 0xd + #define CNTRL11_FIFOPTR_MASK 0x07 +#define SPI_EXT_REG_INDX 0x1e + #define SPI_EXT_REG_TXCOUNT 0x5 + #define SPI_EXT_REG_RXCOUNT 0x6 +#define SPI_EXT_REG_DATA 0x1f #define AMD_SB_SPI_TX_LEN 64 @@ -51,6 +53,17 @@ static inline void spi_write(uint8_t reg, uint8_t val) write8((void *)(spibar + reg), val); } +static void reset_internal_fifo_pointer(void) +{ + uint8_t reg8; + + do { + reg8 = spi_read(SPI_REG_CNTRL02); + reg8 |= CNTRL02_FIFO_RESET; + spi_write(SPI_REG_CNTRL02, reg8); + } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); +} + static void execute_command(void) { uint8_t reg8; @@ -63,54 +76,60 @@ static void execute_command(void) (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY)); } - void spi_init(void) { -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); -#else - const struct device *dev = pcidev_on_root(0x14, 3); -#endif + struct device *dev; + dev = pcidev_on_root(0x14, 3); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; size_t count; - uint8_t cmd; - uint8_t *bufin = din; - const uint8_t *bufout = dout; - /* First byte is cmd which cannot be sent through FIFO */ - cmd = bufout[0]; - bufout++; bytesout--; /* * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not + * than the controller can handle. Iterations for writes are not * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands. + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. */ - if (bytesout + bytesin > AMD_SB_SPI_TX_LEN) { - printk(BIOS_ERR, "%s: FCH_SC: Too much to transfer, code error!\n", __func__); + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_WARNING, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); return -1; } - spi_write(SPI_CMD_CODE, cmd); + spi_write(SPI_EXT_REG_INDX, SPI_EXT_REG_TXCOUNT); + spi_write(SPI_EXT_REG_DATA, bytesout); + spi_write(SPI_EXT_REG_INDX, SPI_EXT_REG_RXCOUNT); + spi_write(SPI_EXT_REG_DATA, bytesin); - spi_write(SPI_TX_BYTE_COUNT, bytesout); - spi_write(SPI_RX_BYTE_COUNT, bytesin); + spi_write(SPI_REG_OPCODE, cmd); - for (count = 0; count < bytesout; count++) - spi_write(SPI_FIFO + count, bufout[count]); + reset_internal_fifo_pointer(); + for (count = 0; count < bytesout; count++, dout++) { + spi_write(SPI_REG_FIFO, *(uint8_t *)dout); + } + reset_internal_fifo_pointer(); execute_command(); - for (count = 0; count < bytesin; count++) - bufin[count] = spi_read(SPI_FIFO + (count + bytesout) % AMD_SB_SPI_TX_LEN); + reset_internal_fifo_pointer(); + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = spi_read(SPI_REG_FIFO); + } + + for (count = 0; count < bytesin; count++, din++) { + *(uint8_t *)din = spi_read(SPI_REG_FIFO); + } return 0; } diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 8a4aada4097..c5ad20e8810 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -78,7 +78,6 @@ CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) -CC_verstage := $(CC_verstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_64 := $(CC_x86_64) $(AGESA_INC) $(AGESA_CFLAGS)