From 92b590019c29c68cfbee05949bc94c3612ffc085 Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Thu, 31 Aug 2023 11:05:44 +0800 Subject: [PATCH 1/3] Adding ex_valid for ex to wb trigger + filter trace_id gpr updates when apu response --- bhv/cv32e40p_rvfi.sv | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40p_rvfi.sv index 03de9a058..97d2d269a 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40p_rvfi.sv @@ -1083,7 +1083,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; e_send_rvfi_trace_ex_1, e_send_rvfi_trace_ex_2, e_send_rvfi_trace_ex_3, - e_send_rvfi_trace_ex_4; + e_send_rvfi_trace_ex_4, + e_send_rvfi_trace_ex_5, + e_send_rvfi_trace_ex_6; event e_send_rvfi_trace_wb_1, e_send_rvfi_trace_wb_2, e_send_rvfi_trace_wb_3; event e_send_rvfi_trace_id_1; @@ -1391,7 +1393,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; `CSR_FROM_PIPE(ex, tdata2) tinfo_to_ex(); - if (r_pipe_freeze_trace.rf_we_wb) begin + if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port) begin if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_id.m_got_ex_reg)) begin trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; @@ -1409,7 +1411,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_ex.m_valid = 1'b0; ->e_send_rvfi_trace_ex_2; end else begin - if (r_pipe_freeze_trace.rf_we_wb) begin + if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port) begin ->e_dev_commit_rf_to_ex_1; if (trace_ex.m_got_ex_reg) begin trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; @@ -1434,10 +1436,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; minstret_to_ex(); end send_rvfi(trace_ex); + ->e_send_rvfi_trace_ex_6; end trace_ex.m_valid = 1'b0; end - end else if (r_pipe_freeze_trace.rf_we_wb && !s_was_flush) begin + end else if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port && !s_was_flush) begin ->e_dev_commit_rf_to_ex_2; if (trace_ex.m_got_ex_reg) begin trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; @@ -1452,7 +1455,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; end end - s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex); + s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex); //EX_STAGE if (trace_id.m_valid) begin mtvec_to_id(); @@ -1516,7 +1519,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_ex.m_valid = 1'b0; ->e_send_rvfi_trace_ex_3; end - if (r_pipe_freeze_trace.ex_reg_we && !r_pipe_freeze_trace.apu_rvalid) begin + if (r_pipe_freeze_trace.ex_reg_we && !s_apu_to_alu_port) begin trace_id.m_ex_fw = 1'b1; trace_id.m_rd_addr[0] = r_pipe_freeze_trace.ex_reg_addr; trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.ex_reg_wdata; @@ -1548,7 +1551,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_id.m_mem_req_id[0] = 0; end end - ->e_id_to_ex_1; hwloop_to_id(); trace_ex.move_down_pipe(trace_id); // The instruction moves forward from ID to EX trace_id.m_valid = 1'b0; @@ -1567,7 +1569,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_id.m_mem_req_id[0] = 0; end end - end + end //trace_if.m_valid //ID_STAGE if (s_new_valid_insn) begin // There is a new valid instruction @@ -1585,6 +1587,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_wb.move_down_pipe(trace_ex); end else begin send_rvfi(trace_ex); + ->e_send_rvfi_trace_ex_5; end end trace_ex.m_valid = 1'b0; From dc9c4177b91dcd42dd2aaa22fc5dbc61f2f36dde Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Thu, 31 Aug 2023 16:00:16 +0800 Subject: [PATCH 2/3] Better filtering between lsu and apu response --- bhv/cv32e40p_rvfi.sv | 9 ++++++--- bhv/cv32e40p_tb_wrapper.sv | 2 +- bhv/pipe_freeze_trace.sv | 2 ++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40p_rvfi.sv index 97d2d269a..4d964a3b7 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40p_rvfi.sv @@ -108,6 +108,7 @@ module cv32e40p_rvfi input logic apu_multicycle_i, input logic wb_contention_lsu_i, input logic wb_contention_i, + input logic regfile_we_lsu_i, input logic branch_in_ex_i, input logic branch_decision_ex_i, @@ -1072,7 +1073,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; //those event are for debug purpose event e_dev_send_wb_1, e_dev_send_wb_2; - event e_dev_commit_rf_to_ex_1, e_dev_commit_rf_to_ex_2, e_dev_commit_rf_to_ex_3; + event e_dev_commit_rf_to_ex_1, e_dev_commit_rf_to_ex_2, e_dev_commit_rf_to_ex_3, e_dev_commit_rf_to_ex_4, e_dev_commit_rf_to_ex_5; event e_if_2_id_1, e_if_2_id_2; event e_ex_to_wb_1, e_ex_to_wb_2; event e_id_to_ex_1, e_id_to_ex_2; @@ -1393,15 +1394,17 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; `CSR_FROM_PIPE(ex, tdata2) tinfo_to_ex(); - if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port) begin - if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_id.m_got_ex_reg)) begin + if (r_pipe_freeze_trace.regfile_we_lsu)begin//r_pipe_freeze_trace.rf_we_wb && (!s_apu_to_lsu_port || r_pipe_freeze_trace.wb_contention_lsu)) begin + if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg)) begin trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; trace_ex.m_got_first_data = 1'b1; + ->e_dev_commit_rf_to_ex_4; end else if (cnt_data_resp == trace_ex.m_mem_req_id[1]) begin trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb; trace_ex.m_got_first_data = 1'b1; + ->e_dev_commit_rf_to_ex_5; end end diff --git a/bhv/cv32e40p_tb_wrapper.sv b/bhv/cv32e40p_tb_wrapper.sv index 97fdfaa5f..be184867f 100644 --- a/bhv/cv32e40p_tb_wrapper.sv +++ b/bhv/cv32e40p_tb_wrapper.sv @@ -298,7 +298,7 @@ module cv32e40p_tb_wrapper .apu_multicycle_i (cv32e40p_top_i.core_i.ex_stage_i.apu_multicycle), .wb_contention_lsu_i(cv32e40p_top_i.core_i.ex_stage_i.wb_contention_lsu), .wb_contention_i (cv32e40p_top_i.core_i.ex_stage_i.wb_contention), - + .regfile_we_lsu_i (cv32e40p_top_i.core_i.ex_stage_i.regfile_we_lsu), // .rf_we_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_we_fw_i), // .rf_addr_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i), // .rf_wdata_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i), diff --git a/bhv/pipe_freeze_trace.sv b/bhv/pipe_freeze_trace.sv index 22bf17749..3635fd030 100644 --- a/bhv/pipe_freeze_trace.sv +++ b/bhv/pipe_freeze_trace.sv @@ -94,6 +94,7 @@ typedef struct { logic apu_multicycle; logic wb_contention_lsu; logic wb_contention; + logic regfile_we_lsu; logic branch_in_ex; logic branch_decision_ex; @@ -437,6 +438,7 @@ task monitor_pipeline(); r_pipe_freeze_trace.apu_multicycle = apu_multicycle_i; r_pipe_freeze_trace.wb_contention_lsu = wb_contention_lsu_i; r_pipe_freeze_trace.wb_contention = wb_contention_i; + r_pipe_freeze_trace.regfile_we_lsu = regfile_we_lsu_i; r_pipe_freeze_trace.branch_in_ex = branch_in_ex_i; r_pipe_freeze_trace.branch_decision_ex = branch_decision_ex_i; From 5ee93bfea5407b3b94f716bdb20ee86c57fd9be6 Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Thu, 31 Aug 2023 16:07:32 +0800 Subject: [PATCH 3/3] Verible --- bhv/cv32e40p_rvfi.sv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40p_rvfi.sv index 4d964a3b7..cd1cf6f75 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40p_rvfi.sv @@ -1073,7 +1073,12 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; //those event are for debug purpose event e_dev_send_wb_1, e_dev_send_wb_2; - event e_dev_commit_rf_to_ex_1, e_dev_commit_rf_to_ex_2, e_dev_commit_rf_to_ex_3, e_dev_commit_rf_to_ex_4, e_dev_commit_rf_to_ex_5; + event + e_dev_commit_rf_to_ex_1, + e_dev_commit_rf_to_ex_2, + e_dev_commit_rf_to_ex_3, + e_dev_commit_rf_to_ex_4, + e_dev_commit_rf_to_ex_5; event e_if_2_id_1, e_if_2_id_2; event e_ex_to_wb_1, e_ex_to_wb_2; event e_id_to_ex_1, e_id_to_ex_2; @@ -1394,17 +1399,16 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; `CSR_FROM_PIPE(ex, tdata2) tinfo_to_ex(); - if (r_pipe_freeze_trace.regfile_we_lsu)begin//r_pipe_freeze_trace.rf_we_wb && (!s_apu_to_lsu_port || r_pipe_freeze_trace.wb_contention_lsu)) begin + if (r_pipe_freeze_trace.regfile_we_lsu) begin + ->e_dev_commit_rf_to_ex_4; if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg)) begin trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; trace_ex.m_got_first_data = 1'b1; - ->e_dev_commit_rf_to_ex_4; end else if (cnt_data_resp == trace_ex.m_mem_req_id[1]) begin trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb; trace_ex.m_got_first_data = 1'b1; - ->e_dev_commit_rf_to_ex_5; end end