diff --git a/components/MMU/MMUImpl.cpp b/components/MMU/MMUImpl.cpp
index c157a17d..9d21d6bb 100644
--- a/components/MMU/MMUImpl.cpp
+++ b/components/MMU/MMUImpl.cpp
@@ -16,13 +16,7 @@
 #include <core/performance/profile.hpp>
 #include <core/qemu/configuration_api.hpp>
 #include <fstream>
-#include <functional>
 #include <iostream>
-#include <map>
-#include <queue>
-#include <sstream>
-#include <unordered_map>
-#include <vector>
 
 #define DBG_DefineCategories MMU
 #define DBG_SetDefaultOps    AddCat(MMU)
@@ -64,16 +58,6 @@ class FLEXUS_COMPONENT(MMU)
     struct TLBentry
     {
 
-        friend class boost::serialization::access;
-
-        template<class Archive>
-        void serialize(Archive& ar, const unsigned int version)
-        {
-            ar & theRate;
-            ar & theVaddr;
-            ar & thePaddr;
-        }
-
         TLBentry() {}
 
         TLBentry(VirtualMemoryAddress aVAddress, PhysicalMemoryAddress aPaddress, uint64_t aRate)
@@ -105,15 +89,6 @@ class FLEXUS_COMPONENT(MMU)
     struct TLB
     {
 
-        friend class boost::serialization::access;
-
-        template<class Archive>
-        void serialize(Archive& ar, const unsigned int version)
-        {
-            ar & theTLB;
-            ar & theSize;
-        }
-
         void loadState(json checkpoint)
         {
             size_t size = checkpoint["capacity"];
@@ -244,6 +219,7 @@ class FLEXUS_COMPONENT(MMU)
             PAGEMASK = ~((1 << theMMU->Gran0->getlogKBSize()) - 1);
             ret      = true;
         }
+
         return ret;
     }
 
diff --git a/components/MMU/mmuRegisters.hpp b/components/MMU/mmuRegisters.hpp
index e7830421..23f0b7b7 100644
--- a/components/MMU/mmuRegisters.hpp
+++ b/components/MMU/mmuRegisters.hpp
@@ -72,27 +72,5 @@ struct mmu_regs_t
     mmu_reg_t ID_AA64MMFR0_EL1; // only implemented in EL1 as far as I know.
 };
 
-/* type      -      ARM_NAME            - funct.
- * ----DO NOT REMOVE---- PEOPLE WILL NEED TO KNOW THIS *
- mmu_reg_t           SCTLR_EL1;          // enables/disables Secure EL1/EL0
-translation mmu_reg_t           SCTLR_EL2;          // enables/disables
-Non-Secure EL2 Stage 1, Non-Secure EL1/EL0 Stage 2 mmu_reg_t SCTLR_EL3; //
-enables/disables Secure EL3 Stage 1
-// all SCTLRs also include cacheability bits for PTEs
-
-mmu_reg_t           TCR_EL1;            // controls Secure/NonSecure EL1/EL0
-mmu_reg_t           TCR_EL2;            // controls Secure EL2Stg1 and
-Non-Secure EL1/EL0 Stage 2 mmu_reg_t           TCR_EL3;            // controls
-Secure EL3 Stage 1
-
-mmu_reg_t           TTBR0_EL1;          // controls lower address range for
-EL1 (default 0x0 - 0xffff ffff ffff), configurable through TCR_ELx.T0SZ
-mmu_reg_t           TTBR1_EL1;          // upper address range for EL1, size
-also configurable through TCR_ELx.T1SZ mmu_reg_t           TTBR0_EL3; //
-controls single address range for EL3 mmu_reg_t           TTBR0_EL2; //
-controls lower address range for EL2 (default 0x0 - 0xffff ffff ffff), config.
-as above mmu_reg_t           TTBR1_EL2;          // upper address range for
-EL2
- * ----DO NOT REMOVE---- PEOPLE WILL NEED TO KNOW THIS */
 
 #endif // FLEXUS_ARM_MMU_REGISTERS_HPP_INCLUDED