From 4bd74e3af4ebea70d3eaa09ed563cdbbc3de5040 Mon Sep 17 00:00:00 2001 From: hpollittsmith Date: Mon, 17 May 2021 20:53:55 -0400 Subject: [PATCH 1/4] Added April 21 HW TG notes Signed-off-by: hpollittsmith --- .../2021-04-21/2021-04-21_minutes.md | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md diff --git a/hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md b/hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md new file mode 100644 index 000000000..6f24e188f --- /dev/null +++ b/hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md @@ -0,0 +1,45 @@ +# HW TG Meeting: April 21, 2021 + +## Attendees: +- Hugh Pollitt-Smith +- Duncan Bees +- Arjan Bink +- Davide Schiavone +- Jeremy Bennett +- Olive Zhao +- Rick O’Connor +- Tim Saxe +- Vincent Cui +- Yunhai Shang + +## Agenda: +- Alibaba CSI HAL +- CORE-V-MCU Project + + + ##Discussion notes: + +### Alibaba CSI HAL: + * Vincent and Yunhai presented Alibaba’s THEAD CSI interface + * CSI is based on CMSIS, but further developed by Alibaba to fit their own requirements + * It appears the environment is big, complex—how well will this work on small chips like cv32e40p/x/s, or OSs like FreeRTOS; for CORE-V-MCU, we’re looking for abstraction of the lowest level of the hardware layer + * Current system supports Alibaba RTOS + * This should support multiple operating systems, including FreeRTOS, Zephyr; also other OSes, devices for CORE-V; we don’t want to lock developers into a particular RTOS; FreeRTOS is a current need for CORE-V-MCU + * Tim is interested to look at further, if there is a repo someone can point him to + * User Guide is currently in Mandarin only; Yunhai will share with Olive and Tim + * Olive can assess the level of effort to port CSI to the current CORE-V-MCU FPGA emulation + * Quicklogic have done their own HAL for CORE-V-MCU, but will switch to whatever SW TG comes up with + * Open question whether to push out emulation with current HAL or wait; don’t want to send people down the wrong path at the beginning + * There will not likely be a single HAL; CMSIS—lots of adoption already, but unlikely to be architecture agnostic; NMSIS — a few vendors getting together to advance it as an option; Alibaba with CSI + * For OpenHW, we should base decisions on community adoption, volume of support around different initiatives, consider what will help with adoption of the HW; is it for OpenHW Group to lead, follow, or wait for dust to settle and then implement? + * Adopt a direction that is well-supported, driven by existence of adoption and volume; count architectures that have used the various implementations; put a matrix table together of options, position in industry, pros/cons for support by OpenHW + * Adoption is important, but also willingness to move to CORE-V; someone will need to pony up effort to move to CORE-V and provide support + * We want to follow the direction of RISC-V International + * Yunhai will lead this effort through the SW TG; first step will be a survey of available options (May); build consensus and way forward, leading to format proposal (June) + + + +### CORE-V-MCU SOC/FPGA project update: + + * Duncan showed the current Project Plan spreadsheet; task breakdown is complete, but needs more details (start/complete dates) to get into shape for Monday’s TWG; Duncan, Tim, Hugh will meet to fill out checklist before Monday + From 04e48c1e65c0813e74a0ba3b56a697eec1fcbb97 Mon Sep 17 00:00:00 2001 From: hpollittsmith Date: Mon, 17 May 2021 20:57:47 -0400 Subject: [PATCH 2/4] Amended April 21 HW TG notes Signed-off-by: hpollittsmith --- hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md b/hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md index 6f24e188f..c6ae28b5c 100644 --- a/hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md +++ b/hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md @@ -30,9 +30,9 @@ * Olive can assess the level of effort to port CSI to the current CORE-V-MCU FPGA emulation * Quicklogic have done their own HAL for CORE-V-MCU, but will switch to whatever SW TG comes up with * Open question whether to push out emulation with current HAL or wait; don’t want to send people down the wrong path at the beginning - * There will not likely be a single HAL; CMSIS—lots of adoption already, but unlikely to be architecture agnostic; NMSIS — a few vendors getting together to advance it as an option; Alibaba with CSI - * For OpenHW, we should base decisions on community adoption, volume of support around different initiatives, consider what will help with adoption of the HW; is it for OpenHW Group to lead, follow, or wait for dust to settle and then implement? - * Adopt a direction that is well-supported, driven by existence of adoption and volume; count architectures that have used the various implementations; put a matrix table together of options, position in industry, pros/cons for support by OpenHW + * There will not likely be a single HAL; CMSIS—lots of adoption already, but unlikely to be architecture agnostic; NMSIS — a few vendors getting together to advance it as an option; Alibaba with CSI + * For OpenHW, we should base decisions on community adoption, volume of support around different initiatives, consider what will help with adoption of the HW; is it for OpenHW Group to lead, follow, or wait for dust to settle and then implement? + * Adopt a direction that is well-supported, driven by existence of adoption and volume; count architectures that have used the various implementations; put a matrix table together of options, position in industry, pros/cons for support by OpenHW * Adoption is important, but also willingness to move to CORE-V; someone will need to pony up effort to move to CORE-V and provide support * We want to follow the direction of RISC-V International * Yunhai will lead this effort through the SW TG; first step will be a survey of available options (May); build consensus and way forward, leading to format proposal (June) From 5aabc6975ebb475540a2e47d4310b9a5ea0552d3 Mon Sep 17 00:00:00 2001 From: hpollittsmith Date: Thu, 20 May 2021 12:19:16 -0400 Subject: [PATCH 3/4] Added May 19, 2021 HW TG minutes Signed-off-by: hpollittsmith --- .../2021-05-19/2021-05-19_minutes.md | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 hw/MeetingMinutes/2021-05-19/2021-05-19_minutes.md diff --git a/hw/MeetingMinutes/2021-05-19/2021-05-19_minutes.md b/hw/MeetingMinutes/2021-05-19/2021-05-19_minutes.md new file mode 100644 index 000000000..efcee6098 --- /dev/null +++ b/hw/MeetingMinutes/2021-05-19/2021-05-19_minutes.md @@ -0,0 +1,54 @@ +# HW TG May 19 Meeting: + +## Attendees: +- Hugh Pollitt-Smith +- Anthony Le +- Li Chen +- Duncan Bees +- Florain Zaruba +- Greg Martin +- Jeremy Bennett +- Mike Thompson +- Olive Zhao +- Randy Oyadomari +- Rick O’Connor +- Tim Saxe + + +## Agenda and discussion: + + +## 1. CORE-V-MCU Verilator + + * Jeremy has picked up the work from Florian, created a simple loop that puts the processor through reset and then runs the clock + * Performance is low (30kHz—the PULP model runs at 800kHz with some tuning) + * Concern about the number of warnings when running Verilator + * 944 warnings + * Need an action to deal with all the warnings; Jeremy will raise the issue in Github and we can triage from there + * Next step is to replace simple test bench with debug server (Embdebug); there appears to be a gap in the documentation regarding what the JTAG registers mean + * Florian suggested Jeremy open an issue to fix the documentation + * The JTAG registers are described in the RISC-V Debug Specification 0.13 (Section 6.1 Debug Transport Module) + * Randy from QuickLogic will bring up Verilator for CI; boot from a ROM and run tests + * Jeremy, Duncan, Randy, and Florian will update the project concept document; agreed to meet on Friday for further discussion + + +## 2. CORE-V-MCU Verification IP + + * We discussed Mike’s research and recommendations on Verification IP needs for CORE-V-MCU + * Overall, it’s a fairly bleak landscape on what is ready available + * There should be an effort to get fully-verified peripherals that anyone can use + * The block diagram on Slide 2 currently doesn’t exist; we emulate on FPGA, which is not satisfactory for CI purposes + * We can put some peripherals into a kind of loopback mode + * Hook UART1 TX to UART2 RX + * I2C master can talk to I2C slave + * Build a simple behavioural model for QSPI (write 4 bytes, read 4 bytes) + * For camera, use PWM output to generate sync signals, and use GPIO for data + * JTAG debug model is coming from Jeremy + * SDIO still needs a solution
 + * Does Renode fit into this picture? AntMicro may have some models for these peripherals + * Tim can ask if they have models + * We want to ensure models are written in Verilog so they can be used in a variety of simulators + * Start with simple models that get more interesting over time + * Action: create a test bench directory in core-v-mcu repo with subdirectories for each component (uart, etc.) + * One day, these may get migrated to separate repos and become a reference set; OpenHW Group can become the place for high quality open source VIP + * Mike will post updated version of his slides to reflect feedback From 59cd12b3cf098ce425fc97c9066edba02358461d Mon Sep 17 00:00:00 2001 From: hpollittsmith Date: Thu, 24 Jun 2021 08:38:33 -0400 Subject: [PATCH 4/4] Added June 16 TW TG minutes Signed-off-by: hpollittsmith --- .../2021-06-16/2021-06-16_minutes.md | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 hw/MeetingMinutes/2021-06-16/2021-06-16_minutes.md diff --git a/hw/MeetingMinutes/2021-06-16/2021-06-16_minutes.md b/hw/MeetingMinutes/2021-06-16/2021-06-16_minutes.md new file mode 100644 index 000000000..51b061512 --- /dev/null +++ b/hw/MeetingMinutes/2021-06-16/2021-06-16_minutes.md @@ -0,0 +1,49 @@ +# HW TG - June 16, 2021 + +## Attendees: +- Hugh Pollitt-Smith +- Anthony Le +- Arjan Bink +- Li Chen +- Davide Schiavone +- Duncan Bees +- Florian Zaruba +- Greg Martin +- Zongru Li +- Olive Zhao +- Richard Barry +- Rick O’Connor +- Tim Saxe + +## Agenda: +1. Introductory presentation by Dr. Li Chen, University of Saskatchewan + * Li’s research is in radiation tolerant/hardened ASICs, including microprocessors; has an interest to implement CV32E40P-based platform using rad-hard libraries + * Li was not sure about the complexity of core-v-mcu versus PULPissimo + * Core-v-mcu is designed to be parametrizable, and it should be straightforward to strip the platform down to a minimal set of elements (no eFPGA, minimal I/O) + * Greg (QuickLogic) can advise on how to do this; Tim can setup call with Li and his students and Greg to discuss +2. Regression/CI discussion + * Richard (AWS) wants to setup a core-v-mcu board in their remote test lab along with several other RISC-V chips to run CI tests for FreeRTOS every evening + * Aim is to have one FreeRTOS kernel port across multiple RISC-V cores + * For core-v-mcu, the FPGA platform (Digilent NexsyA7-100T, Genesys2) is fine; noted that Genesys2 will eventually support the 64-bit core as well + * Need to be able to remote flash the device, observe output (e.g., UART) to see if tests pass or fail + * Hugh will send Richard info on the boards and components required for setup + * This is similar to what QuickLogic have setup already with NexysA7-100T board + * Eventually this would also support the core-v-mcu SOC development board + * Amazon has FPGAs in the cloud also—would they want to use those? Probably not for Richard’s CI/CD, but could be useful to expose to other people + * Cloud CI/CD is handled by another AWS person who is off this month; he would know about cloud-hosted FPGA + * Florian took an action to setup a discussion for technical issues +3. Integrating CV32E40S with core-v-mcu + * CV32E40S core is in development, led by Silabs; 32-bit embedded class core with security features/extensions + * Project team is assessing if there is interest to have core integrated in core-v-mcu + * Intent is not to impact the current core-v-mcu tape-out with CV32E40P (Fall 2021) + * QuickLogic is working to have core-v-mcu parameterized to make the back-end flows easier to manage; would need to understand if this is a total rework, or if this can be handled via parameters/options + * Unibo team is working on a CV32E40S test chip, not under OpenHW Group + * Li Chen is interested in potentially implementing with his rad-hard library; this could be a good candidate project for the OpenHW Accelerate program +4. Core-v-mcu project + * Anthony (QuickLogic) presented development board specs/options, and will post slides + * It is beneficial to make distinction between an eval board with I/O isolation and test points, versus a development kit; OpenHW wants to build development kits in some volume (up to 10000) that is focussed on SW developers + * Characterization/eval board 10-20 boards, several 1000s per run; ~$1000 each + * Could be a 2-board solution + * Researchers in CMC’s community would probably be interested in doing power measurements, etc., versus pure software development + * CMC will manufacture and sell the boards + * Development kit should offer over air update