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Incorrect DCSR value read/ written #443

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shetalani opened this issue Aug 6, 2020 · 1 comment
Closed

Incorrect DCSR value read/ written #443

shetalani opened this issue Aug 6, 2020 · 1 comment
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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@shetalani
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RISC-V Specification:

  • 4.8.1

Issue Description:

Bits [27:16], [14] and [5] of DCSR should be tied to zero as specified in the spec.

Example:

As shown below, the instruction 32'h7b0027f3 (CSRRSI X15, DCSR, X0) is decoded at time point t##0, where dcsr_q.zero2 is read as 12'h800 at t##1. Same goes for dcsr_q.zero1 or dcsr_q.zero0.

DCSR_zero

Top Level Parameters

cv32e40p_core #(
    .FPU                      ( 0 ),
    .NUM_MHPMCOUNTERS         ( 1 ),
    .PULP_CLUSTER             ( 0 ),
    .PULP_XPULP               ( 0 ),
    .PULP_ZFINX               ( 0 )
) 

Product: OneSpin 360 DV-Verify
App: RVV
Tool's version: 2020.1.4

@Silabs-ArjanB Silabs-ArjanB added Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system labels Aug 10, 2020
@Silabs-ArjanB Silabs-ArjanB added the Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation label Sep 8, 2020
@Silabs-ArjanB
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Hi @shetalani This issue should have been fixed now after the merge of #483 . Could you please check again and close this issue if fixed now?

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Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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