From 692165c35a44039650f345d5bb8339c637d7f9e7 Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Thu, 7 Sep 2023 14:35:46 +0800 Subject: [PATCH 1/2] Adding memory access to rvfi trace log --- bhv/cv32e40p_rvfi.sv | 5 ++++- bhv/cv32e40p_rvfi_trace.sv | 24 +++++++++++++++++++++++- bhv/cv32e40p_tb_wrapper.sv | 7 ++++++- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40p_rvfi.sv index b8fae0ff5..7f35f523b 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40p_rvfi.sv @@ -1540,12 +1540,15 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; cnt_data_req = cnt_data_req + 1; end if (!r_pipe_freeze_trace.data_we_ex) begin - trace_id.m_is_load = 1'b1; + trace_id.m_is_load = 1'b1; + trace_id.m_mem.wmask = '1; if (r_pipe_freeze_trace.data_misaligned) begin trace_id.m_data_missaligned = 1'b1; trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; trace_id.m_mem_req_id[0] = cnt_data_req; end + end else begin + trace_id.m_mem.rmask = '1; end if (trace_id.m_got_ex_reg) begin // Shift index 0 to 1 trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; diff --git a/bhv/cv32e40p_rvfi_trace.sv b/bhv/cv32e40p_rvfi_trace.sv index 6ed4b773e..cdd34f5e3 100644 --- a/bhv/cv32e40p_rvfi_trace.sv +++ b/bhv/cv32e40p_rvfi_trace.sv @@ -53,7 +53,13 @@ module cv32e40p_rvfi_trace input logic rvfi_frs1_rvalid, input logic rvfi_frs2_rvalid, input logic [31:0] rvfi_frs1_rdata, - input logic [31:0] rvfi_frs2_rdata + input logic [31:0] rvfi_frs2_rdata, + + input logic [31:0] rvfi_mem_addr, + input logic [ 3:0] rvfi_mem_rmask, + input logic [ 3:0] rvfi_mem_wmask, + input logic [31:0] rvfi_mem_rdata, + input logic [31:0] rvfi_mem_wdata ); import cv32e40p_tracer_pkg::*; @@ -166,6 +172,21 @@ instr_trace_t trace_retire; end endfunction : apply_reg_write + function void apply_mem_access(); + mem_acc_t mem_acc; + + mem_acc.addr = rvfi_mem_addr; + if (rvfi_mem_wmask) begin + mem_acc.we = 1'b1; + mem_acc.wdata = rvfi_mem_wdata; + trace_retire.mem_access.push_back(mem_acc); + end else if (rvfi_mem_rmask) begin + mem_acc.we = 1'b0; + mem_acc.wdata = 'x; + trace_retire.mem_access.push_back(mem_acc); + end + endfunction : apply_mem_access + // cycle counter always_ff @(posedge clk_i, negedge rst_ni) begin if (rst_ni == 1'b0) cycles <= 0; @@ -176,6 +197,7 @@ instr_trace_t trace_retire; if (rvfi_valid) begin trace_retire = trace_new_instr(); apply_reg_write(); + apply_mem_access(); trace_retire.printInstrTrace(); end end diff --git a/bhv/cv32e40p_tb_wrapper.sv b/bhv/cv32e40p_tb_wrapper.sv index be184867f..bde9dd5af 100644 --- a/bhv/cv32e40p_tb_wrapper.sv +++ b/bhv/cv32e40p_tb_wrapper.sv @@ -457,7 +457,12 @@ module cv32e40p_tb_wrapper .rvfi_frs1_rvalid(rvfi_frs1_rvalid), .rvfi_frs2_rvalid(rvfi_frs2_rvalid), .rvfi_frs1_rdata(rvfi_frs1_rdata), - .rvfi_frs2_rdata(rvfi_frs2_rdata) + .rvfi_frs2_rdata(rvfi_frs2_rdata), + .rvfi_mem_addr(rvfi_mem_addr), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata) ); `endif // Instantiate the Core and the optinal FPU From d85ea9976a4a65635c0f1946b8f9663877b55583 Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Tue, 12 Sep 2023 10:37:11 +0800 Subject: [PATCH 2/2] RVFI - Better mask for memory access --- bhv/cv32e40p_rvfi.sv | 28 +++++++++++++++------------- bhv/cv32e40p_tb_wrapper.sv | 2 ++ bhv/pipe_freeze_trace.sv | 2 ++ 3 files changed, 19 insertions(+), 13 deletions(-) diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40p_rvfi.sv index 7f35f523b..4d8a537ac 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40p_rvfi.sv @@ -158,6 +158,8 @@ module cv32e40p_rvfi input logic lsu_ready_ex_i, input logic lsu_ready_wb_i, + input logic [3:0] lsu_data_be_i, + input logic data_req_pmp_i, input logic data_gnt_pmp_i, input logic data_rvalid_i, @@ -723,17 +725,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; end end - - //FOR DEBUG!!!!!!!!!!!!!!!!!!!!!! - // if(new_rvfi_trace.m_order == 64'h0000_0000_0000_4423) begin - // new_rvfi_trace.m_csr.mcause_rdata = 32'h8000_0010; - // new_rvfi_trace.m_csr.mcause_wdata = 32'h8000_0010; - // new_rvfi_trace.m_csr.mstatus_rdata = 32'h0000_1888; - // new_rvfi_trace.m_csr.mstatus_wdata = 32'h0000_1888; - // new_rvfi_trace.m_csr.mepc_rdata = 32'h0000_554E; - // new_rvfi_trace.m_csr.mepc_wdata = 32'h0000_554E; - // end - rvfi_order = new_rvfi_trace.m_order; rvfi_pc_rdata = new_rvfi_trace.m_pc_rdata; rvfi_insn = new_rvfi_trace.m_insn; @@ -1192,6 +1183,17 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; `CSR_FROM_PIPE(id, dpc) endfunction + function logic [31:0] be_to_mask(logic [3:0] be); + logic [31:0] mask; + mask[7:0] = be[0] ? 8'hFF : 8'h00; + mask[15:8] = be[0] ? 8'hFF : 8'h00; + mask[23:16] = be[0] ? 8'hFF : 8'h00; + mask[31:24] = be[0] ? 8'hFF : 8'h00; + + be_to_mask = mask; + return mask; + endfunction + task compute_pipeline(); bit s_new_valid_insn; bit s_ex_valid_adjusted; @@ -1541,14 +1543,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; end if (!r_pipe_freeze_trace.data_we_ex) begin trace_id.m_is_load = 1'b1; - trace_id.m_mem.wmask = '1; + trace_id.m_mem.wmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be); //'1; if (r_pipe_freeze_trace.data_misaligned) begin trace_id.m_data_missaligned = 1'b1; trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; trace_id.m_mem_req_id[0] = cnt_data_req; end end else begin - trace_id.m_mem.rmask = '1; + trace_id.m_mem.rmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be); //'1; end if (trace_id.m_got_ex_reg) begin // Shift index 0 to 1 trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; diff --git a/bhv/cv32e40p_tb_wrapper.sv b/bhv/cv32e40p_tb_wrapper.sv index bde9dd5af..8891a85b0 100644 --- a/bhv/cv32e40p_tb_wrapper.sv +++ b/bhv/cv32e40p_tb_wrapper.sv @@ -325,6 +325,8 @@ module cv32e40p_tb_wrapper .lsu_ready_ex_i (cv32e40p_top_i.core_i.lsu_ready_ex), .lsu_ready_wb_i (cv32e40p_top_i.core_i.lsu_ready_wb), + .lsu_data_be_i(cv32e40p_top_i.core_i.load_store_unit_i.data_be), + .data_req_pmp_i(cv32e40p_top_i.core_i.data_req_pmp), .data_gnt_pmp_i(cv32e40p_top_i.core_i.data_gnt_pmp), .data_rvalid_i(cv32e40p_top_i.core_i.data_rvalid_i), diff --git a/bhv/pipe_freeze_trace.sv b/bhv/pipe_freeze_trace.sv index 3635fd030..e557479df 100644 --- a/bhv/pipe_freeze_trace.sv +++ b/bhv/pipe_freeze_trace.sv @@ -143,6 +143,7 @@ typedef struct { logic p_elw_finish; logic lsu_ready_ex; logic lsu_ready_wb; + logic [3:0] lsu_data_be; logic data_req_pmp; logic data_gnt_pmp; logic data_rvalid; @@ -487,6 +488,7 @@ task monitor_pipeline(); r_pipe_freeze_trace.p_elw_finish = p_elw_finish_i; r_pipe_freeze_trace.lsu_ready_ex = lsu_ready_ex_i; r_pipe_freeze_trace.lsu_ready_wb = lsu_ready_wb_i; + r_pipe_freeze_trace.lsu_data_be = lsu_data_be_i; r_pipe_freeze_trace.data_req_pmp = data_req_pmp_i; r_pipe_freeze_trace.data_gnt_pmp = data_gnt_pmp_i;