diff --git a/riscv_simchecker.sv b/riscv_simchecker.sv
index dd83f05b2..f361a6fe5 100644
--- a/riscv_simchecker.sv
+++ b/riscv_simchecker.sv
@@ -42,8 +42,8 @@ module riscv_simchecker
 
   input  logic        fetch_enable,
   input  logic [31:0] boot_addr,
-  input  logic [4:0]  core_id,
-  input  logic [4:0]  cluster_id,
+  input  logic [3:0]  core_id,
+  input  logic [5:0]  cluster_id,
 
   input  logic [15:0] instr_compressed,
   input  logic        if_valid,
diff --git a/riscv_tracer.sv b/riscv_tracer.sv
index f9fa173d8..2f8002971 100644
--- a/riscv_tracer.sv
+++ b/riscv_tracer.sv
@@ -31,8 +31,8 @@ module riscv_tracer
   input  logic        rst_n,
 
   input  logic        fetch_enable,
-  input  logic [4:0]  core_id,
-  input  logic [4:0]  cluster_id,
+  input  logic [3:0]  core_id,
+  input  logic [5:0]  cluster_id,
 
   input  logic [31:0] pc,
   input  logic [31:0] instr,