diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv
index 4479c2628a..7460274155 100644
--- a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv
+++ b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv
@@ -291,11 +291,6 @@ function void uvme_cv32e40p_cfg_c::pre_randomize();
       zero_stall_sim = 1;
       zero_stall_sim.rand_mode(0);
 
-      // Hack-set is_stall_sim bit in step_compare
-      retval = uvm_hdl_deposit("uvmt_cv32e40p_tb.step_compare.is_stall_sim", 0);
-      if (!retval) begin
-         `uvm_fatal("ZEROSTALL", "Cannot set is_stall_sim in step_compare")
-      end
    end
    else if ($test$plusargs("max_data_zero_instr_stall")) begin
       // No stalls on the I bus, max on D bus
diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk
index 79595322b1..f56be91b8e 100644
--- a/cv32e40p/sim/ExternalRepos.mk
+++ b/cv32e40p/sim/ExternalRepos.mk
@@ -15,10 +15,9 @@ export SHELL = /bin/bash
 
 CV_CORE_REPO   ?= https://github.com/openhwgroup/cv32e40p
 CV_CORE_BRANCH ?= dev
-CV_CORE_HASH   ?= f08fe74f8cfacda5ec6883adc689e827ea562ca7
+CV_CORE_HASH   ?= 4d960913d69e2043df80ac249ea17a008b67aaa6
 CV_CORE_TAG    ?= none
 
-
 # The CV_CORE_HASH above points to version of the RTL that is newer.
 # It is logically equivalent with respect to v1.0.0 RTL freeze version with all parameters disabled.
 # There are some implementation and testbench updates in the above hash.
diff --git a/cv32e40p/sim/uvmt/Makefile b/cv32e40p/sim/uvmt/Makefile
index ba049af273..11f0b84584 100644
--- a/cv32e40p/sim/uvmt/Makefile
+++ b/cv32e40p/sim/uvmt/Makefile
@@ -49,8 +49,6 @@ export CORE_V_VERIF   = $(abspath $(MAKE_PATH)/../../..)
 export CV_CORE       ?= cv32e40p
 
 DPI_DASM_SPIKE_REPO  ?= https://github.com/riscv/riscv-isa-sim.git
-CV_SW_TOOLCHAIN      ?= /opt/riscv
-CV_SW_PREFIX         ?= " "
 
 include ../ExternalRepos.mk
 include $(CORE_V_VERIF)/mk/uvmt/uvmt.mk
diff --git a/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv b/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv
index 634d992765..357643663e 100644
--- a/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv
+++ b/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv
@@ -23,10 +23,10 @@ module cv32e40p_tb_wrapper
                 DM_HALTADDRESS    = 32'h1A11_0800,
                 HART_ID           = 32'h0000_0000,
                 // Parameters used by DUT
-                PULP_XPULP        = 0,
-                PULP_CLUSTER      = 0,
+                COREV_PULP        = 0,
+                COREV_CLUSTER     = 0,
                 FPU               = 0,
-                PULP_ZFINX        = 0,
+                ZFINX             = 0,
                 NUM_MHPMCOUNTERS  = 1
     )
     (input logic         clk_i,
@@ -72,10 +72,10 @@ module cv32e40p_tb_wrapper
 //    // MIKET: commenting out as the cv32e40p RTL wrapper does this as well.
 //    cv32e40p_core_log
 //     #(
-//          .PULP_XPULP            ( PULP_XPULP            ),
-//          .PULP_CLUSTER          ( PULP_CLUSTER          ),
+//          .COREV_PULP            ( COREV_PULP            ),
+//          .COREV_CLUSTER         ( COREV_CLUSTER         ),
 //          .FPU                   ( FPU                   ),
-//          .PULP_ZFINX            ( PULP_ZFINX            ),
+//          .ZFINX                 ( ZFINX                 ),
 //          .NUM_MHPMCOUNTERS      ( NUM_MHPMCOUNTERS      ))
 //    core_log_i(
 //          .clk_i              ( cv32e40p_core_i.id_stage_i.clk              ),
@@ -87,10 +87,10 @@ module cv32e40p_tb_wrapper
 
     // instantiate the core
     cv32e40p_core #(
-                 .PULP_XPULP       (PULP_XPULP),
-                 .PULP_CLUSTER     (PULP_CLUSTER),
+                 .COREV_PULP       (COREV_PULP),
+                 .COREV_CLUSTER    (COREV_CLUSTER),
                  .FPU              (FPU),
-                 .PULP_ZFINX       (PULP_ZFINX),
+                 .ZFINX            (ZFINX),
                  .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS)
                 )
     cv32e40p_core_i
diff --git a/cv32e40p/tb/core/tb_riscv/tb_riscv_core.sv b/cv32e40p/tb/core/tb_riscv/tb_riscv_core.sv
index 620800a771..f82c3ff50c 100644
--- a/cv32e40p/tb/core/tb_riscv/tb_riscv_core.sv
+++ b/cv32e40p/tb/core/tb_riscv/tb_riscv_core.sv
@@ -34,7 +34,7 @@ module tb_riscv_core
   parameter INSTR_RDATA_WIDTH   = 32,
   parameter PULP_SECURE         =  0,
   parameter N_PMP_ENTRIES       = 16,
-  parameter PULP_CLUSTER        =  1,
+  parameter COREV_CLUSTER       =  1,
   parameter FPU                 =  0,
   parameter SHARED_FP           =  0,
   parameter SHARED_DSP_MULT     =  0,
diff --git a/cv32e40p/tb/core/tb_top_verilator.sv b/cv32e40p/tb/core/tb_top_verilator.sv
index 195ec6aaf9..32d7d096bf 100644
--- a/cv32e40p/tb/core/tb_top_verilator.sv
+++ b/cv32e40p/tb/core/tb_top_verilator.sv
@@ -89,9 +89,9 @@ module tb_top_verilator
         #(.INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH),
           .RAM_ADDR_WIDTH    (RAM_ADDR_WIDTH),
           .BOOT_ADDR         (BOOT_ADDR),
-          .PULP_CLUSTER      (0),
+          .COREV_CLUSTER     (0),
           .FPU               (0),
-          .PULP_ZFINX        (0),
+          .ZFINX             (0),
           .DM_HALTADDRESS    (32'h1A110800)
          )
     cv32e40p_tb_wrapper_i
diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv
index 6276567a80..212676dcbd 100644
--- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv
+++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv
@@ -42,12 +42,12 @@
 module uvmt_cv32e40p_dut_wrap 
   #(
                             // CV32E40P parameters.  See User Manual.
-                            parameter PULP_XPULP          =  0,
-                                      PULP_CLUSTER        =  0,
+                            parameter COREV_PULP          =  0,
+                                      COREV_CLUSTER       =  0,
                                       FPU                 =  0,
                                       FPU_ADDMUL_LAT      =  0,
                                       FPU_OTHERS_LAT      =  0,
-                                      PULP_ZFINX          =  0,
+                                      ZFINX               =  0,
                                       NUM_MHPMCOUNTERS    =  1,
                             // Remaining parameters are used by TB components only
                                       INSTR_ADDR_WIDTH    =  32,
@@ -136,12 +136,12 @@ module uvmt_cv32e40p_dut_wrap
     // -------------------------------------------------------------
     // Instantiate the Core and optional FPU plus logger and tracers
     cv32e40p_tb_wrapper #(
-                 .PULP_XPULP       (PULP_XPULP),
-                 .PULP_CLUSTER     (PULP_CLUSTER),
+                 .COREV_PULP       (COREV_PULP),
+                 .COREV_CLUSTER    (COREV_CLUSTER),
                  .FPU              (FPU),
                  .FPU_ADDMUL_LAT   (FPU_ADDMUL_LAT),
                  .FPU_OTHERS_LAT   (FPU_OTHERS_LAT),
-                 .PULP_ZFINX       (PULP_ZFINX),
+                 .ZFINX            (ZFINX),
                  .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS)
                 )
     cv32e40p_tb_wrapper_i
diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
index 8a9ef6c86c..6c6a872dd4 100644
--- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
+++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
@@ -477,10 +477,6 @@ module uvmt_cv32e40p_imperas_dv_wrap
 
     // TODO silabs-hfegran: temp fix to work around issues
     // rvviRefCsrCompareEnable(hart_id, `CSR_DCSR_ADDR,   RVVI_FALSE);
-
-    // rvviRefCsrCompareEnable(hart_id, `CSR_MSTATUS_ADDR,   RVVI_FALSE);
-    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MSTATUS_ADDR          ));
-    rvviRefCsrCompareEnable(hart_id, `CSR_MISA_ADDR,   RVVI_FALSE);
     // end TODO
     // define asynchronous grouping
     // Interrupts
@@ -504,7 +500,7 @@ module uvmt_cv32e40p_imperas_dv_wrap
     rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt14"),    1);
     rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt15"),    1);
 
-    rvviRefNetGroupSet(rvviRefNetIndexGet("InstructionBusFault"), 2);
+//  rvviRefNetGroupSet(rvviRefNetIndexGet("InstructionBusFault"), 2);
 
     // Debug
     rvviRefNetGroupSet(rvviRefNetIndexGet("haltreq"),             4);
diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv
index 8ff3e6ff97..84a8f4cce9 100644
--- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv
+++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv
@@ -41,20 +41,20 @@ module uvmt_cv32e40p_tb;
    `endif
    // DUT (core) parameters: refer to the CV32E40P User Manual.
 `ifdef NO_PULP
-   parameter int CORE_PARAM_PULP_XPULP           = 0;
-   parameter int CORE_PARAM_PULP_CLUSTER         = 0;
+   parameter int CORE_PARAM_COREV_PULP           = 0;
+   parameter int CORE_PARAM_COREV_CLUSTER        = 0;
    parameter int CORE_PARAM_FPU                  = 0;
    parameter int CORE_PARAM_FPU_ADDMUL_LAT       = 0;
    parameter int CORE_PARAM_FPU_OTHERS_LAT       = 0;
-   parameter int CORE_PARAM_PULP_ZFINX           = 0;
+   parameter int CORE_PARAM_ZFINX                = 0;
 `else
    `ifdef PULP
-      parameter int CORE_PARAM_PULP_XPULP        = 1;
+      parameter int CORE_PARAM_COREV_PULP        = 1;
 
       `ifdef CLUSTER
-         parameter int CORE_PARAM_PULP_CLUSTER   = 1;
+         parameter int CORE_PARAM_COREV_CLUSTER  = 1;
       `else
-         parameter int CORE_PARAM_PULP_CLUSTER   = 0;
+         parameter int CORE_PARAM_COREV_CLUSTER  = 0;
       `endif
 
       `ifdef FPU
@@ -70,25 +70,25 @@ module uvmt_cv32e40p_tb;
             parameter int CORE_PARAM_FPU_OTHERS_LAT = 0;
          `endif
          `ifdef ZFINX
-            parameter int CORE_PARAM_PULP_ZFINX  = 1;
+            parameter int CORE_PARAM_ZFINX       = 1;
          `else
-            parameter int CORE_PARAM_PULP_ZFINX  = 0;
+            parameter int CORE_PARAM_ZFINX       = 0;
          `endif
       `else
          parameter int CORE_PARAM_FPU            = 0;
          parameter int CORE_PARAM_FPU_ADDMUL_LAT = 0;
          parameter int CORE_PARAM_FPU_OTHERS_LAT = 0;
-         parameter int CORE_PARAM_PULP_ZFINX     = 0;
+         parameter int CORE_PARAM_ZFINX          = 0;
       `endif
 
    `else
       // If you don't explicitly specify either NO_PULP or PULP, you get NO_PULP
-      parameter int CORE_PARAM_PULP_XPULP        = 0;
-      parameter int CORE_PARAM_PULP_CLUSTER      = 0;
+      parameter int CORE_PARAM_COREV_PULP        = 0;
+      parameter int CORE_PARAM_COREV_CLUSTER     = 0;
       parameter int CORE_PARAM_FPU               = 0;
       parameter int CORE_PARAM_FPU_ADDMUL_LAT    = 0;
       parameter int CORE_PARAM_FPU_OTHERS_LAT    = 0;
-      parameter int CORE_PARAM_PULP_ZFINX        = 0;
+      parameter int CORE_PARAM_ZFINX             = 0;
    `endif
 `endif
 
@@ -148,12 +148,12 @@ module uvmt_cv32e40p_tb;
    * a few mods to bring unused ports from the CORE to this level using SV interfaces.
    */
    uvmt_cv32e40p_dut_wrap  #(
-                             .PULP_XPULP        (CORE_PARAM_PULP_XPULP),
-                             .PULP_CLUSTER      (CORE_PARAM_PULP_CLUSTER),
+                             .COREV_PULP        (CORE_PARAM_COREV_PULP),
+                             .COREV_CLUSTER     (CORE_PARAM_COREV_CLUSTER),
                              .FPU               (CORE_PARAM_FPU),
                              .FPU_ADDMUL_LAT    (CORE_PARAM_FPU_ADDMUL_LAT),
                              .FPU_OTHERS_LAT    (CORE_PARAM_FPU_OTHERS_LAT),
-                             .PULP_ZFINX        (CORE_PARAM_PULP_ZFINX),
+                             .ZFINX             (CORE_PARAM_ZFINX),
                              .NUM_MHPMCOUNTERS  (CORE_PARAM_NUM_MHPMCOUNTERS),
                              .INSTR_ADDR_WIDTH  (ENV_PARAM_INSTR_ADDR_WIDTH),
                              .INSTR_RDATA_WIDTH (ENV_PARAM_INSTR_DATA_WIDTH),
@@ -427,60 +427,60 @@ module uvmt_cv32e40p_tb;
    uvmt_cv32e40p_debug_cov_assert_if debug_cov_assert_if(
     .clk_i(clknrst_if.clk),
     .rst_ni(clknrst_if.reset_n),
-    .fetch_enable_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.fetch_enable_i),
-    .if_stage_instr_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.if_stage_i.instr_rvalid_i),
-    .if_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.if_stage_i.instr_rdata_i),
-    .id_stage_instr_valid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.instr_valid_i),
-    .id_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.instr_rdata_i),
-    .id_stage_is_compressed(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.is_compressed_i),
-    .id_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.id_valid_i),
-    .is_decoding(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.is_decoding_o),
-    .id_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.pc_id_i),
-    .if_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.if_stage_i.pc_if_o),
-    .mie_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mie_q),
-    .ctrl_fsm_cs(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
-    .illegal_insn_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.illegal_insn_i),
-    .illegal_insn_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.illegal_insn_q),
-    .ecall_insn_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.ecall_insn_i),
-    .debug_req_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.debug_req_pending),
-    .debug_mode_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.debug_mode_q),
-    .dcsr_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.dcsr_q),
-    .depc_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.depc_q),
-    .depc_n(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.depc_n),
-    .mcause_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mcause_q),
-    .mtvec({dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mtvec_q, 8'h00}),
-    .mepc_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mepc_q),
-    .tdata1(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.tmatch_control_rdata),
-    .tdata2(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.tmatch_value_rdata),
-    .trigger_match_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.trigger_match_i),
-    .mcountinhibit_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mcountinhibit_q),
-    .mcycle(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mhpmcounter_q[0]),
-    .minstret(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mhpmcounter_q[2]),
-    .fence_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.decoder_i.fencei_insn_o),
+    .fetch_enable_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.fetch_enable_i),
+    .if_stage_instr_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rvalid_i),
+    .if_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rdata_i),
+    .id_stage_instr_valid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_valid_i),
+    .id_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_rdata_i),
+    .id_stage_is_compressed(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.is_compressed_i),
+    .id_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.id_valid_i),
+    .is_decoding(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.is_decoding_o),
+    .id_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.pc_id_i),
+    .if_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.pc_if_o),
+    .mie_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mie_q),
+    .ctrl_fsm_cs(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
+    .illegal_insn_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.illegal_insn_i),
+    .illegal_insn_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.illegal_insn_q),
+    .ecall_insn_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.ecall_insn_i),
+    .debug_req_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_req_pending),
+    .debug_mode_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_mode_q),
+    .dcsr_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.dcsr_q),
+    .depc_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.depc_q),
+    .depc_n(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.depc_n),
+    .mcause_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mcause_q),
+    .mtvec({dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mtvec_q, 8'h00}),
+    .mepc_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mepc_q),
+    .tdata1(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.tmatch_control_rdata),
+    .tdata2(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.tmatch_value_rdata),
+    .trigger_match_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.trigger_match_i),
+    .mcountinhibit_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_q),
+    .mcycle(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mhpmcounter_q[0]),
+    .minstret(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mhpmcounter_q[2]),
+    .fence_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.decoder_i.fencei_insn_o),
 
     // TODO: review this change from CV32E40P_HASH f6196bf to a26b194. It should be logically equivalent.
-    //assign debug_cov_assert_if.inst_ret = dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.inst_ret;
+    //assign debug_cov_assert_if.inst_ret = dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.inst_ret;
     // First attempt: this causes unexpected failures of a_minstret_count
-    //assign debug_cov_assert_if.inst_ret = (dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_valid &
-    //                                       dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.is_decoding);
+    //assign debug_cov_assert_if.inst_ret = (dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_valid &
+    //                                       dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.is_decoding);
     // Second attempt: (based on OK input).  This passes, but maybe only because p_minstret_count
     //                                       is the only property sensitive to inst_ret. Will
     //                                       this work in the general case?
-    .inst_ret(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.mhpmevent_minstret_i),
-    .csr_access(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.csr_access),
-    .csr_op(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.csr_op),
-    .csr_op_dec(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.decoder_i.csr_op),
-    .csr_addr(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.csr_addr),
-    .csr_we_int(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.cs_registers_i.csr_we_int),
-    .irq_ack_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.irq_ack_o),
-    .irq_id_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.irq_id_o),
-    .dm_halt_addr_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.dm_halt_addr_i),
-    .dm_exception_addr_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.dm_exception_addr_i),
-    .core_sleep_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.core_sleep_o),
-    .irq_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.irq_i),
-    .pc_set(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.pc_set_o),
-    .boot_addr_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.boot_addr_i),
-    .branch_in_decode(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.branch_in_id),
+    .inst_ret(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mhpmevent_minstret_i),
+    .csr_access(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.csr_access),
+    .csr_op(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.csr_op),
+    .csr_op_dec(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.decoder_i.csr_op),
+    .csr_addr(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.csr_addr),
+    .csr_we_int(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.csr_we_int),
+    .irq_ack_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.irq_ack_o),
+    .irq_id_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.irq_id_o),
+    .dm_halt_addr_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.dm_halt_addr_i),
+    .dm_exception_addr_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.dm_exception_addr_i),
+    .core_sleep_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.core_sleep_o),
+    .irq_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.irq_i),
+    .pc_set(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.pc_set_o),
+    .boot_addr_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.boot_addr_i),
+    .branch_in_decode(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.branch_in_id),
 
     .is_wfi(),
     .in_wfi(),
@@ -501,8 +501,8 @@ module uvmt_cv32e40p_tb;
     `ifndef FORMAL
     `ifdef USE_ISS
       uvmt_cv32e40p_imperas_dv_wrap #(
-        .FPU(CORE_PARAM_FPU),
-        .ZFINX(CORE_PARAM_PULP_ZFINX)
+        .FPU  (CORE_PARAM_FPU),
+        .ZFINX(CORE_PARAM_ZFINX)
       ) imperas_dv (rvvi_if);
     `endif
     `endif
@@ -691,12 +691,12 @@ module uvmt_cv32e40p_tb;
      uvm_config_db#(bit[31:0])::set(.cntxt(null), .inst_name("*"), .field_name("evalue"), .value(32'h00000000));
 
      // DUT and ENV parameters
-     uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_PULP_XPULP"),       .value(CORE_PARAM_PULP_XPULP)      );
-     uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_PULP_CLUSTER"),     .value(CORE_PARAM_PULP_CLUSTER)    );
+     uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_COREV_PULP"),       .value(CORE_PARAM_COREV_PULP)      );
+     uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_COREV_CLUSTER"),    .value(CORE_PARAM_COREV_CLUSTER)   );
      uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_FPU"),              .value(CORE_PARAM_FPU)             );
      uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_FPU_ADDMUL_LAT"),   .value(CORE_PARAM_FPU_ADDMUL_LAT)  );
      uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_FPU_OTHERS_LAT"),   .value(CORE_PARAM_FPU_OTHERS_LAT)  );
-     uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_PULP_ZFINX"),       .value(CORE_PARAM_PULP_ZFINX)      );
+     uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_ZFINX"),            .value(CORE_PARAM_ZFINX)           );
      uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_NUM_MHPMCOUNTERS"), .value(CORE_PARAM_NUM_MHPMCOUNTERS));
      uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_ADDR_WIDTH"),  .value(ENV_PARAM_INSTR_ADDR_WIDTH) );
      uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_DATA_WIDTH"),  .value(ENV_PARAM_INSTR_DATA_WIDTH) );
@@ -725,9 +725,9 @@ module uvmt_cv32e40p_tb;
    `endif
 
    //TODO verify these are correct with regards to isacov function
-   //always @(dut_wrap.cv32e40p_wrapper_i.rvfi_instr_if_0_i.rvfi_valid) -> isacov_if.retire;
-   //assign isacov_if.instr = dut_wrap.cv32e40p_wrapper_i.rvfi_instr_if_0_i.rvfi_insn;
-   //assign isacov_if.is_compressed = dut_wrap.cv32e40p_wrapper_i.tracer_i.insn_compressed;
+   //always @(dut_wrap.cv32e40p_top_i.rvfi_instr_if_0_i.rvfi_valid) -> isacov_if.retire;
+   //assign isacov_if.instr = dut_wrap.cv32e40p_top_i.rvfi_instr_if_0_i.rvfi_insn;
+   //assign isacov_if.is_compressed = dut_wrap.cv32e40p_top_i.tracer_i.insn_compressed;
 
    // Capture the test status and exit pulse flags
    // TODO: put this logic in the vp_status_if (makes it easier to pass to ENV)
diff --git a/cv32e40p/tests/cfg/default.yaml b/cv32e40p/tests/cfg/default.yaml
index 69505cb0f8..86a1a67cd0 100644
--- a/cv32e40p/tests/cfg/default.yaml
+++ b/cv32e40p/tests/cfg/default.yaml
@@ -7,6 +7,8 @@ ovpsim: >
     --override cpu/sub_Extensions=X
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
 #    --trace --tracechange --traceshowicount --tracemode --monitornets
 cv_sw_march: rv32imc_zicsr_zifencei
 cflags: >
diff --git a/cv32e40p/tests/cfg/no_pulp.yaml b/cv32e40p/tests/cfg/no_pulp.yaml
index 023c88c181..2d5f1a8dec 100644
--- a/cv32e40p/tests/cfg/no_pulp.yaml
+++ b/cv32e40p/tests/cfg/no_pulp.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/marchid=4
     --override cpu/misa_Extensions=0x1104
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
 cv_sw_march: rv32imc_zicsr_zifencei
 cflags: >
     -DNO_PULP
diff --git a/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml b/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml
index 7a5234c110..85f3ac4d53 100644
--- a/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml
+++ b/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override root/cpu/misa_Extensions=0x001104
     --override root/cpu/marchid=4
     --override root/cpu/noinhibit_mask=0000000000
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
 cv_sw_march: rv32imc_zicsr_zifencei
 cflags: >
     -DNO_PULP
diff --git a/cv32e40p/tests/cfg/pulp.yaml b/cv32e40p/tests/cfg/pulp.yaml
index 9a320f1737..7a50a3bb26 100644
--- a/cv32e40p/tests/cfg/pulp.yaml
+++ b/cv32e40p/tests/cfg/pulp.yaml
@@ -4,9 +4,9 @@ compile_flags:
     +define+PULP
 
 # Imperas ISS Options (in ovpsim section)
-# PULP_XPULP=1
+# COREV_PULP=1
 #--override root/cpu/misa_Extensions=0x801104
-# PULP_XPULP=0
+# COREV_PULP=0
 # Set as below
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --monitornets --tracemode
@@ -15,6 +15,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801104
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
 cv_sw_march: rv32imc_zicsr_zifencei_xcvhwlp1p0_xcvmem1p0_xcvmac1p0_xcvbi1p0_xcvalu1p0_xcvsimd1p0_xcvbitmanip1p0
 cflags: >
     -DPULP
diff --git a/cv32e40p/tests/cfg/pulp_cluster.yaml b/cv32e40p/tests/cfg/pulp_cluster.yaml
index 8d09b98d34..55876cf45d 100644
--- a/cv32e40p/tests/cfg/pulp_cluster.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801104
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
 #--showoverrides
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu.yaml
index 0a3a772e98..f275f304bf 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_1cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_1cyclat.yaml
index b5da0d4f8b..dbdd1a56f5 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_1cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_1cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_2cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_2cyclat.yaml
index ee6500cb85..d6050308b7 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_2cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_2cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_3cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_3cyclat.yaml
index bd2ae59579..ac4d343be5 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_3cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_3cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_4cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_4cyclat.yaml
index 38c7106b2e..86ae16dfa6 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_4cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_4cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx.yaml
index 42adf65868..6e8acd34ca 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_1cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_1cyclat.yaml
index 8f2043e4d1..ef6efcb815 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_1cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_1cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_2cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_2cyclat.yaml
index 0aca579738..ea4a2afb11 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_2cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_2cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_3cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_3cyclat.yaml
index 69232798df..5050ab1bfa 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_3cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_3cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_4cyclat.yaml b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_4cyclat.yaml
index fef786861d..8ff1853971 100644
--- a/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_4cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_cluster_fpu_zfinx_4cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu.yaml b/cv32e40p/tests/cfg/pulp_fpu.yaml
index acb41003e4..13c8e92bbf 100644
--- a/cv32e40p/tests/cfg/pulp_fpu.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_1cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_1cyclat.yaml
index 023fa5d16b..daf61ce69e 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_1cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_1cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_2cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_2cyclat.yaml
index 78c5c6091d..34c60fed78 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_2cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_2cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_3cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_3cyclat.yaml
index 4fd9eb6236..1000f68ec8 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_3cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_3cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_4cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_4cyclat.yaml
index 53e2a1e4cc..b7099fb7d2 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_4cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_4cyclat.yaml
@@ -6,6 +6,8 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_zfinx.yaml b/cv32e40p/tests/cfg/pulp_fpu_zfinx.yaml
index f0d90d1465..416e330154 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_zfinx.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_zfinx.yaml
@@ -7,8 +7,8 @@ ovpsim: >
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
     --override cpu/compress_version=1.0.0-RC5.7
-    --override cpu/Zfinx_version=0.41
     --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_zfinx_1cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_zfinx_1cyclat.yaml
index 784d9db088..e473750c7d 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_zfinx_1cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_zfinx_1cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_zfinx_2cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_zfinx_2cyclat.yaml
index ddfa892c7e..65880dedd9 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_zfinx_2cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_zfinx_2cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_zfinx_3cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_zfinx_3cyclat.yaml
index ba7ac3f9e6..f786c3c867 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_zfinx_3cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_zfinx_3cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/cfg/pulp_fpu_zfinx_4cyclat.yaml b/cv32e40p/tests/cfg/pulp_fpu_zfinx_4cyclat.yaml
index 517e22d41a..2576fc8bcb 100644
--- a/cv32e40p/tests/cfg/pulp_fpu_zfinx_4cyclat.yaml
+++ b/cv32e40p/tests/cfg/pulp_fpu_zfinx_4cyclat.yaml
@@ -6,6 +6,9 @@ ovpsim: >
     --override cpu/misa_Extensions=0x801124
     --override cpu/marchid=4
     --override cpu/noinhibit_mask=0xFFFFFFF0
+    --override cpu/compress_version=1.0.0-RC5.7
+    --override cpu/Zcf=T
+    --override cpu/Zfinx_version=0.41
     --showoverrides
 # Debug options (add to ovpsim section as needed)
 #--trace --tracechange --traceshowicount --tracemode --monitornets
diff --git a/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S b/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S
index 71d7b67fa6..0ed1a40caa 100644
--- a/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S
+++ b/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S
@@ -151,7 +151,7 @@ main:
 
     ##
     ## Access the User Custom CSRs.   These are all illegal instructions when
-    ## PULP_XPULP = 0 (which is the default for CV32E40P).
+    ## COREV_PULP = 0 (which is the default for CV32E40P).
     ##
 
     # lpstart0
diff --git a/cv32e40p/tests/programs/custom/illegal_instr_test/illegal_instr_test.S b/cv32e40p/tests/programs/custom/illegal_instr_test/illegal_instr_test.S
index 77e1700bc7..4695272532 100644
--- a/cv32e40p/tests/programs/custom/illegal_instr_test/illegal_instr_test.S
+++ b/cv32e40p/tests/programs/custom/illegal_instr_test/illegal_instr_test.S
@@ -47640,7 +47640,7 @@ main:
 .word(0x00003063)
 .word(0x000020e3)
 .word(0x000030e3)
-# manually added PULP instructions that are interrupts as illegal when PULP_XPULP=0
+# manually added PULP instructions that are interrupts as illegal when COREV_PULP=0
 .word(0x42000033)
 .word(0x42001033)
 .word(0x04002033)
diff --git a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c
index a3a98d3a58..5b3c35cf75 100644
--- a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c
+++ b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c
@@ -41,6 +41,17 @@ void delay(int count) {
     for (volatile int d = 0; d < count; d++);
 }
 
+#ifdef FPU
+void fp_enable ()
+{
+  unsigned int fs = MSTATUS_FS_INITIAL;
+
+  asm volatile("csrs mstatus, %0;"
+               "csrwi fcsr, 0;"
+               : : "r"(fs));
+}
+#endif
+
 void mstatus_mie_enable() {
     int mie_bit = 0x1 << MSTATUS_MIE_BIT;
     asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit));
@@ -212,6 +223,12 @@ __attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void)  {
     );
 
 int main(int argc, char *argv[]) {
+
+#ifdef FPU
+    // Floating Point enable
+    fp_enable();
+#endif
+
     int retval;
 
     // Test 1
diff --git a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.h b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.h
index 70915db9ea..cf15120f93 100644
--- a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.h
+++ b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.h
@@ -26,6 +26,7 @@
 #define TIMER_VAL_ADDR         ((volatile uint32_t *) 0x15000004) 
 
 #define MSTATUS_MIE_BIT 3
+#define MSTATUS_FS_INITIAL 0x00002000
 
 #define MCAUSE_IRQ_MASK 0x1f
 
diff --git a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c
index 4ddc6c8abc..10b456f88a 100644
--- a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c
+++ b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c
@@ -24,7 +24,7 @@
 #define N 16
 #define M 16
 
-#define MSTATUS_FS 0x00006000
+#define MSTATUS_FS_INITIAL 0x00002000
 
 #include "stimuli.h"
 
@@ -43,15 +43,17 @@ int checkInt (long int *B, long int *A, long int n)
   return err;
 }
 
+#ifdef FPU
 void fp_enable ()
 {
-  unsigned int fs = MSTATUS_FS & (MSTATUS_FS >> 1);
+  unsigned int fs = MSTATUS_FS_INITIAL;
 
   __asm__ volatile("csrs mstatus, %0;"
                    "csrwi fcsr, 0;"
                    : : "r"(fs));
 
 }
+#endif
 
 void mcycle_counter_enable ()
 {
@@ -75,8 +77,10 @@ int main()
 
   volatile float fdiv;
 
+#ifdef FPU
   // Floating Point enable
   fp_enable();
+#endif
 
   // Enable mcycle counter
   mcycle_counter_enable();
diff --git a/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c b/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c
index 44c2563c25..3c0fc78bbe 100644
--- a/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c
+++ b/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c
@@ -85,7 +85,7 @@ int main(int argc, char *argv[])
 	*/
 
   /*
-  // lpstat0/1, lpend0/1 and lpcount0/1 present when PULP_XPULP=1
+  // lpstat0/1, lpend0/1 and lpcount0/1 present when COREV_PULP=1
   // Not currently modeled.
   __asm__ volatile("csrr %0, 0x7C0" : "=r"(lpstart0_rval));
   __asm__ volatile("csrr %0, 0x7C1" : "=r"(lpend0_rval));
@@ -123,7 +123,7 @@ int main(int argc, char *argv[])
   /*
   __asm__ volatile("csrr %0, 0x006" : "=r"(fprec_rval));    // not present because FP=0
   __asm__ volatile("csrr %0, 0xC10" : "=r"(privlv_rval));   // not modeled by the Imperas RM
-  __asm__ volatile("csrr %0, 0x014" : "=r"(uhartid_rval));  // present because PULP_XPULP=1
+  __asm__ volatile("csrr %0, 0x014" : "=r"(uhartid_rval));  // present because COREV_PULP=1
 
   if (fprec_rval != 0x0) {
     printf("ERROR: CSR FPREC not zero!\n\n");
diff --git a/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c b/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c
index 62806cd4d1..a740c1e68d 100644
--- a/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c
+++ b/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c
@@ -93,7 +93,7 @@ int main(int argc, char *argv[])
   /*
   // These CSRs are present in the RTL, but will not be modeled in the RM
   // as they are XPULP-specific.
-  // lpstat0/1, lpend0/1 and lpcount0/1 present when PULP_XPULP=1
+  // lpstat0/1, lpend0/1 and lpcount0/1 present when COREV_PULP=1
   __asm__ volatile("csrr %0, 0x7C0" : "=r"(lpstart0_rval));
   __asm__ volatile("csrr %0, 0x7C1" : "=r"(lpend0_rval));
   __asm__ volatile("csrr %0, 0x7C2" : "=r"(lpcount0_rval));
diff --git a/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv b/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv
index 390b64c41f..e1699600b9 100644
--- a/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv
+++ b/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv
@@ -72,7 +72,7 @@ module cv32e40s_tb_wrapper
 //          .PULP_XPULP            ( PULP_XPULP            ),
 //          .PULP_CLUSTER          ( PULP_CLUSTER          ),
 //          .FPU                   ( FPU                   ),
-//          .PULP_ZFINX            ( PULP_ZFINX            ),
+//          .ZFINX                 ( ZFINX                 ),
 //          .NUM_MHPMCOUNTERS      ( NUM_MHPMCOUNTERS      ))
 //    core_log_i(
 //          .clk_i              ( cv32e40s_core_i.id_stage_i.clk              ),
diff --git a/mk/uvmt/uvmt.mk b/mk/uvmt/uvmt.mk
index f81e6263bb..6416852f3b 100644
--- a/mk/uvmt/uvmt.mk
+++ b/mk/uvmt/uvmt.mk
@@ -63,6 +63,7 @@ MKDIR_P = mkdir -p
 # Compile compile flags for all simulators (careful!)
 WAVES        ?= 0
 SV_CMP_FLAGS ?= "+define+$(CV_CORE_UC)_ASSERT_ON"
+SV_CMP_FLAGS = ""
 TIMESCALE    ?= -timescale 1ns/1ps
 UVM_PLUSARGS ?=
 
diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk
index 5bb181c4aa..5517f6dad2 100644
--- a/mk/uvmt/vsim.mk
+++ b/mk/uvmt/vsim.mk
@@ -126,6 +126,7 @@ VLOG_FLAGS += $(DPILIB_VLOG_OPT)
 # Add the ISS to compilation
 VLOG_FLAGS += "+define+$(CV_CORE_UC)_TRACE_EXECUTION"
 VLOG_FLAGS += "+define+$(CV_CORE_UC)_RVFI"
+VLOG_FLAGS += "+define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION"
 VLOG_FLAGS += "+define+$(CV_CORE_UC)_CORE_LOG"
 VLOG_FLAGS += "+define+UVM"
 ifeq ($(call IS_YES,$(USE_ISS)),YES)
@@ -516,6 +517,7 @@ riscof_sim_run: $(VSIM_RISCOF_SIM_PREREQ) comp_dut_rtl_riscof_sim gen_riscof_ovp
 		$(VMAP) work $(SIM_RISCOF_ARCH_TESTS_RESULTS)/work
 	cd $(RISCOF_TEST_RUN_DIR) && \
 	export IMPERAS_TOOLS=$(RISCOF_TEST_RUN_DIR)/ovpsim.ic && \
+	export IMPERAS_QUEUE_LICENSE=1 && \
 		$(VSIM) \
 			-work $(VWORK) \
 			$(VSIM_FLAGS) \
@@ -546,7 +548,12 @@ gen_ovpsim_ic:
 	@if [ ! -z "$(CFG_OVPSIM)" ]; then \
 		echo "$(CFG_OVPSIM)" > $(SIM_RUN_RESULTS)/ovpsim.ic; \
 	fi
-	export IMPERAS_TOOLS=ovpsim.ic
+	#@echo "--override cpu/wfi_is_nop=T" >> $(SIM_RUN_RESULTS)/ovpsim.ic
+	#@echo "--override cpu/sub_Extensions=X" >> $(SIM_RUN_RESULTS)/ovpsim.ic
+	#@echo "--showoverrides --trace --tracechange --traceshowicount --monitornetschange --tracemode --tracemem XSA" >> $(SIM_RUN_RESULTS)/ovpsim.ic
+	#@echo "--extlib refRoot/cpu/cat=imperas.com/intercept/cpuContextAwareTracer/1.0"  >> $(SIM_RUN_RESULTS)/ovpsim.ic
+	#@echo "--override refRoot/cpu/cat/show_changes=T" >> $(SIM_RUN_RESULTS)/ovpsim.ic
+	#@echo "--override refRoot/cpu/cat/definitions_file=${IMPERAS_HOME}/lib/$(IMPERAS_ARCH)/ImperasLib/riscv.ovpworld.org/processor/riscv/1.0/csr_context_info.lis" >> $(SIM_RUN_RESULTS)/ovpsim.ic
 
 # Target to create work directory in $(VSIM_RESULTS)/
 lib: mk_vsim_dir $(CV_CORE_PKG) $(SVLIB_PKG) $(TBSRC_PKG) $(TBSRC)
@@ -604,6 +611,7 @@ run: $(VSIM_RUN_PREREQ) gen_ovpsim_ic
 		$(VMAP) work $(SIM_CFG_RESULTS)/work
 	cd $(RUN_DIR) && \
 	export IMPERAS_TOOLS=$(SIM_RUN_RESULTS)/ovpsim.ic && \
+	export IMPERAS_QUEUE_LICENSE=1 && \
 		$(VSIM) \
 			-work $(VWORK) \
 			$(VSIM_FLAGS) \
diff --git a/mk/uvmt/xrun.mk b/mk/uvmt/xrun.mk
index 996a4b1fd8..b1c6103a44 100644
--- a/mk/uvmt/xrun.mk
+++ b/mk/uvmt/xrun.mk
@@ -173,6 +173,7 @@ XRUN_UVM_MACROS_INC_FILE = $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC)_uvm_macros_inc.sv
 XRUN_FILE_LIST ?= -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist
 XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION
 XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_RVFI
+XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION
 XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_CORE_LOG
 XRUN_USER_COMPILE_ARGS += +define+UVM
 ifeq ($(call IS_YES,$(USE_ISS)),YES)
@@ -357,13 +358,12 @@ gen_ovpsim_ic:
 		echo "$(CFG_OVPSIM)" > $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic; \
 	fi
 	# add glossing of registers
-	@echo "--override cpu/wfi_is_nop=T" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
+	#@echo "--override cpu/wfi_is_nop=T" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
 	#@echo "--override cpu/sub_Extensions=X" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
-	# @echo "--showoverrides --trace --tracechange --traceshowicount --monitornetschange --tracemode --tracemem XSA" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
+	#@echo "--showoverrides --trace --tracechange --traceshowicount --monitornetschange --tracemode --tracemem XSA" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
 	#@echo "--extlib refRoot/cpu/cat=imperas.com/intercept/cpuContextAwareTracer/1.0"  >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
 	#@echo "--override refRoot/cpu/cat/show_changes=T" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
 	#@echo "--override refRoot/cpu/cat/definitions_file=${IMPERAS_HOME}/lib/$(IMPERAS_ARCH)/ImperasLib/riscv.ovpworld.org/processor/riscv/1.0/csr_context_info.lis" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic
-export IMPERAS_TOOLS=ovpsim.ic
 
 ################################################################################
 # The new general test target
@@ -371,6 +371,8 @@ export IMPERAS_TOOLS=ovpsim.ic
 test: $(XRUN_SIM_PREREQ) hex gen_ovpsim_ic
 	mkdir -p $(SIM_RUN_RESULTS)/test_program && \
 	cd $(SIM_RUN_RESULTS) && \
+	export IMPERAS_TOOLS=$(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic && \
+	export IMPERAS_QUEUE_LICENSE=1 && \
 	$(XRUN) \
 		-R -xmlibdirname ../../xcelium.d \
 		-l xrun-$(TEST_NAME).log \
@@ -467,6 +469,7 @@ riscof_sim_run: $(XRUN_RISCOF_SIM_PREREQ) comp_dut_rtl_riscof_sim gen_riscof_ovp
 	@echo "$(BANNER)"
 	cd $(RISCOF_TEST_RUN_DIR) && \
 	export IMPERAS_TOOLS=$(RISCOF_TEST_RUN_DIR)/ovpsim.ic && \
+	export IMPERAS_QUEUE_LICENSE=1 && \
 	$(XRUN) \
 		-R -xmlibdirname xcelium.d \
 		-l xrun-dut_test.log \
diff --git a/vendor_lib/imperas/design/monitor.sv b/vendor_lib/imperas/design/monitor.sv
deleted file mode 100644
index 99511c3df2..0000000000
--- a/vendor_lib/imperas/design/monitor.sv
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- *
- * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
- *
- * The contents of this file are provided under the Software License
- * Agreement that you accepted before downloading this file.
- *
- * This source forms part of the Software and can be used for educational,
- * training, and demonstration purposes but cannot be used for derivative
- * works except in cases where the derivative works require OVP technology
- * to run.
- *
- * For open source models released under licenses that you can use for
- * derivative works, please visit www.OVPworld.org or www.imperas.com
- * for the location of the open source models.
- *
- */
- 
- `include "typedefs.sv"
-
-module MONITOR 
-(
-    RVVI_bus bus,
-    RVVI_io  io
-);
-    int     fd_sym;
-    string  fn_sym;
-    string  type_sym[string];
-    int     addr_sym[string];
-
-    watchT begin_signature;
-    watchT end_signature;
-    watchT _test_stdout;
-    watchT _test_exit;
-    watchT _test_intc_machine_external;
-    watchT _test_intc_machine_software;  
-    watchT _test_intc_machine_timer;  
-    watchT trap_vector;
-    
-    int fd_signature, fd_stdout;
-    
-    function automatic void split_string (
-        output string out [$],
-        input string in,
-        input string separator = ",",
-        input bit drop_blank = 1
-    );
-        string val;
-        bit flag;
-        in = {in,separator};
-        out.delete();
-        foreach (in[i]) begin
-            if (drop_blank && in[i] == " ") continue;
-            if (in[i] == separator[0]) begin
-                if (flag) begin
-                    flag = 0;
-                end else if (val != "") begin
-                    out.push_back(val);
-                end
-                val = "";
-            end else begin
-                val = {val, in[i]};
-            end
-        end
-    endfunction
-    
-    function automatic void nm_get(string name_sym, ref watchT watch);
-        if (addr_sym.exists(name_sym)) begin
-            watch.addr   = addr_sym[name_sym];
-            watch.enable = 1;
-        end
-    endfunction
-    
-    function automatic void nm_load();
-        int i, j;
-        string line;
-        string linesplit[$];
-        string name_sym;
-        
-        // simply return if not provided
-        if (!($value$plusargs("nm_file=%s", fn_sym))) begin
-            return;
-        end
-
-        fd_sym = $fopen(fn_sym, "r");
-        // simply return if not provided
-        if (fd_sym == 0) begin
-            return;
-        end
-        
-        while ($fgets(line, fd_sym)) begin
-            j = line.len() - 2;
-            line = line.substr(0, j);
-            
-            split_string(linesplit, line, " ", 0);
-            name_sym = linesplit[2];
-            
-            addr_sym[name_sym] = linesplit[0].atohex();
-            type_sym[name_sym] = linesplit[1];
-        end
-        $fclose(fd_sym);
-    endfunction
-    
-    // Generate a signature dump file
-    function automatic void dumpSignature();
-        automatic int addr = begin_signature.addr;
-        automatic string sig_file = "signature.txt";
-        
-        if (!begin_signature.enable) return;
-
-        if ($value$plusargs("sig_file=%s", sig_file)) ;
-        $display("Writing signature %s", sig_file);
-        
-        $display("Dump Signature 0x%x -> 0x%x", begin_signature.addr, end_signature.addr);
-
-        fd_signature = $fopen(sig_file, "w");
-
-        while (addr < end_signature.addr) begin
-            $fwrite(fd_signature, "%x\n", ram.memory.mem[addr>>2]);
-            addr = addr + 4;
-        end
-  
-        $fclose(fd_signature);
-    endfunction
-    
-    function void openStdout();
-        automatic string stdout_file = "stdout.txt";
-        if ($value$plusargs("stdout_file=%s", stdout_file)) ;
-        $display("Opening stdout %s", stdout_file);
-    
-        fd_stdout = $fopen(stdout_file, "w");
-    endfunction
-    
-    function void closeStdout();
-        $fclose(fd_stdout);
-    endfunction
-    
-    initial begin
-        nm_load();
-        
-        nm_get("trap_vector"    , trap_vector);
-        nm_get("begin_signature", begin_signature);
-        nm_get("end_signature"  , end_signature);
-        nm_get("_test_stdout"   , _test_stdout);
-        
-        nm_get("_test_intc_machine_external"  , _test_intc_machine_external);
-        nm_get("_test_intc_machine_software"  , _test_intc_machine_software);
-        nm_get("_test_intc_machine_timer"     , _test_intc_machine_timer);
-        
-        nm_get("_test_exit"     , _test_exit);
-        nm_get("write_tohost"   , _test_exit); // used for riscv-dv and riscv-compliance
-
-        if (trap_vector.enable)
-            $display("trap_vector=%x", trap_vector.addr);
-            
-        if (begin_signature.enable)
-            $display("begin_signature=%x", begin_signature.addr);
-        if (end_signature.enable)
-            $display("end_signature=%x", end_signature.addr);
-            
-        if (_test_stdout.enable)
-            $display("_test_stdout=%x", _test_stdout.addr);
-            
-        if (_test_intc_machine_external.enable)
-            $display("_test_intc_machine_external=%x", _test_intc_machine_external.addr);
-        if (_test_intc_machine_software.enable)
-            $display("_test_intc_machine_software=%x", _test_intc_machine_software.addr);
-        if (_test_intc_machine_timer.enable)
-            $display("_test_intc_machine_timer=%x", _test_intc_machine_timer.addr);
-        if (_test_exit.enable)
-            $display("_test_exit=%x", _test_exit.addr);
-        
-        openStdout();
-    end
-    
-    bit [31:0] DAddr, IAddr;
-    bit [31:0] DData, IData;
-    bit [3:0]  Dbe, Ibe;
-    bit [2:0]  DSize, ISize;
-    bit RD, WR, IF, LD, ST;
-    bit MSWInt;
-    bit MTInt;
-    bit MEInt;
-    bit reset;
-    
-    int int_machine_external_cnt;
-    int int_machine_software_cnt;
-    int int_machine_timer_cnt;
-    
-    always @(*) begin
-        DAddr  = bus.DAddr;
-        DData  = bus.DData;
-        Dbe    = bus.Dbe;
-        DSize  = bus.DSize;
-        IAddr  = bus.IAddr;
-        IData  = bus.IData;
-        Ibe    = bus.Ibe;
-        ISize  = bus.ISize;
-        
-        reset  = io.reset;
-        MSWInt = io.irq_i[3];
-        MTInt  = io.irq_i[7];
-        MEInt  = io.irq_i[11];
-
-        IF     = (bus.Ird==1);
-        LD     = (bus.Drd==1);
-        ST     = (bus.Dwr==1);
-        RD     = IF | LD;
-        WR     = ST;
-    end
-    
-    always @(posedge bus.Clk) begin
-        if (bus.Ird) begin
-            // EXIT
-            if (_test_exit.enable && bus.IAddr==_test_exit.addr) begin
-                if (!io.Shutdown) $display("Fetch: Exit Label");
-                io.Shutdown = 1;
-            end
-            // TRAP
-            if (trap_vector.enable && bus.IAddr==trap_vector.addr) begin
-                $display("Fetch: Trap Label");
-                io.Shutdown = 1;
-            end
-        end
-        
-        if (bus.Drd) begin
-        end
-        
-        if (bus.Dwr) begin
-            // STDOUT
-            if (_test_stdout.enable && bus.DAddr==_test_stdout.addr) begin
-                automatic int c = bus.DData&'hff;
-                $write("%c", c);
-                $fwrite(fd_stdout, "%c", c);
-                $fflush(fd_stdout);
-            end
-            
-            //
-            // Interrupt Generation
-            //
-            if (_test_intc_machine_external.enable && bus.DAddr==_test_intc_machine_external.addr) begin
-                int_machine_external_cnt = bus.DData;
-                if (int_machine_external_cnt == 0) begin
-                    // Interrupt Clear
-                    $display("io.irq_i[11] = 0");
-                    io.irq_i[11] = 0;
-                end
-            end  
-            if (_test_intc_machine_software.enable && bus.DAddr==_test_intc_machine_software.addr) begin
-                int_machine_software_cnt = bus.DData;
-                if (int_machine_software_cnt == 0) begin
-                    // Interrupt Clear
-                    $display("io.irq_i[3] = 0");
-                    io.irq_i[3] = 0;
-                end
-            end
-            if (_test_intc_machine_timer.enable && bus.DAddr==_test_intc_machine_timer.addr) begin
-                int_machine_timer_cnt = bus.DData;
-                if (int_machine_timer_cnt == 0) begin
-                    // Interrupt Clear
-                    $display("io.irq_i[7] = 0");
-                    io.irq_i[7] = 0;
-                end
-            end
-        end
-        
-        // Machine External Interrupt Generation
-        if (int_machine_external_cnt > 1) begin
-            int_machine_external_cnt = int_machine_external_cnt - 1;
-        end else if ((int_machine_external_cnt == 1) && (io.irq_i[11] == 0)) begin
-            $display("io.irq_i[11] = 1");
-            io.irq_i[11] = 1;
-        end 
-   
-        // Machine_timer Interrupt Generation
-        if (int_machine_timer_cnt > 1) begin
-            int_machine_timer_cnt = int_machine_timer_cnt - 1;
-        end else if ((int_machine_timer_cnt == 1) && (io.irq_i[7] == 0)) begin
-            $display("io.irq_i[7] = 1");
-            io.irq_i[7] = 1;        
-        end
-
-        // Machine_software Interrupt Generation
-        if (int_machine_software_cnt > 1) begin
-            int_machine_software_cnt = int_machine_software_cnt - 1;
-        end else if ((int_machine_software_cnt == 1) && (io.irq_i[3] == 0)) begin
-            $display("io.irq_i[3] = 1");
-            io.irq_i[3] = 1;        
-        end
-    end // always @ (posedge bus.Clk)
-    
-    final begin
-        dumpSignature();
-        closeStdout();
-    end
-endmodule
diff --git a/vendor_lib/imperas/design/ram.sv b/vendor_lib/imperas/design/ram.sv
deleted file mode 100644
index b5b589f34f..0000000000
--- a/vendor_lib/imperas/design/ram.sv
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- *
- * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
- *
- * The contents of this file are provided under the Software License
- * Agreement that you accepted before downloading this file.
- *
- * This source forms part of the Software and can be used for educational,
- * training, and demonstration purposes but cannot be used for derivative
- * works except in cases where the derivative works require OVP technology
- * to run.
- *
- * For open source models released under licenses that you can use for
- * derivative works, please visit www.OVPworld.org or www.imperas.com
- * for the location of the open source models.
- *
- */
- 
- `include "typedefs.sv"
- 
-interface RVVI_memory;
-
-    reg [31:0] mem [bit[29:0]];
-
-endinterface
-
-//
-// Memory is an array of words
-// ROM = ROM_START_ADDR : ROM_START_ADDR+ROM_MEM_DEPTH-1
-// RAM = ROM_START_ADDR+ROM_MEM_DEPTH : ROM_START_ADDR+ROM_MEM_DEPTH+RAM_MEM_DEPTH-1
-//
-module RAM
-#(
-    parameter int ROM_START_ADDR = 'h8000,
-    parameter int ROM_BYTE_SIZE  = 'h20000,
-    parameter int RAM_BYTE_SIZE  = 'h20000
-)
-(
-    RVVI_bus bus   
-);
-
-    Uns32 daddr4, iaddr4;
-    Uns32 value;
-    bit isROM, isRAM;
-    Uns32 loROM, hiROM;
-    Uns32 loRAM, hiRAM;
-
-    RVVI_memory memory();
-
-    initial begin
-        loROM = ROM_START_ADDR;
-        hiROM = loROM + ROM_BYTE_SIZE - 1;
-        loRAM = hiROM + 1;
-        hiRAM = loRAM + RAM_BYTE_SIZE - 1;
-    end
-    
-    function automatic Uns32 byte2bit (input int ByteEn);
-        Uns32 BitEn = 0;
-        if (ByteEn & 'h1) BitEn |= 'h000000FF;
-        if (ByteEn & 'h2) BitEn |= 'h0000FF00;
-        if (ByteEn & 'h4) BitEn |= 'h00FF0000;
-        if (ByteEn & 'h8) BitEn |= 'hFF000000;
-        return BitEn;
-    endfunction
-    
-    always @(posedge bus.Clk) begin
-        isROM = (bus.IAddr>=loROM && bus.IAddr<=hiROM);
-        isRAM = (bus.DAddr>=loRAM && bus.DAddr<=hiRAM);
-        
-        daddr4 = bus.DAddr >> 2;
-        iaddr4 = bus.IAddr >> 2;
-        
-        // Uninitialized Memory
-        if (!memory.mem.exists(daddr4)) memory.mem[daddr4] = 'h0;
-        if (!memory.mem.exists(iaddr4)) memory.mem[iaddr4] = 'h0;
-
-        // READ (ROM & RAM)
-        if (isROM || isRAM) begin
-            if (bus.Drd==1) begin
-                bus.DData = memory.mem[daddr4] & byte2bit(bus.Dbe);
-                //$display("Load  %08x <= [%08X]", bus.DData, daddr4);
-            end
-        end
-
-        // WRITE
-        if (isRAM) begin
-            if (bus.Dwr==1) begin
-                value = memory.mem[daddr4] & ~(byte2bit(bus.Dbe));
-                memory.mem[daddr4] = value | (bus.DData & byte2bit(bus.Dbe));
-                //$display("Store %08x <= %08X", daddr4, mem[daddr4]);
-                
-            end
-        end
-        
-        // EXEC
-        if (isROM) begin
-            if (bus.Ird==1) begin
-                bus.IData = memory.mem[iaddr4] & byte2bit(bus.Ibe);
-                //$display("Fetch %08x <= [%08X]", bus.IData, iaddr4);
-            end
-        end
-        
-        // checkers
-        if (bus.Ird==1 && isROM==0) begin
-            //$display("ERROR: Fetch Address %08X does not have EXECUTE permission", bus.IAddr);
-            //$finish;
-        end
-        if (bus.Drd==1 && isROM==0 && isRAM==0) begin
-            //$display("ERROR: Load Address %08X does not have READ permission", bus.DAddr);
-            //$finish;
-        end
-        if (bus.Dwr==1 && isRAM==0) begin
-            //$display("ERROR: Store Address %08X does not have WRITE permission", bus.DAddr);
-            //$finish;
-        end
-
-    end
-endmodule
diff --git a/vendor_lib/imperas/design/typedefs.sv b/vendor_lib/imperas/design/typedefs.sv
deleted file mode 100644
index d9a83da9b2..0000000000
--- a/vendor_lib/imperas/design/typedefs.sv
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *
- * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
- *
- * The contents of this file are provided under the Software License
- * Agreement that you accepted before downloading this file.
- *
- * This source forms part of the Software and can be used for educational,
- * training, and demonstration purposes but cannot be used for derivative
- * works except in cases where the derivative works require OVP technology
- * to run.
- *
- * For open source models released under licenses that you can use for
- * derivative works, please visit www.OVPworld.org or www.imperas.com
- * for the location of the open source models.
- *
- */
-
-`ifndef __INCL_TYPEDEFS_SV
-`define __INCL_TYPEDEFS_SV
-
-typedef byte     Int8;
-typedef shortint Int16;
-typedef int      Int32;
-typedef longint  Int64;
-typedef byte     unsigned Uns8;
-typedef shortint unsigned Uns16;
-typedef int      unsigned Uns32;
-typedef longint  unsigned Uns64;
-
-//
-// Address label monitor type
-//
-typedef struct {
-    int addr;
-    int enable;
-} watchT;
-
-`endif
\ No newline at end of file
diff --git a/vendor_lib/imperas/imperas_DV_COREV/ChangeLog.md b/vendor_lib/imperas/imperas_DV_COREV/ChangeLog.md
deleted file mode 100644
index aac83629dc..0000000000
--- a/vendor_lib/imperas/imperas_DV_COREV/ChangeLog.md
+++ /dev/null
@@ -1,60 +0,0 @@
-CV32E40P Change Log
-===
-Copyright (c) 2005-2022 Imperas Software Ltd., www.imperas.com
-
-This CHANGELOG contains information for the Imperas OVP OpenHW CV32E40P fixed platform which includes information of the OVP Simulator and RISCV processor model
-
----
-
-- Trigger Module Behaviour
-  - tdata1 access only permitted in debug mode, ignored in others
-
-Date 2020-August-06
-Version 20200805.1
-===
-- Trigger Module Behaviour
-  - tdata1 execute bit enables address fetch trap on value in tdata2
-  - trap causes entry to debug mode and execution from debug vector
-
-Date 2020-August-05
-Version 20200805.0
-===
-- Trigger Module Registers
-  - Initial registers added for tselect, tdata1, tdata2, tdata3, tinfo
-  - No trigger behaviour added
-- Local Interrupt
-  - 16 local interrupts are enabled
-  - Interrupt acknowledge and Interrupt Id provided
-- CSR Registers
-  - Add mtval, mcontext, scontext write ignored and read zero
-
-Date 2020-July-29
-Version 20200728.2
-===
-- CSR Registers
-   - cycle, intret, cycleh, intereth illegal instruction exception on access
-
-
-Date 2020-July-28
-Version 20200728.1
-===
-
-- Add Debug Module
-   - Provides input signals haltreq and resethaltreq to enter debnuig mode
-   - Provides output DM to provide Debug Mode
-- Trigger Module register
-   - Add tinfo register writes ignored / read zero
-- CSR Registers
-   - mcycle, mintret, mcycleh, mintreth behaviour write ignored / read zero
-   - cycle, intret, cycleh, intereth  behaviour write ignored / read zero
-   - Set PMP undefined to remove pmpcfgN registers
-
-Date 2020-July-23
-===
-
-- CSR Configuration updates
-  - Enabled mcounten register
-  - Set mvendorid to 0x0602
-  - Set mcountinhibit reset value 0xd
-
-===
\ No newline at end of file
diff --git a/vendor_lib/imperas/imperas_DV_COREV/OVP_IMPERAS_LICENSE.pdf b/vendor_lib/imperas/imperas_DV_COREV/OVP_IMPERAS_LICENSE.pdf
deleted file mode 100644
index 9538934336..0000000000
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diff --git a/vendor_lib/imperas/imperas_DV_COREV/OVP_MODIFIED_1.1_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf b/vendor_lib/imperas/imperas_DV_COREV/OVP_MODIFIED_1.1_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
deleted file mode 100644
index 86fdfd0988..0000000000
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diff --git a/vendor_lib/imperas/imperas_DV_COREV/OVP_model_Encapsulation.jpg b/vendor_lib/imperas/imperas_DV_COREV/OVP_model_Encapsulation.jpg
deleted file mode 100644
index dad62ca8c7..0000000000
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diff --git a/vendor_lib/imperas/imperas_DV_COREV/README.md b/vendor_lib/imperas/imperas_DV_COREV/README.md
deleted file mode 100644
index c94795d615..0000000000
--- a/vendor_lib/imperas/imperas_DV_COREV/README.md
+++ /dev/null
@@ -1,68 +0,0 @@
-Imperas OVP Fixed Model of OpenHW CV32E40P CPU for SystemVerilog encapsulation
-==============================================================================
-A Complete, Fully Functional, Configurable CV32E40P Simulation Model
-===
-
-Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 20220419 
-Version: 20200821.606  
-License: Simulation Model CV32E40P licensed under [Software License Agreement for Open Virtual Platforms Technology](OVP_IMPERAS_LICENSE.pdf)
-RISC-V Specifications currently supported:
-- RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.3)
-- RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.11)
-
-
-
-
-![OVP Image ](OVP_model_Encapsulation.jpg)  
-[OVP_MODIFIED_1.1_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf](./doc/OVP_MODIFIED_1.1_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf)
-
-
-
-About Imperas OVP OpenHW CV32E40P Model
----
-The **riscv_CV32E40P_OVPsim** fixed model implements the functionality of the RISC-V Foundation's public User and Privilege specifications, configured for the OpenHW Group CV32E40P processor.
-
-The fixed model is provided as a shared object, riscv_CV32E40P.dpi.so, with a System Verilog DPI interface allowing it to be used in any compatible System Verilog simulator.
-
-The simulator is developed, licensed and maintained by [Imperas Software](http://www.imperas.com/riscv) and it is fully compliant to the OVP open standard APIs. 
-
-As a member of the RISC-V Foundation community of software and hardware innovators collaboratively driving RISC-V adoption, Imperas has developed the riscvOVPsim simulator to assist RISC-V adopters to become compliant to the RISC-V specifications.
-
-
-Debugging using GDB / Eclipse
----
-The same fixed module can be used to debug the application using GDB and Eclipse. Additional Imperas products must be installed to enable these features.
-
-Command line parameters for the fixed model can be provided using an Imperas Control file. Specify a text file containing commands using IMPERAS_TOOLS in the environment.
-
-For GDB debug add the command line argument _-gdbconsole_, this will start the GDB debugger and connect to the virtual platform.
-
-For Eclipse debug add the command line argument _-gdbegui_, this will start the Eclipse eGui debugger and connect to the virtual platform.
-
-
-Using OpenHW CV32E40P Model
----
-The documentation for this CV32E40P model is in the document:
-[OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf](./doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf)
-
-  
-Extending CV32E40P Model and building your own models and platforms
----
-CV32E40P Model is a fixed function simulation of one configurable processor model in a fixed platform. Full extendable platform simulations of reference designs booting FreeRTOS, Linux, SMP Linux etc. are available as open source and are available from [www.IMPERAS.com](http://www.imperas.com), [www.OVPworld.org](http://www.OVPworld.org).  
-
-
-About Open Virtual Platforms (OVP) and Imperas Software
----
-**Open Virtual Platforms** was created in 2008 to provide an open standard set of APIs and methodology to develop virtual platforms and simulation technology. 
-[www.OVPworld.org](http://www.OVPworld.org/riscv).
-
-**Imperas Software Ltd.** is the leading independent commercial developer of virtual platforms and high-performance software simulation solutions for embedded processor and systems. Leading semiconductor and embedded software companies use Imperas simulators for their processor based simulation solutions.
-[www.imperas.com](http://www.imperas.com/riscv).
-
-![OVP Image ](http://www.imperas.com/sites/default/files/partner-logos/ovp_0.jpg)  
-![Imperas Imperas](https://www.imperas.com/sites/default/files/imperas-web-logo_2.png)  
----
-
-
-This is the CV32E40P/README.md  
diff --git a/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so b/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so
deleted file mode 100755
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diff --git a/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/libdwarf-20120410.so b/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/libdwarf-20120410.so
deleted file mode 100755
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diff --git a/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/libelf.so.0.8.13 b/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/libelf.so.0.8.13
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diff --git a/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/libtcl8.4.so b/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/libtcl8.4.so
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