CV32E40s compilation issue with hello world

[vinomutty]

Hi

I have cloned below and not able to run hello world test
git clone https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40s/

ERROR:git clone https://github.com/openhwgroup/cv32e40s /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s; cd /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s; git checkout 103056f0deeac8e6cc10244c86bff83d3014f66f
fatal: destination path '/Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s' already exists and is not an empty directory.
M rtl/cv32e40s_register_file_wrapper.sv
HEAD is now at 103056f... Merge pull request #144 from silabs-oivind/mpu_if_data_access

---

• Compiling CORE TB and CV32E40S with Verilator

---

verilator --cc --sv --exe

--Wno-lint --Wno-UNOPTFLAT
--Wno-MODDUP --top-module
tb_top_verilator /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/tb_top_verilator.sv /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/tb_riscv/riscv_rvalid_stall.sv /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/tb_riscv/riscv_gnt_stall.sv /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/mm_ram.sv /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/dp_ram.sv
-f /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s/cv32e40s_manifest.flist
/Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s/bhv/cv32e40s_core_log.sv
/Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/tb_top_verilator.cpp --Mdir cobj_dir
-CFLAGS "-std=gnu++11 -O2"
-Wno-BLKANDNBLK +define+COREV_ASSERT_OFF
%Warning-UNPACKED: /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s/rtl/../bhv/cv32e40s_dbg_helper.sv:45:26: Unsupported: Unpacked array in packed struct/union (struct/union converted to unpacked)
45 | rf_addr_t rf_raddr[REGFILE_NUM_READ_PORTS];
| ^
/Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s/rtl/../bhv/cv32e40s_core_log.sv:63:1: ... note: In file included from cv32e40s_core_log.sv
/Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/core-v-cores/cv32e40s/rtl/../bhv/cv32e40s_wrapper.sv:41:1: ... note: In file included from cv32e40s_wrapper.sv
... For warning description see https://verilator.org/warn/UNPACKED?v=5.004
... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.
%Error-PINNOTFOUND: /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv:118:11: Pin not found: 'irq_ack_o'
118 | .irq_ack_o ( irq_ack ),
| ^~~~~~~~~
%Error-PINNOTFOUND: /Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv:119:11: Pin not found: 'irq_id_o'
: ... Suggested alternative: 'irq_i'
119 | .irq_id_o ( irq_id_out ),
| ^~~~~~~~
%Error: Exiting due to 2 error(s), 1 warning(s)
... See the manual at https://verilator.org/verilator_doc.html for more assistance.
make[1]: *** [Makefile:460: testbench_verilator] Error 1
make[1]: Leaving directory '/Projects/marmik_project/hemashri.bhagavati/core-v-verif_bck1/cv32e40s/sim/core'
make: *** [Makefile:454: sanity-veri-run] Error 2

we wanted to run with questa but its running with verilator only

command used: make SIMULATOR=vsim

[MikeOpenHWGroup]

Hi @vinomutty. You've got two problems here with the same root-cause. That is, the so-called "core" testbench does not attract a lot of attention and so it tends to suffer from bit-rot as we do not necessarily update it as the RTL progresses and environment changes. It seems the Makefiles for Verilator and Questa are both out-of-date.

It would be greatly appreciated if you could get the core testbench working with Verilator. From the errors you are seeing it seems that the instanitation of the CV32E40S in cv32e40s/tb/core/cv32e40s_tb_wrapper.sv does not match the top-level ports of the cv32e40s_core. I would start there.

[vinomutty]

Hi
Please suggest which branch we need to clone

[MikeOpenHWGroup]

I would recommend the latest version, 9d9cae78b01a11458953133d1173c61933a2ba86.

You do not need to clone the RTL yourself. The Makefiles will automatically clone a specific version of the RTL from the CV32E40S repository into core-v-verif/core-v-cores/cv32e40s. The URL, branch and hash are determined in ExternalRepos.mk. Operation of the Makefiles and related scriptware is documented in mk/README.

[vinomutty]

Hi
As per your comment, we have updated the HASH value mentained above, but still facing same issue. if even we tried with questa its still running with verilator.

export SHELL = /bin/bash

CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40s
CV_CORE_BRANCH ?= dev-1
CV_CORE_HASH ?= 9d9cae78b01a11458953133d1173c61933a2ba86
CV_CORE_TAG ?= none

ERROR:

• Compiling CORE TB and CV32E40S with Verilator

---

verilator --cc --sv --exe

--Wno-lint --Wno-UNOPTFLAT
--Wno-MODDUP --top-module
tb_top_verilator /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/tb_top_verilator.sv /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/tb_riscv/riscv_rvalid_stall.sv /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/tb_riscv/riscv_gnt_stall.sv /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/mm_ram.sv /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/dp_ram.sv
-f /Projects/marmik_project/ansia.liji/core-v-verif/core-v-cores/cv32e40s/cv32e40s_manifest.flist
/Projects/marmik_project/ansia.liji/core-v-verif/core-v-cores/cv32e40s/bhv/cv32e40s_core_log.sv
/Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/tb_top_verilator.cpp --Mdir cobj_dir
-CFLAGS "-std=gnu++11 -O2"
-Wno-BLKANDNBLK +define+COREV_ASSERT_OFF
%Error-PINNOTFOUND: /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv:112:11: Pin not found: 'irq_ack_o'
112 | .irq_ack_o ( irq_ack ),
| ^~~~~~~~~
... For error description see https://verilator.org/warn/PINNOTFOUND?v=5.004
%Error-PINNOTFOUND: /Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv:113:11: Pin not found: 'irq_id_o'
: ... Suggested alternative: 'irq_i'
113 | .irq_id_o ( irq_id_out ),
| ^~~~~~~~
%Error: Exiting due to 2 error(s)
... See the manual at https://verilator.org/verilator_doc.html for more assistance.
make[1]: *** [Makefile:460: testbench_verilator] Error 1
make[1]: Leaving directory '/Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/sim/core'
make: *** [Makefile:454: sanity-veri-run] Error 2
[ansia.liji@coeserver core]$

[MikeOpenHWGroup]

That would not work for two reasons:

1. If you are going to re-pull the RTL, you'll need to delete your current working copy. make clean_all should do it.
2. There is no dev-1 branch of https://github.com/openhwgroup/cv32e40s, and hash you are using is from the master branch. The CV_CORE variables must point to a valid repo/branch/hash combination.

[vinomutty]

Hi
we have i cloned git clone using this link https://github.com/openhwgroup/core-v-verif
and updated the CV_CORE_HASH value to 9d9cae78b01a11458953133d1173c61933a2ba86
but still facing the error.

export SHELL = /bin/bash

CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40s
CV_CORE_BRANCH ?= master
CV_CORE_HASH ?= 9d9cae78b01a11458953133d1173c61933a2ba86
CV_CORE_TAG ?= none

ERROR:***

• Cloning CV32E40S RTL model

---

git clone https://github.com/openhwgroup/core-v-verif /Projects/marmik_project/ansia.liji/core-v-verif/core-v-cores/cv32e40s; cd /Projects/marmik_project/ansia.liji/core-v-verif/core-v-cores/cv32e40s; git checkout 9d9cae78b01a11458953133d1173c61933a2ba86
Cloning into '/Projects/marmik_project/ansia.liji/core-v-verif/core-v-cores/cv32e40s'...
remote: Enumerating objects: 59224, done.
remote: Counting objects: 100% (558/558), done.
remote: Compressing objects: 100% (173/173), done.
remote: Total 59224 (delta 392), reused 499 (delta 365), pack-reused 58666 (from 1)
Receiving objects: 100% (59224/59224), 114.71 MiB | 8.53 MiB/s, done.
Resolving deltas: 100% (40207/40207), done.
fatal: reference is not a tree: 9d9cae78b01a11458953133d1173c61933a2ba86
make[1]: *** [Makefile:636: clone_cv32e40s_rtl] Error 128
make[1]: Leaving directory '/Projects/marmik_project/ansia.liji/core-v-verif/cv32e40s/sim/core'
make: *** [Makefile:454: sanity-veri-run] Error 2

[MikeOpenHWGroup]

Hmmm. This is odd. Here is what happens when I do it manually:

Try this:

$ cd /Projects/marmik_project/ansia.liji/core-v-verif/core-v-cores/cv32e40s
$ git checkout 9d9cae78b01a11458953133d1173c61933a2ba86

If that doesn't work, try $ git checkout 9d9cae7. This is the "short form" of the git hash and it works for most operations. If that works then there is some typo in your External.mk file somewhere.

If that still isn't working then try this:

$ cd /Projects/marmik_project/ansia.liji/core-v-verif/core-v-cores
$ rm -rf cv32e40s
$ git clone https://github.com/openhwgroup/core-v-verif cv32e40s
$ cd cv32e40s
$ git checkout 9d9cae7

If that doesn't work, there is something wrong with your local machine. Good luck!

[vinomutty]

Hi
we tried this
[hemashri.bhagavati@coeserver cv32e40s]$ git checkout 9d9cae78b01a11458953133d1173c61933a2ba86
HEAD is now at 9d9cae7... Merge pull request #528 from silabs-oysteink/silabs-oysteink_merge_24_w44
[hemashri.bhagavati@coeserver cv32e40s]$ ls

then again facing the issues while simulating.
ERROR:* Cloning CV32E40S RTL model

---

git clone https://github.com/openhwgroup/cv32e40s /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/core-v-cores/cv32e40s; cd /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/core-v-cores/cv32e40s; git checkout 9d9cae78b01a11458953133d1173c61933a2ba86
fatal: destination path '/Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/core-v-cores/cv32e40s' already exists and is not an empty directory.
HEAD is now at 9d9cae7... Merge pull request #528 from silabs-oysteink/silabs-oysteink_merge_24_w44

But again we are facing the issue. even if we running with vsim its simulating with verilator only.
ERROR:

• Compiling CORE TB and CV32E40S with Verilator

---

verilator --cc --sv --exe

--Wno-lint --Wno-UNOPTFLAT
--Wno-MODDUP --top-module
tb_top_verilator /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/tb_top_verilator.sv /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/tb_riscv/riscv_rvalid_stall.sv /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/tb_riscv/riscv_gnt_stall.sv /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/mm_ram.sv /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/dp_ram.sv
-f /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/core-v-cores/cv32e40s/cv32e40s_manifest.flist
/Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/core-v-cores/cv32e40s/bhv/cv32e40s_core_log.sv
/Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/tb_top_verilator.cpp --Mdir cobj_dir
-CFLAGS "-std=gnu++11 -O2"
-Wno-BLKANDNBLK +define+COREV_ASSERT_OFF
%Error-PINNOTFOUND: /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv:112:11: Pin not found: 'irq_ack_o'
112 | .irq_ack_o ( irq_ack ),
| ^~~~~~~~~
... For error description see https://verilator.org/warn/PINNOTFOUND?v=5.004
%Error-PINNOTFOUND: /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv:113:11: Pin not found: 'irq_id_o'
: ... Suggested alternative: 'irq_i'
113 | .irq_id_o ( irq_id_out ),
| ^~~~~~~~
%Error: Exiting due to 2 error(s)
... See the manual at https://verilator.org/verilator_doc.html for more assistance.
make[1]: *** [Makefile:460: testbench_verilator] Error 1
make[1]: Leaving directory '/Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/sim/core'
make: *** [Makefile:454: sanity-veri-run] Error 2

COMMAND: $ make SIMULATOR=vsim

export commands: $ export CV_SW_PREFIX=riscv32-unknown-elf-
$ export CV_SW_TOOLCHAIN=/opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1
$ export RISCV=/opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1
$ export CV_SW_MARCH=rv32imcb

path which is used for simulation:
/Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/cv32e40s/sim/core

[MikeOpenHWGroup]

Hi @vinomutty, you are going to need to take the time to understand how git and make work, and look at the Makefiles in core-v-verif in detail. The reason you are getting this error:

fatal: destination path '/Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/core-v-cores/cv32e40s' already exists and is not an empty directory.

is because you are attempting to clone a repo into a working copy that already exists. My instructions were clear about that and the Makefiles won't do that. Run make clean_all and check to see that /Projects/marmik_project/hemashri.bhagavati/ridhu/core-v-verif/core-v-cores is empty.

Your second problem one we've already discussed.