From 7d44a4e2cf05c7db04676b3600167e82ebcd2c53 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 10:48:41 +0800 Subject: [PATCH 01/17] add debug trigger related config items Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_instr_gen_config.sv | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv index 20e76ae460..6f1857c41e 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv @@ -59,6 +59,23 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; rand riscv_reg_t str_rs1; rand riscv_reg_t str_rs3; + // Enable debug trigger breakpoint setup in debug rom + bit setup_debug_trigger_on_addr_match = 0; + + // Number of trigger iterations in a given test + rand int trigger_iterations; + + // Random offset to program next trigger address + rand int trigger_addr_offset; + + //random field to enable setting of single stepping only after + //a trigger breakpoint causes debug entry + rand bit debug_trigger_before_single_step; + + //random field to enable setting of single stepping only after + //an ebreak causes debug entry + rand bit debug_ebreak_before_single_step; + constraint ss_dbg_high_iteration_cnt_c { ss_dbg_high_iteration_cnt dist {0 := 60, 1 := 40}; } @@ -164,6 +181,12 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; } } + constraint trigger_c { + trigger_iterations inside {[1:10]}; + trigger_addr_offset inside {[4:100]}; + trigger_addr_offset % 4 == 0; + } + `uvm_object_utils_begin(cv32e40p_instr_gen_config) `uvm_field_enum(mtvec_mode_t, mtvec_mode, UVM_DEFAULT) `uvm_field_int(knob_zero_fast_intr_handlers, UVM_DEFAULT) @@ -181,6 +204,11 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; `uvm_field_int(xpulp_instr_in_debug_rom, UVM_DEFAULT) `uvm_field_enum(riscv_reg_t, str_rs1, UVM_DEFAULT) `uvm_field_enum(riscv_reg_t, str_rs3, UVM_DEFAULT) + `uvm_field_int(setup_debug_trigger_on_addr_match, UVM_DEFAULT) + `uvm_field_int(trigger_iterations, UVM_DEFAULT) + `uvm_field_int(trigger_addr_offset, UVM_DEFAULT) + `uvm_field_int(debug_trigger_before_single_step, UVM_DEFAULT) + `uvm_field_int(debug_ebreak_before_single_step, UVM_DEFAULT) `uvm_object_utils_end function new(string name=""); @@ -190,6 +218,13 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; get_bool_arg_value("+insert_rand_directed_instr_stream=", insert_rand_directed_instr_stream); get_int_arg_value("+test_rand_directed_instr_stream_num=", test_rand_directed_instr_stream_num); get_bool_arg_value("+is_hwloop_test=", is_hwloop_test); + get_bool_arg_value("+setup_debug_trigger_on_addr_match=", setup_debug_trigger_on_addr_match); + get_bool_arg_value("+debug_trigger_before_single_step=", debug_trigger_before_single_step); + get_bool_arg_value("+debug_ebreak_before_single_step=", debug_ebreak_before_single_step); + + if ($test$plusargs("debug_trigger_before_single_step")) debug_trigger_before_single_step.rand_mode(0); + if ($test$plusargs("debug_ebreak_before_single_step")) debug_ebreak_before_single_step.rand_mode(0); + endfunction : new function void post_randomize(); From 389d64691e7313e0c6ea1092299ad21630113378 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 10:50:57 +0800 Subject: [PATCH 02/17] add cv32e40p_instr_gen_config config field and use uvm_config_db to get Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv index 2104aeabb3..4e22345525 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv @@ -18,6 +18,7 @@ // class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; string debug_dret[$]; + cv32e40p_instr_gen_config cfg_corev; `uvm_object_utils(cv32e40p_debug_rom_gen) @@ -27,18 +28,17 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; virtual function void gen_program(); string sub_program_name[$] = {}; - cv32e40p_instr_gen_config cfg_corev; privileged_reg_t status = MSTATUS; + if(!uvm_config_db#(cv32e40p_instr_gen_config)::get(null,get_full_name(),"cv32e40p_instr_cfg", cfg_corev)) begin + `uvm_fatal(get_full_name(), "Cannot get cv32e40p_instr_gen_config") + end + // CORE-V Addition // Insert section info so linker can place // debug code at the correct adress instr_stream.push_back(".section .debugger, \"ax\""); - // CORE-V Addition - // Cast CORE-V derived handle to enable fetching core-v config fields - `DV_CHECK($cast(cfg_corev, cfg)) - // Randomly add a WFI at start of ddebug rom // This will be treaed as a NOP always, but added here to close instructon // combination coverage (i.e. ebreak->wfi) From 8b4e115564f1b05616e6fb2ae551ae7ffbbca485 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 10:53:17 +0800 Subject: [PATCH 03/17] add new functions related to debug trigger setup in debug rom Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_debug_rom_gen.sv | 178 +++++++++++++++++- 1 file changed, 176 insertions(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv index 4e22345525..ca8f904690 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv @@ -79,6 +79,13 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; // having to execute unnecessary push/pop of GPRs on the stack ever // time a debug request is sent gen_signature_handshake(debug_main, CORE_STATUS, IN_DEBUG_MODE); + if (cfg_corev.setup_debug_trigger_on_addr_match) begin + // Setup tdata1 and tdata2 for trigger breakpoint + if (!cfg.enable_debug_single_step) + gen_dbg_trigger_setup_with_addr_match(1); //use_dscratch0=1, num of trigger iterations > 1 allowed + else + gen_dbg_trigger_setup_with_addr_match(0); //use_dscratch0=0, num of trigger iterations = 1 + end if (cfg.enable_ebreak_in_debug_rom) begin // send dpc and dcsr to testbench, as this handshake will be // executed twice due to the ebreak loop, there should be no change @@ -93,7 +100,11 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; gen_dcsr_ebreak(); end if (cfg.enable_debug_single_step) begin - gen_single_step_logic(); + if ((cfg_corev.debug_trigger_before_single_step & cfg_corev.setup_debug_trigger_on_addr_match) || + (cfg_corev.debug_ebreak_before_single_step & cfg_corev.set_dcsr_ebreak)) + gen_single_step_logic_if_trigger_ebreak(); + else + gen_single_step_logic(); end gen_dpc_update(); // write DCSR to the testbench for any analysis @@ -167,6 +178,169 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; // original section instr_stream.push_back(".section text"); endfunction : gen_debug_exception_handler - + + // Function: gen_dbg_trigger_setup_with_addr_match + // Inputs int use_dscratch0, dscratch0 is used to store number of + // iterations and overlaps its usage for single step routine as well + // So this input is to differentiate code generation for different + // scenrios with or without single step overlap in the tests + // + // Description: Setup trigger breakpoint setup with instruction address + // match. Uses random config item trigger_addr_offset to set trigger + // address adding this random offset to depc value + // Use config trigger_iterations with use_dscratch0=1 to setup trigger + // multiple times in a single test. + virtual function void gen_dbg_trigger_setup_with_addr_match(int use_dscratch0=0); + + if(use_dscratch0) begin + str = {$sformatf("csrw 0x%0x, x%0d", DSCRATCH1, cfg.scratch_reg), + // Only un-set tdata1.execute if it is 1 and the iterations counter + // is at 0 (has finished expected iterations) + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, TDATA1), + $sformatf("andi x%0d, x%0d, 4", cfg.scratch_reg, cfg.scratch_reg), + // If tdata1.execute is 0, set to 1 and set the counter + $sformatf("beqz x%0d, 1f", cfg.scratch_reg), + // Check DCSR.cause, if cause was trigger-module, continue + // else dont change trigger configuration + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR), + $sformatf("slli x%0d, x%0d, 0x17", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("srli x%0d, x%0d, 0x1d", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("li x%0d, 0x2", cfg.gpr[0]), + $sformatf("bne x%0d, x%0d, 3f", cfg.scratch_reg, cfg.gpr[0]), + + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH0), + // if the counter is greater than 0, decrement and continue further trigger iterations + $sformatf("bgtz x%0d, 2f", cfg.scratch_reg), + $sformatf("csrc 0x%0x, 0x4", TDATA1), + //Set TDATA2 = 0xffff_ffff as a hint for sw to skip any + //subsequent debug rom entry from re-enabling trigger execute + $sformatf("li x%0d, 0xffffffff", cfg.scratch_reg), + $sformatf("csrw 0x%0x, x%0d", TDATA2, cfg.scratch_reg), + $sformatf("beqz x0, 3f"), + // Set tdata1.execute, set tdata2 and the num_iterations counter, if + // TDATA2 != 0xffff_ffff + $sformatf("1: csrr x%0d, 0x%0x", cfg.scratch_reg, TDATA2), + $sformatf("li x%0d, 0xffffffff", cfg.gpr[0]), + $sformatf("beq x%0d, x%0d, 3f", cfg.scratch_reg, cfg.gpr[0]), + $sformatf("csrs 0x%0x, 0x4", TDATA1), + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DPC), + $sformatf("addi x%0d, x%0d, %0d", cfg.scratch_reg, cfg.scratch_reg, cfg_corev.trigger_addr_offset), + $sformatf("csrw 0x%0x, x%0d", TDATA2, cfg.scratch_reg), + $sformatf("li x%0d, %0d", cfg.scratch_reg, cfg_corev.trigger_iterations), + $sformatf("csrw 0x%0x, x%0d", DSCRATCH0, cfg.scratch_reg), + $sformatf("beqz x0, 3f"), + // Decrement dscratch counter and set tdata2 + $sformatf("2: csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH0), + $sformatf("addi x%0d, x%0d, -1", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("csrw 0x%0x, x%0d", DSCRATCH0, cfg.scratch_reg), + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DPC), + $sformatf("addi x%0d, x%0d, %0d", cfg.scratch_reg, cfg.scratch_reg, cfg_corev.trigger_addr_offset), + $sformatf("csrw 0x%0x, x%0d", TDATA2, cfg.scratch_reg), + // Restore scratch_reg value from dscratch1 + $sformatf("3: csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH1)}; + end + else begin + str = {$sformatf("csrw 0x%0x, x%0d", DSCRATCH1, cfg.scratch_reg), + // Only un-set tdata1.execute if it is 1 and the iterations counter + // is at 0 (has finished expected iterations) + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, TDATA1), + $sformatf("andi x%0d, x%0d, 4", cfg.scratch_reg, cfg.scratch_reg), + // If tdata1.execute is 0, set to 1 else clear + $sformatf("beqz x%0d, 1f", cfg.scratch_reg), + // Check DCSR.cause, if cause was trigger-module, continue + // else dont change trigger configuration + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR), + $sformatf("slli x%0d, x%0d, 0x17", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("srli x%0d, x%0d, 0x1d", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("li x%0d, 0x2", cfg.gpr[0]), + $sformatf("bne x%0d, x%0d, 3f", cfg.scratch_reg, cfg.gpr[0]), + + $sformatf("csrc 0x%0x, 0x4", TDATA1), + //Set TDATA2 = 0xffff_ffff as a hint for sw to skip any + //subsequent debug rom entry from re-enabling trigger execute + $sformatf("li x%0d, 0xffffffff", cfg.scratch_reg), + $sformatf("csrw 0x%0x, x%0d", TDATA2, cfg.scratch_reg), + $sformatf("beqz x0, 3f"), + // Set tdata1.execute, set tdata2, if + // TDATA2 != 0xffff_ffff + $sformatf("1: csrr x%0d, 0x%0x", cfg.scratch_reg, TDATA2), + $sformatf("li x%0d, 0xffffffff", cfg.gpr[0]), + $sformatf("beq x%0d, x%0d, 3f", cfg.scratch_reg, cfg.gpr[0]), + $sformatf("csrs 0x%0x, 0x4", TDATA1), + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DPC), + $sformatf("addi x%0d, x%0d, %0d", cfg.scratch_reg, cfg.scratch_reg, cfg_corev.trigger_addr_offset), + $sformatf("csrw 0x%0x, x%0d", TDATA2, cfg.scratch_reg), + $sformatf("beqz x0, 3f"), + // Restore scratch_reg value from dscratch1 + $sformatf("3: csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH1)}; + end + debug_main = {debug_main, str}; + + endfunction + + // Function: gen_single_step_logic_if_trigger_ebreak + // Description: The logic in this function is to setup single stepping, + // after 1 debug trigger or debug ebreak is triggered. + // This covers cases with trigger/ebreak and single step + // Debug entry cause Trigger/Ebreak -> Single Step Enable + virtual function void gen_single_step_logic_if_trigger_ebreak(); + str = {$sformatf("csrw 0x%0x, x%0d", DSCRATCH1, cfg.scratch_reg), + // Only un-set dcsr.step if it is 1 and the iterations counter + // is at 0 (has finished iterating) + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR), + $sformatf("andi x%0d, x%0d, 4", cfg.scratch_reg, cfg.scratch_reg), + // If dcsr.step is 0, set to 1 and set the counter, if + // trigger was the debug entry cause + $sformatf("beqz x%0d, 1f", cfg.scratch_reg), + // Check DCSR.cause, if cause was step, continue + // else dont change step configuration + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR), + $sformatf("slli x%0d, x%0d, 0x17", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("srli x%0d, x%0d, 0x1d", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("li x%0d, 0x4", cfg.gpr[0]), + $sformatf("bne x%0d, x%0d, 3f", cfg.scratch_reg, cfg.gpr[0]), + + $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH0), + // if the counter is greater than 0, decrement and continue single stepping + $sformatf("bgtz x%0d, 2f", cfg.scratch_reg), + $sformatf("csrc 0x%0x, 0x4", DCSR), + //Set DSCRATCH0 = 0xffff_ffff as a hint for sw to skip any + //subsequent debug rom entry from re-enabling step + $sformatf("li x%0d, 0xffffffff", cfg.scratch_reg), + $sformatf("csrw 0x%0x, x%0d", DSCRATCH0, cfg.scratch_reg), + $sformatf("beqz x0, 3f"), + // Check DCSR.cause, if cause was trigger-module breakpoint or ebreak, set dcsr.step + // else dont change configuration + $sformatf("1: csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR), + $sformatf("slli x%0d, x%0d, 0x17", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("srli x%0d, x%0d, 0x1d", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("li x%0d, 0x1", cfg.gpr[0]), + $sformatf("beq x%0d, x%0d, 11f", cfg.scratch_reg, cfg.gpr[0]), + $sformatf("li x%0d, 0x2", cfg.gpr[0]), + $sformatf("beq x%0d, x%0d, 11f", cfg.scratch_reg, cfg.gpr[0]), + $sformatf("beqz x0, 3f"), + // Set dcsr.step and the num_iterations counter, if + // DSCRATCH0 != 0xffff_ffff + $sformatf("11: csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH0), + $sformatf("li x%0d, 0xffffffff", cfg.gpr[0]), + $sformatf("beq x%0d, x%0d, 3f", cfg.scratch_reg, cfg.gpr[0]), + $sformatf("csrs 0x%0x, 0x4", DCSR), + $sformatf("li x%0d, %0d", cfg.scratch_reg, cfg.single_step_iterations), + $sformatf("csrw 0x%0x, x%0d", DSCRATCH0, cfg.scratch_reg), + $sformatf("beqz x0, 3f"), + // Decrement dscratch counter + $sformatf("2: csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH0), + $sformatf("addi x%0d, x%0d, -1", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("csrw 0x%0x, x%0d", DSCRATCH0, cfg.scratch_reg), + // Restore scratch_reg value from dscratch1 + $sformatf("3: csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH1) + }; + debug_main = {debug_main, str}; + // write dpc to testbench + gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DPC)); + // write out the counter to the testbench + gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DSCRATCH0)); + endfunction + endclass : cv32e40p_debug_rom_gen From 4a4b12aa5eb7e64b1d77438bc164a3a97ae11dc2 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 10:55:40 +0800 Subject: [PATCH 04/17] improve debug req randomization for uvme_cv32e40p_reduced_rand_debug_req_c Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv | 2 +- .../env/uvme/vseq/uvme_cv32e40p_random_debug_vseq.sv | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv index 7baeb00a26..4d3b573608 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv @@ -164,12 +164,12 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; //Use this plusarg - include_xpulp_instr_in_debug_rom to include xpulp instr //In random debug_rom instructions. Added for v2 debug tests with xpulp. if (cv32e40p_cfg.xpulp_instr_in_debug_rom && is_debug_program && $test$plusargs("include_xpulp_instr_in_debug_rom")) begin + `uvm_info("cv32e40p_rand_instr_stream", $sformatf("Including xpulp instr in debug_rom"), UVM_LOW) foreach(instr_list[i]) begin randcase 1: randomize_debug_rom_instr(.instr(instr_list[i]), .is_in_debug(is_debug_program), .disable_dist()); 2: randomize_instr(instr_list[i], is_debug_program); endcase - `uvm_info("cv32e40p_rand_instr_stream", $sformatf("include_xpulp_instr_in_debug_rom set- Including xpulp instr in debug_rom"), UVM_LOW) end end else begin diff --git a/cv32e40p/env/uvme/vseq/uvme_cv32e40p_random_debug_vseq.sv b/cv32e40p/env/uvme/vseq/uvme_cv32e40p_random_debug_vseq.sv index ff08ab31fe..2153d8416f 100644 --- a/cv32e40p/env/uvme/vseq/uvme_cv32e40p_random_debug_vseq.sv +++ b/cv32e40p/env/uvme/vseq/uvme_cv32e40p_random_debug_vseq.sv @@ -73,11 +73,12 @@ class uvme_cv32e40p_reduced_rand_debug_req_c extends uvme_cv32e40p_random_debug_ } constraint num_dgb_req_c { - num_of_debug_req inside {[1:3]}; + num_of_debug_req inside {[1:5]}; } extern function new(string name="uvme_cv32e40p_reduced_rand_debug_req"); extern virtual task body(); + extern virtual task rand_delay(); endclass : uvme_cv32e40p_reduced_rand_debug_req_c function uvme_cv32e40p_reduced_rand_debug_req_c::new(string name="uvme_cv32e40p_reduced_rand_debug_req"); @@ -87,6 +88,12 @@ function uvme_cv32e40p_reduced_rand_debug_req_c::new(string name="uvme_cv32e40p_ end endfunction : new +task uvme_cv32e40p_reduced_rand_debug_req_c::rand_delay(); + std::randomize(dly) with { dly inside {[1:10000]}; + }; + #(dly); +endtask : rand_delay + task uvme_cv32e40p_reduced_rand_debug_req_c::body(); for (int i = 1; i <= num_of_debug_req; i++) begin uvma_debug_seq_item_c debug_req; From 39f2fece3abd4dcfdecd0fa58128085e976050cb Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 10:57:18 +0800 Subject: [PATCH 05/17] improve hwloop_debug test for better randomization Signed-off-by: Vaibhav Jain --- .../corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml | 2 +- .../programs/corev-dv/corev_rand_pulp_hwloop_debug/test.yaml | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml index 6f9ee69c08..91b5f89447 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml @@ -8,7 +8,7 @@ uvm_test: $(CV_CORE_LC)_instr_base_test description: > RISCV-DV generated random hwloop test with random debug plusargs: > - +instr_cnt=1000 + +instr_cnt=200 +num_of_sub_program=0 +insert_rand_directed_instr_stream=1 +test_rand_directed_instr_stream_num=6 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/test.yaml index daac496e0a..c3c1e52541 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/test.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/test.yaml @@ -8,4 +8,3 @@ description: > Random debug in xpulp hwloop stream plusargs: > +gen_reduced_rand_dbg_req - +num_debug_req=2 From 7f4022b7390f1b7ef73873f309001d5d28268bc0 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 11:00:00 +0800 Subject: [PATCH 06/17] add new debug trigger test_cfg file Signed-off-by: Vaibhav Jain --- cv32e40p/tests/test_cfg/debug_trigger_basic.yaml | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 cv32e40p/tests/test_cfg/debug_trigger_basic.yaml diff --git a/cv32e40p/tests/test_cfg/debug_trigger_basic.yaml b/cv32e40p/tests/test_cfg/debug_trigger_basic.yaml new file mode 100644 index 0000000000..1a0b6790b9 --- /dev/null +++ b/cv32e40p/tests/test_cfg/debug_trigger_basic.yaml @@ -0,0 +1,7 @@ +name: debug_trigger_basic +description: > + Use debug trigger with instr address +plusargs: > + +no_dret=1 + +setup_debug_trigger_on_addr_match=1 + +gen_debug_section=1 From 4e1c15850766dd1199d212f669011027c9d9106a Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 13:43:20 +0800 Subject: [PATCH 07/17] add cv32e40p_init for cv32e40p specific legal opcodes Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv | 14 +++++++++++++- cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv | 2 +- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv index 54f9191fa7..4160c8185c 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv @@ -39,6 +39,18 @@ class cv32e40p_illegal_instr extends riscv_illegal_instr; function new(string name=""); super.new(name); - endfunction + endfunction + + function void cv32e40p_init(riscv_instr_gen_config cfg); + this.cfg = cfg; + if (riscv_instr_pkg::RV32ZFINX inside {riscv_instr_pkg::supported_isa}) begin + legal_opcode = {legal_opcode, 7'b1000011, 7'b1000111, 7'b1001011, + 7'b1001111, 7'b1010011}; + end + if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin + legal_opcode = {legal_opcode, 7'b0001011, 7'b0101011, 7'b1011011, + 7'b1111011}; + end + endfunction endclass : cv32e40p_illegal_instr diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv index 63aa757eef..809e282739 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv @@ -34,9 +34,9 @@ package cv32e40p_instr_test_pkg; // RISCV-DV class override definitions `include "cv32e40p_rand_instr_stream.sv" + `include "cv32e40p_illegal_instr.sv" `include "cv32e40p_instr_sequence.sv" `include "cv32e40p_compressed_instr.sv" - `include "cv32e40p_illegal_instr.sv" `include "cv32e40p_privil_reg.sv" `include "cv32e40p_debug_rom_gen.sv" `include "cv32e40p_asm_program_gen.sv" From efe91b079d9e8ae7243f488ddeec005b424504de Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 13:46:52 +0800 Subject: [PATCH 08/17] replace insert_illegal_hint_instr with cv32e40p_insert_illegal_hint_instr using cv32e40p_illegal_instr object for cv32e40p specific values Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_instr_sequence.sv | 41 ++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv index a1181be52c..3756295b06 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv @@ -29,6 +29,7 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; cv32e40p_instr_gen_config cv32e40p_cfg; + cv32e40p_illegal_instr cv32_illegal_instr; // Illegal instruction generator `uvm_object_utils(cv32e40p_instr_sequence) @@ -37,6 +38,7 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; if(!uvm_config_db#(cv32e40p_instr_gen_config)::get(null, "*", "cv32e40p_instr_cfg", cv32e40p_cfg)) begin `uvm_fatal(get_full_name(), "Cannot get cv32e40p_instr_gen_config") end + cv32_illegal_instr = cv32e40p_illegal_instr::type_id::create("cv32_illegal_instr"); endfunction //Function: cv32e40p_instr_sequence::post_process_instr() @@ -275,11 +277,48 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; if (riscv_instr_pkg::support_pmp && !uvm_re_match(uvm_glob_to_re("*main*"), label_name)) begin instr_string_list.push_front(".align 2"); end - insert_illegal_hint_instr(); + cv32e40p_insert_illegal_hint_instr(); prefix = format_string($sformatf("%0d:", i), LABEL_STR_LEN); if(!is_main_program) begin generate_return_routine(prefix); end endfunction + // Similar to base class insert_illegal_hint_instr function + // Added cv32_illegal_instr.cv32e40p_init() to include cv32e40p + // specific legal opcodes + function void cv32e40p_insert_illegal_hint_instr(); + int bin_instr_cnt; + int idx; + string str; + cv32_illegal_instr.init(cfg); + cv32_illegal_instr.cv32e40p_init(cfg); // Init legal_opcode for cv32e40p + bin_instr_cnt = instr_cnt * cfg.illegal_instr_ratio / 1000; + if (bin_instr_cnt >= 0) begin + `uvm_info(`gfn, $sformatf("Injecting %0d illegal instructions, ratio %0d/100", + bin_instr_cnt, cfg.illegal_instr_ratio), UVM_LOW) + repeat (bin_instr_cnt) begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(cv32_illegal_instr, + exception != kHintInstr;) + str = {indent, $sformatf(".4byte 0x%s # %0s", + cv32_illegal_instr.get_bin_str(), cv32_illegal_instr.comment)}; + idx = $urandom_range(0, instr_string_list.size()); + instr_string_list.insert(idx, str); + end + end + bin_instr_cnt = instr_cnt * cfg.hint_instr_ratio / 1000; + if (bin_instr_cnt >= 0) begin + `uvm_info(`gfn, $sformatf("Injecting %0d HINT instructions, ratio %0d/100", + bin_instr_cnt, cfg.illegal_instr_ratio), UVM_LOW) + repeat (bin_instr_cnt) begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(cv32_illegal_instr, + exception == kHintInstr;) + str = {indent, $sformatf(".2byte 0x%s # %0s", + cv32_illegal_instr.get_bin_str(), cv32_illegal_instr.comment)}; + idx = $urandom_range(0, instr_string_list.size()); + instr_string_list.insert(idx, str); + end + end + endfunction + endclass From a72eea24f85715c9689c1a9832c0c3325baf01e3 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Mon, 30 Oct 2023 14:52:34 +0800 Subject: [PATCH 09/17] update cv32e40pv2_interrupt_debug regress yaml for random debug trigger tests Signed-off-by: Vaibhav Jain --- .../regress/cv32e40pv2_interrupt_debug.yaml | 67 +++++++++++++++++++ .../cv32e40pv2_interrupt_debug_short.yaml | 64 ++++++++++++++++++ 2 files changed, 131 insertions(+) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 0b23a62fcb..f1c294d297 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -26,12 +26,14 @@ tests: description: corev_rand_debug dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + num: 1 corev_rand_debug_ebreak: build: uvmt_cv32e40p description: corev_rand_debug_ebreak dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + num: 1 corev_rand_debug_ebreak_xpulp: build: uvmt_cv32e40p @@ -91,6 +93,7 @@ tests: description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + num: 1 debug_test: build: uvmt_cv32e40p @@ -164,6 +167,14 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" test_cfg: debug_single_step_en + corev_rand_pulp_instr_debug_trigger_test: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + test_cfg: debug_trigger_basic + corev_rand_pulp_instr_interrupt_test: testname: corev_rand_pulp_instr_test description: pulp instr test with random interrupts @@ -194,6 +205,30 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_single_step_en + corev_rand_pulp_hwloop_debug_trigger: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger on instr addr match + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic + + corev_rand_pulp_hwloop_debug_trigger_with_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_ebreak + + corev_rand_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_single_step_en + corev_rand_pulp_hwloop_debug_with_interrupt: testname: corev_rand_pulp_hwloop_debug description: hwloop debug with interrupt random test @@ -202,6 +237,22 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: gen_rand_int + corev_rand_pulp_hwloop_debug_with_int_debug_trigger: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt and debug trigger random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic + + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts @@ -218,3 +269,19 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" test_cfg: debug_single_step_en + corev_rand_pulp_hwloop_exception_debug_trigger: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + test_cfg: debug_trigger_basic + + corev_rand_pulp_hwloop_exception_with_int_debug_trigger: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + test_cfg: gen_rand_int,debug_trigger_basic + diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index bbb5824c4f..ca3d2efd71 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -55,6 +55,14 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" test_cfg: debug_single_step_en + corev_rand_pulp_instr_debug_trigger_test: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + test_cfg: debug_trigger_basic + corev_rand_pulp_instr_interrupt_test: testname: corev_rand_pulp_instr_test description: pulp instr test with random interrupts @@ -85,6 +93,30 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_single_step_en + corev_rand_pulp_hwloop_debug_trigger: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger on instr addr match + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic + + corev_rand_pulp_hwloop_debug_trigger_with_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_ebreak + + corev_rand_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_single_step_en + corev_rand_pulp_hwloop_debug_with_interrupt: testname: corev_rand_pulp_hwloop_debug description: hwloop debug with interrupt random test @@ -93,6 +125,22 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: gen_rand_int + corev_rand_pulp_hwloop_debug_with_int_debug_trigger: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt and debug trigger random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic + + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts @@ -109,6 +157,22 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" test_cfg: debug_single_step_en + corev_rand_pulp_hwloop_exception_debug_trigger: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + test_cfg: debug_trigger_basic + + corev_rand_pulp_hwloop_exception_with_int_debug_trigger: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + test_cfg: gen_rand_int,debug_trigger_basic + debug_test: build: uvmt_cv32e40p description: debug_test (adapted from v1) From e8c924d0c60abf52c7006af909ffc1fc9bb0ad85 Mon Sep 17 00:00:00 2001 From: bsm Date: Mon, 30 Oct 2023 15:41:19 +0800 Subject: [PATCH 10/17] Fix fp failing test from regression run Signed-off-by: bsm --- .../programs/custom/fpu_bugs_test/test.c | 34 ++++++++++++++++--- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c index fa8afa1c95..9b2687e115 100644 --- a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c +++ b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c @@ -48,6 +48,10 @@ int main() { unsigned int i = 0, j = 0, error = 0; + float *P_INPUT = INPUT; + float *P_EXP_RES = EXP_RES; + float *P_RES = RES; + // Floating Point enable fp_enable(); @@ -55,35 +59,55 @@ int main() __asm__ volatile("csrw frm, 0x4"); __asm__ volatile("csrw fflags, 0x0"); - __asm__ volatile("fmadd.s %0, %1, %2, %3" : "=r"(RES[i]) : "r"(INPUT[j++]), "r"(INPUT[j++]), "r"(INPUT[j++]) ); +#ifdef ZFINX + __asm__ volatile("fmadd.s %0, %1, %2, %3" : "=r"(P_RES[i]) : "r"(P_INPUT[j++]), "r"(P_INPUT[j++]), "r"(P_INPUT[j++]) ); +#else + __asm__ volatile("fmadd.s %0, %1, %2, %3" : "=f"(P_RES[i]) : "f"(P_INPUT[j++]), "f"(P_INPUT[j++]), "f"(P_INPUT[j++]) ); +#endif __asm__ volatile("csrr %0, fflags" : "=r"(FLAGS[i++])); // #727 __asm__ volatile("csrw frm, 0x2"); __asm__ volatile("csrw fflags, 0x0"); - __asm__ volatile("fcvt.w.s %0, %1" : "=r"(RES[i]) : "r"(INPUT[j++]) ); +#ifdef ZFINX + __asm__ volatile("fcvt.w.s %0, %1" : "=r"(P_RES[i]) : "r"(P_INPUT[j++]) ); +#else + __asm__ volatile("fcvt.w.s %0, %1" : "=r"(P_RES[i]) : "f"(P_INPUT[j++]) ); +#endif __asm__ volatile("csrr %0, fflags" : "=r"(FLAGS[i++])); // #728 __asm__ volatile("csrw frm, 0x2"); __asm__ volatile("csrw fflags, 0x0"); - __asm__ volatile("fmul.s %0, %1, %2" : "=r"(RES[i]) : "r"(INPUT[j++]), "r"(INPUT[j++]) ); +#ifdef ZFINX + __asm__ volatile("fmul.s %0, %1, %2" : "=r"(P_RES[i]) : "r"(P_INPUT[j++]), "r"(P_INPUT[j++]) ); +#else + __asm__ volatile("fmul.s %0, %1, %2" : "=f"(P_RES[i]) : "f"(P_INPUT[j++]), "f"(P_INPUT[j++]) ); +#endif __asm__ volatile("csrr %0, fflags" : "=r"(FLAGS[i++])); // #729 __asm__ volatile("csrw frm, 0x3"); __asm__ volatile("csrw fflags, 0x0"); - __asm__ volatile("fmul.s %0, %1, %2" : "=r"(RES[i]) : "r"(INPUT[j++]), "r"(INPUT[j++]) ); +#ifdef ZFINX + __asm__ volatile("fmul.s %0, %1, %2" : "=r"(P_RES[i]) : "r"(P_INPUT[j++]), "r"(P_INPUT[j++]) ); +#else + __asm__ volatile("fmul.s %0, %1, %2" : "=f"(P_RES[i]) : "f"(P_INPUT[j++]), "f"(P_INPUT[j++]) ); +#endif __asm__ volatile("csrr %0, fflags" : "=r"(FLAGS[i++])); // #94 __asm__ volatile("csrw frm, 0x0"); __asm__ volatile("csrw fflags, 0x0"); - __asm__ volatile("fdiv.s %0, %1, %2" : "=r"(RES[i]) : "r"(INPUT[j++]), "r"(INPUT[j++]) ); +#ifdef ZFINX + __asm__ volatile("fdiv.s %0, %1, %2" : "=r"(P_RES[i]) : "r"(P_INPUT[j++]), "r"(P_INPUT[j++]) ); +#else + __asm__ volatile("fdiv.s %0, %1, %2" : "=f"(P_RES[i]) : "f"(P_INPUT[j++]), "f"(P_INPUT[j++]) ); +#endif __asm__ volatile("csrr %0, fflags" : "=r"(FLAGS[i++])); for (j = 0; j < i ; j++) { From 329ec5fdd7d5ed069f761a49a01681d8fd1556cc Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 31 Oct 2023 11:45:32 +0800 Subject: [PATCH 11/17] add new pkg file cv32e40p_instr_pkg.sv for cv32e40p to add on to riscv_instr_pkg Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_instr_pkg.sv | 36 +++++++++++++++++++ .../env/corev-dv/cv32e40p_instr_test_pkg.sv | 3 ++ 2 files changed, 39 insertions(+) create mode 100644 cv32e40p/env/corev-dv/cv32e40p_instr_pkg.sv diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_pkg.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_pkg.sv new file mode 100644 index 0000000000..eeb0993824 --- /dev/null +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_pkg.sv @@ -0,0 +1,36 @@ +// +// Copyright 2023 OpenHW Group +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 +//**************************************************************************************************************** + + +package cv32e40p_instr_pkg; + + typedef enum bit [11:0] { + // User Custom CSRs + LPSTART0 = 'hCC0, // Hardware Loop 0 Start + LPEND0 = 'hCC1, // Hardware Loop 0 End + LPCOUNT0 = 'hCC2, // Hardware Loop 0 Counter + LPSTART1 = 'hCC4, // Hardware Loop 1 Start + LPEND1 = 'hCC5, // Hardware Loop 1 End + LPCOUNT1 = 'hCC6, // Hardware Loop 1 Counter + UHARTID = 'hCD0, // Hardware Thread ID + PRIVLV = 'hCD1, // Privilege Level + ZFINX = 'hCD2 // ZFINX ISA + } custom_csr_reg_t; + +endpackage diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv index 809e282739..1bfb8c8463 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv @@ -14,12 +14,15 @@ * limitations under the License. */ +`include "cv32e40p_instr_pkg.sv" + package cv32e40p_instr_test_pkg; parameter int HWLOOP_LABEL_STR_LEN = 32; import uvm_pkg::*; import riscv_instr_pkg::*; + import cv32e40p_instr_pkg::*; import riscv_instr_test_pkg::*; import riscv_signature_pkg::*; import corev_instr_test_pkg::*; From 1a6ab26ed667a30b8a97da41cca3b905098f4daf Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 31 Oct 2023 12:24:38 +0800 Subject: [PATCH 12/17] update illegal_instr_handler to take into account hwloop execution Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_asm_program_gen.sv | 40 ++++++++++++++++--- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv index c5d6b4049a..ed095c67a0 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv @@ -550,6 +550,9 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Override Illegal instruction handler - gen_illegal_instr_handler // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack + // With RV32X enabled, check for illegal instr on the last instr of hwloop + // If true, then set MEPC to first instr of hwloop instead of simply + // incrementing by 4. virtual function void gen_illegal_instr_handler(int hart); string instr[$]; cv32e40p_instr_gen_config corev_cfg; @@ -558,11 +561,38 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; gen_signature_handshake(instr, CORE_STATUS, ILLEGAL_INSTR_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); - instr = {instr, - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), - $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), - $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) - }; + if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin + instr = {instr, + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT1), + $sformatf("li x%0d, 2", cfg.gpr[1]), + $sformatf("bge x%0d, x%0d, 1f", cfg.gpr[0], cfg.gpr[1]), + $sformatf("2: csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT0), + $sformatf("li x%0d, 2", cfg.gpr[1]), + $sformatf("bge x%0d, x%0d, 3f", cfg.gpr[0], cfg.gpr[1]), + $sformatf("beqz x0, 4f"), + $sformatf("1: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND1), + $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), + $sformatf("bne x%0d, x%0d, 2b", cfg.gpr[0], cfg.gpr[1]), + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART1), + $sformatf("beqz x0, 5f"), + $sformatf("3: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND0), + $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), + $sformatf("bne x%0d, x%0d, 4f", cfg.gpr[0], cfg.gpr[1]), + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART0), + $sformatf("beqz x0, 5f"), + $sformatf("4: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("5: csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) + }; + end else begin + instr = {instr, + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) + }; + end // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack //pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); pop_regfile_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr, corev_cfg); From 1517a66be5ac7326552fb40f79029abfe4160379 Mon Sep 17 00:00:00 2001 From: bsm Date: Thu, 2 Nov 2023 09:42:25 +0800 Subject: [PATCH 13/17] Add core-v-verif rvvi interface Signed-off-by: bsm --- cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv | 172 +++++++++++++++++++++++ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 22 +++ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 111 ++++++++++++++- 3 files changed, 303 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv index a4b7794b34..66ad145f50 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv @@ -49,4 +49,176 @@ .field_name({"csr_", `"csr_name`", "_vif0"}), \ .value(dut_wrap.cv32e40p_tb_wrapper_i.rvfi_csr_``csr_name``_if_0_i)); + +`define PORTMAP_CSR_RVFI_2_RVVI(CSR_NAME) \ + .csr_``CSR_NAME``_rmask (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_csr_``CSR_NAME``_rmask), \ + .csr_``CSR_NAME``_wmask (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_csr_``CSR_NAME``_wmask), \ + .csr_``CSR_NAME``_rdata (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_csr_``CSR_NAME``_rdata), \ + .csr_``CSR_NAME``_wdata (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_csr_``CSR_NAME``_wdata), + + +`define STRINGIFY(x) `"x`" + +//////////////////////////////////////////////////////////////////////////// +// CSR definitions +//////////////////////////////////////////////////////////////////////////// +`define CSR_FFLAGS_ADDR 32'h001 +`define CSR_FRM_ADDR 32'h002 +`define CSR_FCSR_ADDR 32'h003 +`define CSR_JVT_ADDR 32'h017 +`define CSR_MSTATUS_ADDR 32'h300 +`define CSR_MISA_ADDR 32'h301 +`define CSR_MIE_ADDR 32'h304 +`define CSR_MTVEC_ADDR 32'h305 +`define CSR_MCOUNTEREN_ADDR 32'h306 +`define CSR_MENVCFG_ADDR 32'h30A +`define CSR_MSTATEEN0_ADDR 32'h30C +`define CSR_MSTATEEN1_ADDR 32'h30D +`define CSR_MSTATEEN2_ADDR 32'h30E +`define CSR_MSTATEEN3_ADDR 32'h30F +`define CSR_MTVT_ADDR 32'h307 // only available when SMCLIC=1 +`define CSR_MSTATUSH_ADDR 32'h310 +`define CSR_MENVCFGH_ADDR 32'h31A +`define CSR_MSTATEEN0H_ADDR 32'h31C +`define CSR_MSTATEEN1H_ADDR 32'h31D +`define CSR_MSTATEEN2H_ADDR 32'h31E +`define CSR_MSTATEEN3H_ADDR 32'h31F +`define CSR_MCOUNTINHIBIT_ADDR 32'h320 +`define CSR_MSCRATCH_ADDR 32'h340 +`define CSR_MEPC_ADDR 32'h341 +`define CSR_MCAUSE_ADDR 32'h342 +`define CSR_MTVAL_ADDR 32'h343 +`define CSR_MIP_ADDR 32'h344 +`define CSR_MNXTI_ADDR 32'h345 // only available when SMCLIC=1 +`define CSR_MINTSTATUS_ADDR 32'h346 // only available when SMCLIC=1 +`define CSR_MINTTHRESH_ADDR 32'h347 // only available when SMCLIC=1 +`define CSR_MSCRATCHCSW_ADDR 32'h348 // only available when SMCLIC=1 +`define CSR_MCLICBASE_ADDR 32'h34A // only available when SMCLIC=1 +`define CSR_MSECCFG 32'h747 +`define CSR_MSECCFGH 32'h757 +`define CSR_TSELECT_ADDR 32'h7A0 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TDATA1_ADDR 32'h7A1 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TDATA2_ADDR 32'h7A2 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TDATA3_ADDR 32'h7A3 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TINFO_ADDR 32'h7A4 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TCONTROL_ADDR 32'h7A5 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_MCONTEXT_ADDR 32'h7A8 +`define CSR_MSCONTEXT_ADDR 32'h7A9 +`define CSR_SCONTEXT_ADDR 32'h7AA +`define CSR_DCSR_ADDR 32'h7B0 +`define CSR_DPC_ADDR 32'h7B1 +`define CSR_DSCRATCH0_ADDR 32'h7B2 +`define CSR_DSCRATCH1_ADDR 32'h7B3 +`define CSR_MCYCLE_ADDR 32'hB00 +`define CSR_MINSTRET_ADDR 32'hB02 +`define CSR_CYCLE_ADDR 32'hC00 +`define CSR_INSTRET_ADDR 32'hC02 +`define CSR_CYCLEH_ADDR 32'hC80 +`define CSR_INSTRETH_ADDR 32'hC82 +`define CSR_LPSTART0_ADDR 32'hCC0 +`define CSR_LPEND0_ADDR 32'hCC1 +`define CSR_LPCOUNT0_ADDR 32'hCC2 +`define CSR_LPSTART1_ADDR 32'hCC4 +`define CSR_LPEND1_ADDR 32'hCC5 +`define CSR_LPCOUNT1_ADDR 32'hCC6 +`define CSR_MHPMCOUNTER3_ADDR 32'hB03 +`define CSR_MHPMCOUNTER4_ADDR 32'hB04 +`define CSR_MHPMCOUNTER5_ADDR 32'hB05 +`define CSR_MHPMCOUNTER6_ADDR 32'hB06 +`define CSR_MHPMCOUNTER7_ADDR 32'hB07 +`define CSR_MHPMCOUNTER8_ADDR 32'hB08 +`define CSR_MHPMCOUNTER9_ADDR 32'hB09 +`define CSR_MHPMCOUNTER10_ADDR 32'hB0A +`define CSR_MHPMCOUNTER11_ADDR 32'hB0B +`define CSR_MHPMCOUNTER12_ADDR 32'hB0C +`define CSR_MHPMCOUNTER13_ADDR 32'hB0D +`define CSR_MHPMCOUNTER14_ADDR 32'hB0E +`define CSR_MHPMCOUNTER15_ADDR 32'hB0F +`define CSR_MHPMCOUNTER16_ADDR 32'hB10 +`define CSR_MHPMCOUNTER17_ADDR 32'hB11 +`define CSR_MHPMCOUNTER18_ADDR 32'hB12 +`define CSR_MHPMCOUNTER19_ADDR 32'hB13 +`define CSR_MHPMCOUNTER20_ADDR 32'hB14 +`define CSR_MHPMCOUNTER21_ADDR 32'hB15 +`define CSR_MHPMCOUNTER22_ADDR 32'hB16 +`define CSR_MHPMCOUNTER23_ADDR 32'hB17 +`define CSR_MHPMCOUNTER24_ADDR 32'hB18 +`define CSR_MHPMCOUNTER25_ADDR 32'hB19 +`define CSR_MHPMCOUNTER26_ADDR 32'hB1A +`define CSR_MHPMCOUNTER27_ADDR 32'hB1B +`define CSR_MHPMCOUNTER28_ADDR 32'hB1C +`define CSR_MHPMCOUNTER29_ADDR 32'hB1D +`define CSR_MHPMCOUNTER30_ADDR 32'hB1E +`define CSR_MHPMCOUNTER31_ADDR 32'hB1F +`define CSR_MHPMCOUNTER3H_ADDR 32'hB83 +`define CSR_MHPMCOUNTER4H_ADDR 32'hB84 +`define CSR_MHPMCOUNTER5H_ADDR 32'hB85 +`define CSR_MHPMCOUNTER6H_ADDR 32'hB86 +`define CSR_MHPMCOUNTER7H_ADDR 32'hB87 +`define CSR_MHPMCOUNTER8H_ADDR 32'hB88 +`define CSR_MHPMCOUNTER9H_ADDR 32'hB89 +`define CSR_MHPMCOUNTER10H_ADDR 32'hB8A +`define CSR_MHPMCOUNTER11H_ADDR 32'hB8B +`define CSR_MHPMCOUNTER12H_ADDR 32'hB8C +`define CSR_MHPMCOUNTER13H_ADDR 32'hB8D +`define CSR_MHPMCOUNTER14H_ADDR 32'hB8E +`define CSR_MHPMCOUNTER15H_ADDR 32'hB8F +`define CSR_MHPMCOUNTER16H_ADDR 32'hB90 +`define CSR_MHPMCOUNTER17H_ADDR 32'hB91 +`define CSR_MHPMCOUNTER18H_ADDR 32'hB92 +`define CSR_MHPMCOUNTER19H_ADDR 32'hB93 +`define CSR_MHPMCOUNTER20H_ADDR 32'hB94 +`define CSR_MHPMCOUNTER21H_ADDR 32'hB95 +`define CSR_MHPMCOUNTER22H_ADDR 32'hB96 +`define CSR_MHPMCOUNTER23H_ADDR 32'hB97 +`define CSR_MHPMCOUNTER24H_ADDR 32'hB98 +`define CSR_MHPMCOUNTER25H_ADDR 32'hB99 +`define CSR_MHPMCOUNTER26H_ADDR 32'hB9A +`define CSR_MHPMCOUNTER27H_ADDR 32'hB9B +`define CSR_MHPMCOUNTER28H_ADDR 32'hB9C +`define CSR_MHPMCOUNTER29H_ADDR 32'hB9D +`define CSR_MHPMCOUNTER30H_ADDR 32'hB9E +`define CSR_MHPMCOUNTER31H_ADDR 32'hB9F +`define CSR_MHPMEVENT3_ADDR 32'h323 +`define CSR_MHPMEVENT4_ADDR 32'h324 +`define CSR_MHPMEVENT5_ADDR 32'h325 +`define CSR_MHPMEVENT6_ADDR 32'h326 +`define CSR_MHPMEVENT7_ADDR 32'h327 +`define CSR_MHPMEVENT8_ADDR 32'h328 +`define CSR_MHPMEVENT9_ADDR 32'h329 +`define CSR_MHPMEVENT10_ADDR 32'h32A +`define CSR_MHPMEVENT11_ADDR 32'h32B +`define CSR_MHPMEVENT12_ADDR 32'h32C +`define CSR_MHPMEVENT13_ADDR 32'h32D +`define CSR_MHPMEVENT14_ADDR 32'h32E +`define CSR_MHPMEVENT15_ADDR 32'h32F +`define CSR_MHPMEVENT16_ADDR 32'h330 +`define CSR_MHPMEVENT17_ADDR 32'h331 +`define CSR_MHPMEVENT18_ADDR 32'h332 +`define CSR_MHPMEVENT19_ADDR 32'h333 +`define CSR_MHPMEVENT20_ADDR 32'h334 +`define CSR_MHPMEVENT21_ADDR 32'h335 +`define CSR_MHPMEVENT22_ADDR 32'h336 +`define CSR_MHPMEVENT23_ADDR 32'h337 +`define CSR_MHPMEVENT24_ADDR 32'h338 +`define CSR_MHPMEVENT25_ADDR 32'h339 +`define CSR_MHPMEVENT26_ADDR 32'h33A +`define CSR_MHPMEVENT27_ADDR 32'h33B +`define CSR_MHPMEVENT28_ADDR 32'h33C +`define CSR_MHPMEVENT29_ADDR 32'h33D +`define CSR_MHPMEVENT30_ADDR 32'h33E +`define CSR_MHPMEVENT31_ADDR 32'h33F +`define CSR_MCYCLEH_ADDR 32'hB80 +`define CSR_MINSTRETH_ADDR 32'hB82 +`define CSR_CPUCTRL_ADDR 32'hBF0 +`define CSR_SECURESEED0_ADDR 32'hBF9 +`define CSR_SECURESEED1_ADDR 32'hBFA +`define CSR_SECURESEED2_ADDR 32'hBFC +`define CSR_MVENDORID_ADDR 32'hF11 +`define CSR_MARCHID_ADDR 32'hF12 +`define CSR_MIMPID_ADDR 32'hF13 +`define CSR_MHARTID_ADDR 32'hF14 +`define CSR_MCONFIGPTR_ADDR 32'hF15 + + `endif // __UVMT_CV32E40P_MACROS_SV__ diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index 8e8ef35c42..ee1bab8cd7 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -508,6 +508,28 @@ module uvmt_cv32e40p_tb; uvmt_cv32e40p_debug_assert u_debug_assert(.cov_assert_if(debug_cov_assert_if)); + // simplify rvvi for coverage + uvmt_cv32e40p_rvvi_if cv32e40p_rvvi ( + .clk (clknrst_if.clk), + .valid (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_valid[0]), + .insn (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_insn[uvme_cv32e40p_pkg::ILEN*0+:uvme_cv32e40p_pkg::ILEN]), + .trap (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_trap.trap), + .pc_rdata (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_pc_rdata), + .interrupt_if (interrupt_if), + .debug_if (debug_if), + `PORTMAP_CSR_RVFI_2_RVVI(lpstart0) + `PORTMAP_CSR_RVFI_2_RVVI(lpend0) + `PORTMAP_CSR_RVFI_2_RVVI(lpcount0) + `PORTMAP_CSR_RVFI_2_RVVI(lpstart1) + `PORTMAP_CSR_RVFI_2_RVVI(lpend1) + `PORTMAP_CSR_RVFI_2_RVVI(lpcount1) + `PORTMAP_CSR_RVFI_2_RVVI(mie) + `PORTMAP_CSR_RVFI_2_RVVI(mip) + `PORTMAP_CSR_RVFI_2_RVVI(dcsr) + `PORTMAP_CSR_RVFI_2_RVVI(tdata) + .dummy () + ); + // IMPERAS DV `ifndef FORMAL `ifdef USE_ISS diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 214b566c0f..5b8ea92940 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -15,8 +15,6 @@ // limitations under the License. // - - // This file specifies all interfaces used by the CV32E40P test bench (uvmt_cv32e40p_tb). // Most interfaces support tasks to allow control by the ENV or test cases. @@ -334,4 +332,113 @@ interface uvmt_cv32e40p_debug_cov_assert_if endinterface : uvmt_cv32e40p_debug_cov_assert_if + +// core-v-verif simplify rvvi for coverage collection purpose + `define DEF_CSR_PORTS(CSR_NAME) \ + input logic [(XLEN-1):0] csr_``CSR_NAME``_rmask, \ + input logic [(XLEN-1):0] csr_``CSR_NAME``_wmask, \ + input logic [(XLEN-1):0] csr_``CSR_NAME``_rdata, \ + input logic [(XLEN-1):0] csr_``CSR_NAME``_wdata, + + `define DEF_CSR_PORTS_VEC(CSR_NAME, VEC_SIZE) \ + input logic [(``VEC_SIZE``-1):0][(XLEN-1):0] csr_``CSR_NAME``_rmask, \ + input logic [(``VEC_SIZE``-1):0][(XLEN-1):0] csr_``CSR_NAME``_wmask, \ + input logic [(``VEC_SIZE``-1):0][(XLEN-1):0] csr_``CSR_NAME``_rdata, \ + input logic [(``VEC_SIZE``-1):0][(XLEN-1):0] csr_``CSR_NAME``_wdata, + + `define ASSIGN_CSR_N_WB(CSR_ADDR, CSR_NAME) \ + bit csr_``CSR_NAME``_wb; \ + wire [31:0] csr_``CSR_NAME``_w; \ + wire [31:0] csr_``CSR_NAME``_r; \ + assign csr_``CSR_NAME``_w = csr_``CSR_NAME``_wdata & csr_``CSR_NAME``_wmask; \ + assign csr_``CSR_NAME``_r = csr_``CSR_NAME``_rdata & ~(csr_``CSR_NAME``_wmask); \ + assign csr[``CSR_ADDR] = csr_``CSR_NAME``_w | csr_``CSR_NAME``_r; \ + assign csr_wb[``CSR_ADDR] = csr_``CSR_NAME``_wb; \ + always @(csr[``CSR_ADDR]) begin \ + csr_``CSR_NAME``_wb = 1; \ + end \ + always @(posedge clk) begin \ + if (valid && csr_``CSR_NAME``_wb) begin \ + csr_``CSR_NAME``_wb = 0; \ + end \ + end + + `define ASSIGN_CSR_N_WB_VEC(CSR_ADDR, CSR_NAME, CSR_ID) \ + bit csr_``CSR_NAME````CSR_ID``_wb; \ + wire [31:0] csr_``CSR_NAME````CSR_ID``_w; \ + wire [31:0] csr_``CSR_NAME````CSR_ID``_r; \ + assign csr_``CSR_NAME````CSR_ID``_w = csr_``CSR_NAME``_wdata[``CSR_ID] & csr_``CSR_NAME``_wmask[``CSR_ID]; \ + assign csr_``CSR_NAME````CSR_ID``_r = csr_``CSR_NAME``_rdata[``CSR_ID] & ~(csr_``CSR_NAME``_wmask[``CSR_ID]); \ + assign csr[``CSR_ADDR] = csr_``CSR_NAME````CSR_ID``_w | csr_``CSR_NAME````CSR_ID``_r; \ + assign csr_wb[``CSR_ADDR] = csr_``CSR_NAME````CSR_ID``_wb; \ + always @(csr[``CSR_ADDR]) begin \ + csr_``CSR_NAME````CSR_ID``_wb = 1; \ + end \ + always @(posedge clk) begin \ + if (valid && csr_``CSR_NAME````CSR_ID``_wb) begin \ + csr_``CSR_NAME````CSR_ID``_wb = 0; \ + end \ + end + +interface uvmt_cv32e40p_rvvi_if #( + parameter int ILEN = 32, + parameter int XLEN = 32 +) ( + + input clk, + input valid, + input logic [(ILEN-1):0] insn, + input trap, + input logic [(XLEN-1):0] pc_rdata, + + uvma_interrupt_if interrupt_if, + uvma_debug_if debug_if, + + // Currently only define specific csrs for current usage + `DEF_CSR_PORTS(lpstart0) + `DEF_CSR_PORTS(lpend0) + `DEF_CSR_PORTS(lpcount0) + `DEF_CSR_PORTS(lpstart1) + `DEF_CSR_PORTS(lpend1) + `DEF_CSR_PORTS(lpcount1) + `DEF_CSR_PORTS(mie) + `DEF_CSR_PORTS(mip) + `DEF_CSR_PORTS(dcsr) + `DEF_CSR_PORTS_VEC(tdata,4) + + input dummy + +); + + wire [4095:0][32:0] csr; + wire [4095:0] csr_wb; + wire [31:0] valid_irq, valid_irq2; + wire [2:0] csr_dcsr_cause; + wire [31:0] csr_trig_pc; + + assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; + assign dbg_req = debug_if.debug_req; + + assign csr_dcsr_ebreakm = csr[`CSR_DCSR_ADDR][15]; + assign csr_dcsr_stepie = csr[`CSR_DCSR_ADDR][11]; + assign csr_dcsr_cause = csr[`CSR_DCSR_ADDR][8:6]; + assign csr_dcsr_step = csr[`CSR_DCSR_ADDR][2]; + assign csr_trig_execute = csr[`CSR_TDATA1_ADDR][2]; + assign csr_trig_pc = csr[`CSR_TDATA2_ADDR]; + + // can be expanded. Currently only define for current usage + `ASSIGN_CSR_N_WB(`CSR_LPSTART0_ADDR, lpstart0) + `ASSIGN_CSR_N_WB(`CSR_LPEND0_ADDR, lpend0) + `ASSIGN_CSR_N_WB(`CSR_LPCOUNT0_ADDR, lpcount0) + `ASSIGN_CSR_N_WB(`CSR_LPSTART1_ADDR, lpstart1) + `ASSIGN_CSR_N_WB(`CSR_LPEND1_ADDR, lpend1) + `ASSIGN_CSR_N_WB(`CSR_LPCOUNT1_ADDR, lpcount1) + `ASSIGN_CSR_N_WB(`CSR_MIE_ADDR, mie) + `ASSIGN_CSR_N_WB(`CSR_MIP_ADDR, mip) + `ASSIGN_CSR_N_WB(`CSR_DCSR_ADDR, dcsr) + `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA1_ADDR, tdata, 1); + `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA2_ADDR, tdata, 2); + +endinterface + `endif // __UVMT_CV32E40P_TB_IFS_SV__ From cc53aebb3df3a8bc03ff206bfe0aca04b9078edb Mon Sep 17 00:00:00 2001 From: bsm Date: Thu, 2 Nov 2023 13:19:56 +0800 Subject: [PATCH 14/17] Update uvmt_cv32e40p_rvvi_if to accomodate for hwloop coverage collection Signed-off-by: bsm --- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 11 +++++++++++ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 24 +++++++++++++++--------- 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index ee1bab8cd7..0b634d4d45 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -517,6 +517,7 @@ module uvmt_cv32e40p_tb; .pc_rdata (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_pc_rdata), .interrupt_if (interrupt_if), .debug_if (debug_if), + .debug_rom (dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.dm_halt_addr_i), `PORTMAP_CSR_RVFI_2_RVVI(lpstart0) `PORTMAP_CSR_RVFI_2_RVVI(lpend0) `PORTMAP_CSR_RVFI_2_RVVI(lpcount0) @@ -524,6 +525,7 @@ module uvmt_cv32e40p_tb; `PORTMAP_CSR_RVFI_2_RVVI(lpend1) `PORTMAP_CSR_RVFI_2_RVVI(lpcount1) `PORTMAP_CSR_RVFI_2_RVVI(mie) + `PORTMAP_CSR_RVFI_2_RVVI(mcause) `PORTMAP_CSR_RVFI_2_RVVI(mip) `PORTMAP_CSR_RVFI_2_RVVI(dcsr) `PORTMAP_CSR_RVFI_2_RVVI(tdata) @@ -554,6 +556,15 @@ module uvmt_cv32e40p_tb; // Specify time format for simulation (units_number, precision_number, suffix_string, minimum_field_width) $timeformat(-9, 3, " ns", 8); + + // Pass rvvi_if handle to cov_model + uvm_config_db#(virtual uvmt_cv32e40p_rvvi_if)::set( + .cntxt(null), + .inst_name("uvm_test_top.env.cov_model*"), + .field_name("cv32e40p_rvvi_vif"), + .value(cv32e40p_rvvi) + ); + // Add interfaces handles to uvm_config_db uvm_config_db#(virtual uvma_debug_if )::set(.cntxt(null), .inst_name("*.env.debug_agent"), .field_name("vif"), .value(debug_if) ); uvm_config_db#(virtual uvma_clknrst_if )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"), .value(clknrst_if) ); diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 5b8ea92940..a197afde29 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -393,6 +393,7 @@ interface uvmt_cv32e40p_rvvi_if #( uvma_interrupt_if interrupt_if, uvma_debug_if debug_if, + input logic [31:0] debug_rom, // Currently only define specific csrs for current usage `DEF_CSR_PORTS(lpstart0) @@ -402,6 +403,7 @@ interface uvmt_cv32e40p_rvvi_if #( `DEF_CSR_PORTS(lpend1) `DEF_CSR_PORTS(lpcount1) `DEF_CSR_PORTS(mie) + `DEF_CSR_PORTS(mcause) `DEF_CSR_PORTS(mip) `DEF_CSR_PORTS(dcsr) `DEF_CSR_PORTS_VEC(tdata,4) @@ -410,21 +412,24 @@ interface uvmt_cv32e40p_rvvi_if #( ); + wire [31:0] valid_irq; wire [4095:0][32:0] csr; wire [4095:0] csr_wb; - wire [31:0] valid_irq, valid_irq2; + wire [4:0] csr_mcause_ecp_code; wire [2:0] csr_dcsr_cause; wire [31:0] csr_trig_pc; - assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; - assign dbg_req = debug_if.debug_req; + assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; + assign dbg_req = debug_if.debug_req; - assign csr_dcsr_ebreakm = csr[`CSR_DCSR_ADDR][15]; - assign csr_dcsr_stepie = csr[`CSR_DCSR_ADDR][11]; - assign csr_dcsr_cause = csr[`CSR_DCSR_ADDR][8:6]; - assign csr_dcsr_step = csr[`CSR_DCSR_ADDR][2]; - assign csr_trig_execute = csr[`CSR_TDATA1_ADDR][2]; - assign csr_trig_pc = csr[`CSR_TDATA2_ADDR]; + assign csr_mcause_irq = csr[`CSR_MCAUSE_ADDR][31]; + assign csr_mcause_ecp_code = csr[`CSR_MCAUSE_ADDR][4:0]; + assign csr_dcsr_ebreakm = csr[`CSR_DCSR_ADDR][15]; + assign csr_dcsr_stepie = csr[`CSR_DCSR_ADDR][11]; + assign csr_dcsr_cause = csr[`CSR_DCSR_ADDR][8:6]; + assign csr_dcsr_step = csr[`CSR_DCSR_ADDR][2]; + assign csr_trig_execute = csr[`CSR_TDATA1_ADDR][2]; + assign csr_trig_pc = csr[`CSR_TDATA2_ADDR]; // can be expanded. Currently only define for current usage `ASSIGN_CSR_N_WB(`CSR_LPSTART0_ADDR, lpstart0) @@ -434,6 +439,7 @@ interface uvmt_cv32e40p_rvvi_if #( `ASSIGN_CSR_N_WB(`CSR_LPEND1_ADDR, lpend1) `ASSIGN_CSR_N_WB(`CSR_LPCOUNT1_ADDR, lpcount1) `ASSIGN_CSR_N_WB(`CSR_MIE_ADDR, mie) + `ASSIGN_CSR_N_WB(`CSR_MCAUSE_ADDR, mcause) `ASSIGN_CSR_N_WB(`CSR_MIP_ADDR, mip) `ASSIGN_CSR_N_WB(`CSR_DCSR_ADDR, dcsr) `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA1_ADDR, tdata, 1); From cf1bca18327fa9766b823430e9e69432bcc9fff2 Mon Sep 17 00:00:00 2001 From: bsm Date: Thu, 2 Nov 2023 15:11:51 +0800 Subject: [PATCH 15/17] Minor refinements Signed-off-by: bsm --- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 3 +-- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 5 ++--- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index 0b634d4d45..e52641cc31 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -517,7 +517,6 @@ module uvmt_cv32e40p_tb; .pc_rdata (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_pc_rdata), .interrupt_if (interrupt_if), .debug_if (debug_if), - .debug_rom (dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.dm_halt_addr_i), `PORTMAP_CSR_RVFI_2_RVVI(lpstart0) `PORTMAP_CSR_RVFI_2_RVVI(lpend0) `PORTMAP_CSR_RVFI_2_RVVI(lpcount0) @@ -529,7 +528,7 @@ module uvmt_cv32e40p_tb; `PORTMAP_CSR_RVFI_2_RVVI(mip) `PORTMAP_CSR_RVFI_2_RVVI(dcsr) `PORTMAP_CSR_RVFI_2_RVVI(tdata) - .dummy () + .dm_halt_addr (dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.dm_halt_addr_i) ); // IMPERAS DV diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index a197afde29..15fadf368a 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -389,11 +389,10 @@ interface uvmt_cv32e40p_rvvi_if #( input valid, input logic [(ILEN-1):0] insn, input trap, - input logic [(XLEN-1):0] pc_rdata, + input logic [31:0] pc_rdata, uvma_interrupt_if interrupt_if, uvma_debug_if debug_if, - input logic [31:0] debug_rom, // Currently only define specific csrs for current usage `DEF_CSR_PORTS(lpstart0) @@ -408,7 +407,7 @@ interface uvmt_cv32e40p_rvvi_if #( `DEF_CSR_PORTS(dcsr) `DEF_CSR_PORTS_VEC(tdata,4) - input dummy + input logic [31:0] dm_halt_addr ); From 220cca6533652cf586e7d50b5e9db0989cd9e227 Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 3 Nov 2023 08:50:07 +0800 Subject: [PATCH 16/17] Add parameter list of all cv32e40p supported instructions Signed-off-by: bsm --- .../env/uvme/uvme_cv32e40p_param_all_insn.sv | 624 ++++++++++++++++++ cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv | 2 +- 2 files changed, 625 insertions(+), 1 deletion(-) create mode 100644 cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv b/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv new file mode 100644 index 0000000000..6bbfc0ba4e --- /dev/null +++ b/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv @@ -0,0 +1,624 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVME_CV32E40P_PARAM_ALL_INSN__ +`define __UVME_CV32E40P_PARAM_ALL_INSN__ + +// note: +// 1) below instructions parameters are mirror copy of cv32e40p_pkg.sv and cv32e40p_tracer_pkg.sv +// 2) cv32e40p_pkg.sv is available at /cv32e40p/rtl/include +// 3) cv32e40p_tracer_pkg.sv is available at /cv32e40p/bhv/include + + //////////////////////////////////////////////// + // ___ ____ _ // + // / _ \ _ __ / ___|___ __| | ___ ___ // + // | | | | '_ \| | / _ \ / _` |/ _ \/ __| // + // | |_| | |_) | |__| (_) | (_| | __/\__ \ // + // \___/| .__/ \____\___/ \__,_|\___||___/ // + // |_| // + //////////////////////////////////////////////// + + parameter OPCODE_SYSTEM = 7'h73; + parameter OPCODE_FENCE = 7'h0f; + parameter OPCODE_OP = 7'h33; + parameter OPCODE_OPIMM = 7'h13; + parameter OPCODE_STORE = 7'h23; + parameter OPCODE_LOAD = 7'h03; + parameter OPCODE_BRANCH = 7'h63; + parameter OPCODE_JALR = 7'h67; + parameter OPCODE_JAL = 7'h6f; + parameter OPCODE_AUIPC = 7'h17; + parameter OPCODE_LUI = 7'h37; + parameter OPCODE_OP_FP = 7'h53; + parameter OPCODE_OP_FMADD = 7'h43; + parameter OPCODE_OP_FNMADD = 7'h4f; + parameter OPCODE_OP_FMSUB = 7'h47; + parameter OPCODE_OP_FNMSUB = 7'h4b; + parameter OPCODE_STORE_FP = 7'h27; + parameter OPCODE_LOAD_FP = 7'h07; + parameter OPCODE_AMO = 7'h2F; + // Those custom opcodes are used for PULP custom instructions + // parameter OPCODE_CUSTOM_0 = 7'h0b; + // parameter OPCODE_CUSTOM_1 = 7'h2b; + // parameter OPCODE_CUSTOM_2 = 7'h5b; + // parameter OPCODE_CUSTOM_3 = 7'h7b; + + // Atomic operations + parameter AMO_LR = 5'b00010; + parameter AMO_SC = 5'b00011; + parameter AMO_SWAP = 5'b00001; + parameter AMO_ADD = 5'b00000; + parameter AMO_XOR = 5'b00100; + parameter AMO_AND = 5'b01100; + parameter AMO_OR = 5'b01000; + parameter AMO_MIN = 5'b10000; + parameter AMO_MAX = 5'b10100; + parameter AMO_MINU = 5'b11000; + parameter AMO_MAXU = 5'b11100; + + // instruction masks (for tracer) + parameter INSTR_LUI = {25'b?, OPCODE_LUI}; + parameter INSTR_AUIPC = {25'b?, OPCODE_AUIPC}; + parameter INSTR_JAL = {25'b?, OPCODE_JAL}; + parameter INSTR_JALR = {17'b?, 3'b000, 5'b?, OPCODE_JALR}; + // BRANCH + parameter INSTR_BEQ = {17'b?, 3'b000, 5'b?, OPCODE_BRANCH}; + parameter INSTR_BNE = {17'b?, 3'b001, 5'b?, OPCODE_BRANCH}; + parameter INSTR_BLT = {17'b?, 3'b100, 5'b?, OPCODE_BRANCH}; + parameter INSTR_BGE = {17'b?, 3'b101, 5'b?, OPCODE_BRANCH}; + parameter INSTR_BLTU = {17'b?, 3'b110, 5'b?, OPCODE_BRANCH}; + parameter INSTR_BGEU = {17'b?, 3'b111, 5'b?, OPCODE_BRANCH}; + // OPIMM + parameter INSTR_ADDI = {17'b?, 3'b000, 5'b?, OPCODE_OPIMM}; + parameter INSTR_SLTI = {17'b?, 3'b010, 5'b?, OPCODE_OPIMM}; + parameter INSTR_SLTIU = {17'b?, 3'b011, 5'b?, OPCODE_OPIMM}; + parameter INSTR_XORI = {17'b?, 3'b100, 5'b?, OPCODE_OPIMM}; + parameter INSTR_ORI = {17'b?, 3'b110, 5'b?, OPCODE_OPIMM}; + parameter INSTR_ANDI = {17'b?, 3'b111, 5'b?, OPCODE_OPIMM}; + parameter INSTR_SLLI = {7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OPIMM}; + parameter INSTR_SRLI = {7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM}; + parameter INSTR_SRAI = {7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM}; + // OP + parameter INSTR_ADD = {7'b0000000, 10'b?, 3'b000, 5'b?, OPCODE_OP}; + parameter INSTR_SUB = {7'b0100000, 10'b?, 3'b000, 5'b?, OPCODE_OP}; + parameter INSTR_SLL = {7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OP}; + parameter INSTR_SLT = {7'b0000000, 10'b?, 3'b010, 5'b?, OPCODE_OP}; + parameter INSTR_SLTU = {7'b0000000, 10'b?, 3'b011, 5'b?, OPCODE_OP}; + parameter INSTR_XOR = {7'b0000000, 10'b?, 3'b100, 5'b?, OPCODE_OP}; + parameter INSTR_SRL = {7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OP}; + parameter INSTR_SRA = {7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OP}; + parameter INSTR_OR = {7'b0000000, 10'b?, 3'b110, 5'b?, OPCODE_OP}; + parameter INSTR_AND = {7'b0000000, 10'b?, 3'b111, 5'b?, OPCODE_OP}; + + parameter INSTR_PAVG = {7'b0000010, 10'b?, 3'b000, 5'b?, OPCODE_OP}; + parameter INSTR_PAVGU = {7'b0000010, 10'b?, 3'b001, 5'b?, OPCODE_OP}; + + // FENCE + parameter INSTR_FENCE = {4'b0, 8'b?, 13'b0, OPCODE_FENCE}; + parameter INSTR_FENCEI = {17'b0, 3'b001, 5'b0, OPCODE_FENCE}; + // SYSTEM + parameter INSTR_CSRRW = {17'b?, 3'b001, 5'b?, OPCODE_SYSTEM}; + parameter INSTR_CSRRS = {17'b?, 3'b010, 5'b?, OPCODE_SYSTEM}; + parameter INSTR_CSRRC = {17'b?, 3'b011, 5'b?, OPCODE_SYSTEM}; + parameter INSTR_CSRRWI = {17'b?, 3'b101, 5'b?, OPCODE_SYSTEM}; + parameter INSTR_CSRRSI = {17'b?, 3'b110, 5'b?, OPCODE_SYSTEM}; + parameter INSTR_CSRRCI = {17'b?, 3'b111, 5'b?, OPCODE_SYSTEM}; + parameter INSTR_ECALL = {12'b000000000000, 13'b0, OPCODE_SYSTEM}; + parameter INSTR_EBREAK = {12'b000000000001, 13'b0, OPCODE_SYSTEM}; + parameter INSTR_URET = {12'b000000000010, 13'b0, OPCODE_SYSTEM}; + parameter INSTR_SRET = {12'b000100000010, 13'b0, OPCODE_SYSTEM}; + parameter INSTR_MRET = {12'b001100000010, 13'b0, OPCODE_SYSTEM}; + parameter INSTR_DRET = {12'b011110110010, 13'b0, OPCODE_SYSTEM}; + parameter INSTR_WFI = {12'b000100000101, 13'b0, OPCODE_SYSTEM}; + + // RV32M + parameter INSTR_DIV = {7'b0000001, 10'b?, 3'b100, 5'b?, OPCODE_OP}; + parameter INSTR_DIVU = {7'b0000001, 10'b?, 3'b101, 5'b?, OPCODE_OP}; + parameter INSTR_REM = {7'b0000001, 10'b?, 3'b110, 5'b?, OPCODE_OP}; + parameter INSTR_REMU = {7'b0000001, 10'b?, 3'b111, 5'b?, OPCODE_OP}; + parameter INSTR_PMUL = {7'b0000001, 10'b?, 3'b000, 5'b?, OPCODE_OP}; + parameter INSTR_PMUH = {7'b0000001, 10'b?, 3'b001, 5'b?, OPCODE_OP}; + parameter INSTR_PMULHSU = {7'b0000001, 10'b?, 3'b010, 5'b?, OPCODE_OP}; + parameter INSTR_PMULHU = {7'b0000001, 10'b?, 3'b011, 5'b?, OPCODE_OP}; + + // RV32F + parameter INSTR_FMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMADD}; + parameter INSTR_FMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMSUB}; + parameter INSTR_FNMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMSUB}; + parameter INSTR_FNMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMADD}; + + parameter INSTR_FADD = {5'b00000, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FSUB = {5'b00001, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FMUL = {5'b00010, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FDIV = {5'b00011, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FSQRT = {5'b01011, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FSGNJS = {5'b00100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FSGNJNS = {5'b00100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FSGNJXS = {5'b00100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FMIN = {5'b00101, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FMAX = {5'b00101, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FCVTWS = {5'b11000, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FCVTWUS = {5'b11000, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FMVXS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FEQS = {5'b10100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FLTS = {5'b10100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FLES = {5'b10100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FCLASS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b001, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FCVTSW = {5'b11010, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FCVTSWU = {5'b11010, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; + parameter INSTR_FMVSX = {5'b11110, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP}; + + // RV32A + parameter INSTR_LR = {AMO_LR, 2'b?, 5'b0, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_SC = {AMO_SC, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOSWAP = {AMO_SWAP, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOADD = {AMO_ADD, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOXOR = {AMO_XOR, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOAND = {AMO_AND, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOOR = {AMO_OR, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOMIN = {AMO_MIN, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOMAX = {AMO_MAX, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOMINU = {AMO_MINU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + parameter INSTR_AMOMAXU = {AMO_MAXU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; + + + // LOAD STORE + parameter INSTR_LB = {17'b?, 3'b000, 5'b?, OPCODE_LOAD}; + parameter INSTR_LH = {17'b?, 3'b001, 5'b?, OPCODE_LOAD}; + parameter INSTR_LW = {17'b?, 3'b010, 5'b?, OPCODE_LOAD}; + parameter INSTR_LBU = {17'b?, 3'b100, 5'b?, OPCODE_LOAD}; + parameter INSTR_LHU = {17'b?, 3'b101, 5'b?, OPCODE_LOAD}; + + parameter INSTR_SB = {17'b?, 3'b000, 5'b?, OPCODE_STORE}; + parameter INSTR_SH = {17'b?, 3'b001, 5'b?, OPCODE_STORE}; + parameter INSTR_SW = {17'b?, 3'b010, 5'b?, OPCODE_STORE}; + + // parameter INSTR_FL = {OPCODE_LOAD_FP}; + // parameter INSTR_FS = {OPCODE_STORE_FP} + + // CUSTOM_0 + parameter INSTR_BEQIMM = {17'b?, 3'b110, 5'b?, OPCODE_CUSTOM_0}; + parameter INSTR_BNEIMM = {17'b?, 3'b111, 5'b?, OPCODE_CUSTOM_0}; + + // Post-Increment Register-Immediate Load + parameter INSTR_CVLBI = {17'b?, 3'b000, 5'b?, OPCODE_CUSTOM_0}; + parameter INSTR_CVLBUI = {17'b?, 3'b100, 5'b?, OPCODE_CUSTOM_0}; + parameter INSTR_CVLHI = {17'b?, 3'b001, 5'b?, OPCODE_CUSTOM_0}; + parameter INSTR_CVLHUI = {17'b?, 3'b101, 5'b?, OPCODE_CUSTOM_0}; + parameter INSTR_CVLWI = {17'b?, 3'b010, 5'b?, OPCODE_CUSTOM_0}; + + // Event Load + parameter INSTR_CVELW = {17'b?, 3'b011, 5'b?, OPCODE_CUSTOM_0}; + + // CUSTOM_1 + // Post-Increment Register-Register Load + parameter INSTR_CVLBR = {7'b0000000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLBUR = {7'b0001000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLHR = {7'b0000001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLHUR = {7'b0001001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLWR = {7'b0000010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + // Register-Register Load + parameter INSTR_CVLBRR = {7'b0000100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLBURR = {7'b0001100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLHRR = {7'b0000101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLHURR = {7'b0001101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVLWRR = {7'b0000110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + // Post-Increment Register-Immediate Store + parameter INSTR_CVSBI = {17'b?, 3'b000, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVSHI = {17'b?, 3'b001, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVSWI = {17'b?, 3'b010, 5'b?, OPCODE_CUSTOM_1}; + + // Post-Increment Register-Register Store operations encoding + parameter INSTR_CVSBR = {7'b0010000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVSHR = {7'b0010001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVSWR = {7'b0010010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + // Register-Register Store operations + parameter INSTR_CVSBRR = {7'b0010100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVSHRR = {7'b0010101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CVSWRR = {7'b0010110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + // Hardware Loops + parameter INSTR_CVSTARTI0 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b0, OPCODE_CUSTOM_1}; + parameter INSTR_CVSTART0 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b0, OPCODE_CUSTOM_1}; + parameter INSTR_CVSENDI0 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b0, OPCODE_CUSTOM_1}; + parameter INSTR_CVEND0 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1}; + parameter INSTR_CVCOUNTI0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1}; + parameter INSTR_CVCOUNT0 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1}; + parameter INSTR_CVSETUPI0 = {17'b?, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1}; + parameter INSTR_CVSETUP0 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1}; + + parameter INSTR_CVSTARTI1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1}; + parameter INSTR_CVSTART1 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1}; + parameter INSTR_CVSENDI1 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b1, OPCODE_CUSTOM_1}; + parameter INSTR_CVEND1 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1}; + parameter INSTR_CVCOUNTI1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1}; + parameter INSTR_CVCOUNT1 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1}; + parameter INSTR_CVSETUPI1 = {17'b?, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1}; + parameter INSTR_CVSETUP1 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1}; + + + parameter INSTR_FF1 = {7'b0100001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_FL1 = {7'b0100010, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CLB = {7'b0100011, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_CNT = {7'b0100100, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + parameter INSTR_EXTHS = {7'b0110000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_EXTHZ = {7'b0110001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_EXTBS = {7'b0110010, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_EXTBZ = {7'b0110011, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + parameter INSTR_PADDNR = {7'b1000000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PADDUNR = {7'b1000001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PADDRNR = {7'b1000010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PADDURNR = {7'b1000011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PSUBNR = {7'b1000100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PSUBUNR = {7'b1000101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PSUBRNR = {7'b1000110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PSUBURNR = {7'b1000111, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + parameter INSTR_PABS = {7'b0101000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PCLIP = {7'b0111000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PCLIPU = {7'b0111001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PCLIPR = {7'b0111010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PCLIPUR = {7'b0111011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + parameter INSTR_PSLET = {7'b0101001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PSLETU = {7'b0101010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PMIN = {7'b0101011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PMINU = {7'b0101100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PMAX = {7'b0101101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PMAXU = {7'b0101110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_ROR = {7'b0100000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + parameter INSTR_PBEXTR = {7'b0011000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PBEXTUR = {7'b0011001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PBINSR = {7'b0011010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PBCLRR = {7'b0011100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PBSETR = {7'b0011101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + parameter INSTR_PMAC = {7'b1001000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + parameter INSTR_PMSU = {7'b1001001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; + + // CUSTOM_2 + parameter INSTR_PBEXT = {2'b00, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PBEXTU = {2'b01, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PBINS = {2'b10, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PBCLR = {2'b00, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PBSET = {2'b01, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PBREV = {2'b11, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; + + parameter INSTR_PADDN = {2'b00, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PADDUN = {2'b01, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PADDRN = {2'b10, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PADDURN = {2'b11, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PSUBN = {2'b00, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PSUBUN = {2'b01, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PSUBRN = {2'b10, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PSUBURN = {2'b11, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; + + parameter INSTR_PMULSN = {2'b00, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMULHHSN = {2'b01, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMULSRN = {2'b10, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMULHHSRN = {2'b11, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMULUN = {2'b00, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMULHHUN = {2'b01, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMULURN = {2'b10, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMULHHURN = {2'b11, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACSN = {2'b00, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACHHSN = {2'b01, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACSRN = {2'b10, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACHHSRN = {2'b11, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACUN = {2'b00, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACHHUN = {2'b01, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACURN = {2'b10, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; + parameter INSTR_PMACHHURN = {2'b11, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; + + + // CUSTOM_3 + // SIMD ALU + parameter INSTR_CVADDH = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVADDSCH = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVADDSCIH = {5'b00000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVADDB = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVADDSCB = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVADDSCIB = {5'b00000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSUBH = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBSCH = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBSCIH = {5'b00001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBB = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBSCB = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBSCIB = {5'b00001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVAVGH = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGSCH = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGSCIH = {5'b00010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGB = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGSCB = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGSCIB = {5'b00010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVAVGUH = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGUSCH = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGUSCIH = {5'b00011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGUB = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGUSCB = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVAVGUSCIB = {5'b00011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVMINH = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINSCH = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINSCIH = {5'b00100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINB = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINSCB = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINSCIB = {5'b00100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVMINUH = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINUSCH = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINUSCIH = {5'b00101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINUB = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINUSCB = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMINUSCIB = {5'b00101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVMAXH = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXSCH = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXSCIH = {5'b00110, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXB = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXSCB = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXSCIB = {5'b00110, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVMAXUH = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXUSCH = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXUSCIH = {5'b00111, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXUB = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXUSCB = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVMAXUSCIB = {5'b00111, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSRLH = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRLSCH = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRLSCIH = {5'b01000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRLB = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRLSCB = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRLSCIB = {5'b01000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSRAH = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRASCH = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRASCIH = {5'b01001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRAB = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRASCB = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSRASCIB = {5'b01001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSLLH = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSLLSCH = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSLLSCIH = {5'b01010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSLLB = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSLLSCB = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSLLSCIB = {5'b01010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVORH = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVORSCH = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVORSCIH = {5'b01011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVORB = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVORSCB = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVORSCIB = {5'b01011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVXORH = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVXORSCH = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVXORSCIH = {5'b01100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVXORB = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVXORSCB = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVXORSCIB = {5'b01100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVANDH = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVANDSCH = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVANDSCIH = {5'b01101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVANDB = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVANDSCB = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVANDSCIB = {5'b01101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVABSH = {5'b01110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVABSB = {5'b01110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVEXTRACTH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVEXTRACTB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVEXTRACTUH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVEXTRACTUB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVINSERTH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVINSERTB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVDOTUPH = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUPSCH = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUPSCIH = {5'b10000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUPB = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUPSCB = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUPSCIB = {5'b10000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVDOTUSPH = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUSPSCH = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUSPSCIH = {5'b10001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUSPB = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUSPSCB = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTUSPSCIB = {5'b10001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVDOTSPH = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTSPSCH = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTSPSCIH = {5'b10010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTSPB = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTSPSCB = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVDOTSPSCIB = {5'b10010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSDOTUPH = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUPSCH = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUPSCIH = {5'b10011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUPB = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUPSCB = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUPSCIB = {5'b10011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSDOTUSPH = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUSPSCH = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUSPSCIH = {5'b10100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUSPB = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUSPSCB = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTUSPSCIB = {5'b10100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSDOTSPH = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTSPSCH = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTSPSCIH = {5'b10101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTSPB = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTSPSCB = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSDOTSPSCIB = {5'b10101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSHUFFLEH = {5'b11000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSHUFFLESCIH = {5'b11000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSHUFFLEB = {5'b11000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSHUFFLEL0SCIB = {5'b11000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSHUFFLEL1SCIB = {5'b11001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSHUFFLEL2SCIB = {5'b11010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSHUFFLEL3SCIB = {5'b11011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSHUFFLE2H = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSHUFFLE2B = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVPACK = {5'b11110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVPACKH = {5'b11110, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVPACKHIB = {5'b11111, 1'b0, 1'b1, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVPACKLOB = {5'b11111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + + // SIMD COMPARISON + parameter INSTR_CVCMPEQH = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPEQSCH = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPEQSCIH = {5'b00000, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPEQB = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPEQSCB = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPEQSCIB = {5'b00000, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPNEH = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPNESCH = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPNESCIH = {5'b00001, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPNEB = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPNESCB = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPNESCIB = {5'b00001, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPGTH = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTSCH = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTSCIH = {5'b00010, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTB = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTSCB = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTSCIB = {5'b00010, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPGEH = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGESCH = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGESCIH = {5'b00011, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGEB = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGESCB = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGESCIB = {5'b00011, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPLTH = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTSCH = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTSCIH = {5'b00100, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTB = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTSCB = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTSCIB = {5'b00100, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPLEH = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLESCH = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLESCIH = {5'b00101, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLEB = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLESCB = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLESCIB = {5'b00101, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPGTUH = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTUSCH = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTUSCIH = {5'b00110, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTUB = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTUSCB = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGTUSCIB = {5'b00110, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPGEUH = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGEUSCH = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGEUSCIH = {5'b00111, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGEUB = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGEUSCB = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPGEUSCIB = {5'b00111, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPLTUH = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTUSCH = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTUSCIH = {5'b01000, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTUB = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTUSCB = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLTUSCIB = {5'b01000, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVCMPLEUH = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLEUSCH = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLEUSCIH = {5'b01001, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLEUB = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLEUSCB = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCMPLEUSCIB = {5'b01001, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; + + // SIMD CPLX + parameter INSTR_CVCPLXMULR = {5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCPLXMULRDIV2 = { + 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 + }; + parameter INSTR_CVCPLXMULRDIV4 = { + 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 + }; + parameter INSTR_CVCPLXMULRDIV8 = { + 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 + }; + + parameter INSTR_CVCPLXMULI = {5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVCPLXMULIDIV2 = { + 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 + }; + parameter INSTR_CVCPLXMULIDIV4 = { + 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 + }; + parameter INSTR_CVCPLXMULIDIV8 = { + 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 + }; + + parameter INSTR_CVCPLXCONJ = { + 5'b01011, 1'b1, 1'b0, 5'b00000, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3 + }; + + parameter INSTR_CVSUBROTMJ = {5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBROTMJDIV2 = { + 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 + }; + parameter INSTR_CVSUBROTMJDIV4 = { + 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 + }; + parameter INSTR_CVSUBROTMJDIV8 = { + 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 + }; + + parameter INSTR_CVADDIV2 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVADDIV4 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVADDIV8 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + + parameter INSTR_CVSUBIV2 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBIV4 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; + parameter INSTR_CVSUBIV8 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; + + // Load-Store (RV32F) + parameter INSTR_FLW = {17'b?, 3'b010, 5'b?, OPCODE_LOAD_FP}; + parameter INSTR_FSW = {17'b?, 3'b010, 5'b?, OPCODE_STORE_FP}; + +`endif diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv index 8838267167..6bea3b51c8 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv @@ -27,7 +27,6 @@ `include "uvma_clknrst_macros.sv" `include "uvme_cv32e40p_macros.sv" - /** * Encapsulates all the types needed for an UVM environment capable of driving/ * monitoring and verifying the behavior of an CV32E40P design. @@ -51,6 +50,7 @@ package uvme_cv32e40p_pkg; // Constants / Structs / Enums `include "uvme_cv32e40p_constants.sv" + `include "uvme_cv32e40p_param_all_insn.sv" `include "uvme_cv32e40p_tdefs.sv" // Objects From 83fd0e67e193cf3e5f6ae1407e0c27367c8d19af Mon Sep 17 00:00:00 2001 From: bsm Date: Mon, 6 Nov 2023 16:09:14 +0800 Subject: [PATCH 17/17] Add RV32X hwloop covergroups with updates based on review Signed-off-by: bsm --- .../env/uvme/cov/uvme_cv32e40p_cov_model.sv | 9 +- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 920 ++++++++++++++++++ cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv | 1 + cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv | 14 + cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 16 +- 5 files changed, 956 insertions(+), 4 deletions(-) create mode 100644 cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv index cec3311d58..519f0f6a12 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv @@ -29,9 +29,10 @@ class uvme_cv32e40p_cov_model_c extends uvm_component; uvme_cv32e40p_cfg_c cfg; uvme_cv32e40p_cntxt_c cntxt; - uvme_rv32isa_covg isa_covg; - uvme_interrupt_covg interrupt_covg; - uvme_debug_covg debug_covg; + uvme_rv32isa_covg isa_covg; + uvme_interrupt_covg interrupt_covg; + uvme_debug_covg debug_covg; + uvme_rv32x_hwloop_covg rv32x_hwloop_covg; `uvm_component_utils_begin(uvme_cv32e40p_cov_model_c) `uvm_field_object(cfg , UVM_DEFAULT) @@ -110,6 +111,8 @@ function void uvme_cv32e40p_cov_model_c::build_phase(uvm_phase phase); debug_covg = uvme_debug_covg::type_id::create("debug_covg", this); uvm_config_db#(uvme_cv32e40p_cntxt_c)::set(this, "debug_covg", "cntxt", cntxt); + rv32x_hwloop_covg = uvme_rv32x_hwloop_covg::type_id::create("rv32x_hwloop_covg", this); + endfunction : build_phase function void uvme_cv32e40p_cov_model_c::connect_phase(uvm_phase phase); diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv new file mode 100644 index 0000000000..e1f2742d26 --- /dev/null +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -0,0 +1,920 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 OpenHW Group +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 +//******************************************************************************************************************************************* + +// Note: +// 1) This coverage model complements Imperas coverage XPULPV2 with addtional coverage collection related to hwloops +// 2) It uses uvmt_cv32e40p_rvvi_if +// 3) Has covergroup for hwloops csr setup registers +// 4) Has covergroup for hwloops features and events within hwloops such as exception, irq and debug entry (debug covers haltreq, trigger, ebreakm, step) + +`ifndef UVME_RV32X_HWLOOP_COVG +`define UVME_RV32X_HWLOOP_COVG + +class uvme_rv32x_hwloop_covg # ( + parameter int ILEN = 32, + parameter int XLEN = 32 +) extends uvm_component; + + localparam SKIP_RVVI_INIT_VALID_CNT = 1; + localparam HWLOOP_NB = 2; + localparam CSR_LPSTART0_ADDR = 32'hCC0; + localparam CSR_LPEND0_ADDR = 32'hCC1; + localparam CSR_LPCOUNT0_ADDR = 32'hCC2; + localparam INSN_CEBREAK = 32'h00009002; // compress ebreak + localparam INSN_ILLEGAL = 32'hFFFFFFFF; // user-defined for any illegal insn that leads to illegal exception + localparam INSN_EBREAKM = 32'hFFFFFFFE; // user-defined + + typedef enum bit [1:0] {NULL_TYPE=0, SINGLE, NESTED} hwloop_type_t; + typedef enum bit [1:0] {NULL_SETUP=0, SHORT, LONG} hwloop_setup_t; + typedef struct { + bit [31:0] lp_start [HWLOOP_NB]; + bit [31:0] lp_end [HWLOOP_NB]; + bit [31:0] lp_count [HWLOOP_NB]; + bit lp_start_wb [HWLOOP_NB]; + bit lp_end_wb [HWLOOP_NB]; + bit lp_count_wb [HWLOOP_NB]; + } s_csr_hwloop; + typedef struct { + hwloop_type_t hwloop_type; + hwloop_setup_t hwloop_setup [HWLOOP_NB]; + s_csr_hwloop hwloop_csr; + bit execute_instr_in_hwloop [HWLOOP_NB]; + int track_lp_count [HWLOOP_NB]; + } s_hwloop_stat; + + // PROPERTIES - START + local s_csr_hwloop csr_hwloop_init = '{default:0}; + local s_hwloop_stat hwloop_stat_init = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; + + `define DEF_LOCAL_VARS(TYPE) \ + local s_csr_hwloop csr_hwloop_``TYPE = '{default:0}; \ + local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ + local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ + local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ + local bit debug_req_``TYPE [HWLOOP_NB] = '{default:0}; \ + local bit dbg_trigger_``TYPE [HWLOOP_NB] = '{default:0}; \ + local int unsigned dbg_step_cnt_``TYPE [HWLOOP_NB] = '{default:0}; \ + local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; + + `DEF_LOCAL_VARS(main) + `DEF_LOCAL_VARS(sub) + + virtual uvmt_cv32e40p_rvvi_if #( .XLEN(XLEN), .ILEN(ILEN)) cv32e40p_rvvi_vif; + string _header = "XPULPV2_HWLOOP_COV"; + bit en_cvg_sampling = 1; + bit in_nested_loop0 = 0; + bit is_ebreak = 0, is_ebreakm, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0; + bit enter_hwloop_sub = 0; + + dcsr_cause_t dcsr_cause; + exception_code_t exception_code; + + // PROPERTIES - END + + // COVERGROUPS DEFINE HERE - START + + `define CG_CSR_HWLOOP(LOOP_IDX) cg_csr_hwloop_``LOOP_IDX`` + `define DEF_CG_CSR_HWLOOP(LOOP_IDX) covergroup cg_csr_hwloop_``LOOP_IDX with function sample(s_csr_hwloop csr_hwloop); \ + option.per_instance = 1; \ + `ifdef MODEL_TECH \ + option.get_inst_coverage = 1; \ + `endif \ + type_option.merge_instances = 1; \ + cp_lpstart_``LOOP_IDX : coverpoint (csr_hwloop.lp_start[``LOOP_IDX``]) iff (csr_hwloop.lp_start_wb[``LOOP_IDX``] && csr_hwloop.lp_end_wb[``LOOP_IDX``] && csr_hwloop.lp_count_wb[``LOOP_IDX``]) { \ + bins lpstart_range_0 = {[32'h0000_03FC : 32'h0000_0004]}; \ + bins lpstart_range_1 = {[32'h0000_0FFC : 32'h0000_0400]}; \ + bins lpstart_range_2 = {[32'h0000_FFFC : 32'h0000_1000]}; \ + // higher range is not covered now due to limited generated codespace (amend if needed) \ + } \ + cp_lpend_``LOOP_IDX : coverpoint (csr_hwloop.lp_end[``LOOP_IDX``]) iff (csr_hwloop.lp_start_wb[``LOOP_IDX``] && csr_hwloop.lp_end_wb[``LOOP_IDX``] && csr_hwloop.lp_count_wb[``LOOP_IDX``]) { \ + bins lpend_range_0 = {[32'h0000_03FC : 32'h0000_0004]}; \ + bins lpend_range_1 = {[32'h0000_0FFC : 32'h0000_0400]}; \ + bins lpend_range_2 = {[32'h0000_FFFC : 32'h0000_1000]}; \ + // higher range is not covered now due to limited generated codespace (amend if needed) \ + } \ + cp_lpcount_``LOOP_IDX : coverpoint (csr_hwloop.lp_count[``LOOP_IDX``]) iff (csr_hwloop.lp_start_wb[``LOOP_IDX``] && csr_hwloop.lp_end_wb[``LOOP_IDX``] && csr_hwloop.lp_count_wb[``LOOP_IDX``]) { \ + // bins lpcount_zero = {32'h0}; // valid CSR writes to sample should be when lpcount{0/1}.value != 0 \ + bins lpcount_range_low_1 = {[32'h0000_00FF : 32'h0000_0001]}; // 1 <= x <255 \ + bins lpcount_range_low_2 = {[32'h0000_1FFF : 32'h0000_0100]}; // 256 <= x < 4K \ + // bins lpcount_range_middle = {[32'h00FF_FFFF : 32'h0000_1000]}; // 4K <= x < 16M \ + // bins lpcount_range_high = {[32'hFFFF_FFFF : 32'h0100_0000]}; // 16M <= x < 4G \ + // higher counts are not covered now to reduced simtime (amend if needed) \ + } \ + ccp_lpstart_0_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ + ignore_bins ignore__lpstart_range_1 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_0FFC : 32'h0000_0400]}; \ + ignore_bins ignore__lpstart_range_2 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_FFFC : 32'h0000_1000]}; \ + } \ + ccp_lpstart_1_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ + ignore_bins ignore__lpstart_range_0 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ + ignore_bins ignore__lpstart_range_2 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_FFFC : 32'h0000_1000]}; \ + ignore_bins ignore__lpend_range_0 = binsof (cp_lpend_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ + } \ + ccp_lpstart_2_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ + ignore_bins ignore__lpstart_range_0 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ + ignore_bins ignore__lpstart_range_1 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_0FFC : 32'h0000_0400]}; \ + ignore_bins ignore__lpend_range_0 = binsof (cp_lpend_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ + ignore_bins ignore__lpend_range_1 = binsof (cp_lpend_``LOOP_IDX``) intersect {[32'h0000_0FFC : 32'h0000_0400]}; \ + } \ + endgroup : cg_csr_hwloop_``LOOP_IDX + + `define CG_FEATURES_OF_HWLOOP(LOOP_IDX) cg_features_of_hwloop_``LOOP_IDX`` + `define DEF_CG_FEATURES_OF_HWLOOP(LOOP_IDX) covergroup cg_features_of_hwloop_``LOOP_IDX with function \ + sample(s_hwloop_stat hwloop_stat, bit [31:0] insn, bit [31:0] irq, bit dbg_haltreq, bit dbg_trigger, int unsigned dbg_step_cnt); \ + option.per_instance = 1; \ + `ifdef MODEL_TECH \ + option.get_inst_coverage = 1; \ + `endif \ + type_option.merge_instances = 1; \ + cp_hwloop_type : coverpoint (hwloop_stat.hwloop_type) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + bins single_hwloop = {SINGLE}; \ + bins nested_hwloop = {NESTED}; \ + illegal_bins invalid = default; \ + } \ + cp_hwloop_setup : coverpoint (hwloop_stat.hwloop_setup[``LOOP_IDX``]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + bins short_hwloop_setup = {SHORT}; \ + bins long_hwloop_setup = {LONG}; \ + illegal_bins invalid = default; \ + } \ + cp_hwloop_irq : coverpoint (irq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + // priority order (high->low) : irq[31]...irq[16], irq[11], irq[3], irq[7] \ + bins vec_irq_1hot_priority[] = {32'h0000_0008, \ + 32'h0000_0080, \ + 32'h0000_0800, \ + 32'h0001_0000, 32'h0002_0000, 32'h0004_0000, 32'h0008_0000, \ + 32'h0010_0000, 32'h0020_0000, 32'h0040_0000, 32'h0080_0000, \ + 32'h0100_0000, 32'h0200_0000, 32'h0400_0000, 32'h0800_0000, \ + 32'h1000_0000, 32'h2000_0000, 32'h4000_0000, 32'h8000_0000}; \ + } \ + cp_hwloop_dbg_haltreq : coverpoint (dbg_haltreq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + bins dbg_haltreq = {1}; \ + } \ + cp_hwloop_dbg_trigger : coverpoint (dbg_trigger) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + bins dbg_trigger = {1}; \ + } \ + cp_hwloop_dbg_step_cnt : coverpoint (dbg_step_cnt) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + bins dbg_step_range_1 = {[1:4]}; \ + bins dbg_step_range_2 = {[5:20]}; \ + bins dbg_step_range_3 = {[20:50]}; \ + bins dbg_step_range_4 = {[51:$]}; \ + } \ + // note: hwloop setup custom instructions are not allow in hwloop_0 (manual exclusion needed) \ + cp_insn_list_in_hwloop : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + wildcard bins instr_lui = {INSTR_LUI}; \ + wildcard bins instr_auipc = {INSTR_AUIPC}; \ + // OPIMM \ + wildcard bins instr_addi = {INSTR_ADDI}; \ + wildcard bins instr_slti = {INSTR_SLTI}; \ + wildcard bins instr_sltiu = {INSTR_SLTIU}; \ + wildcard bins instr_xori = {INSTR_XORI}; \ + wildcard bins instr_ori = {INSTR_ORI}; \ + wildcard bins instr_andi = {INSTR_ANDI}; \ + wildcard bins instr_slli = {INSTR_SLLI}; \ + wildcard bins instr_srli = {INSTR_SRLI}; \ + wildcard bins instr_srai = {INSTR_SRAI}; \ + // OP \ + wildcard bins instr_add = {INSTR_ADD}; \ + wildcard bins instr_sub = {INSTR_SUB}; \ + wildcard bins instr_sll = {INSTR_SLL}; \ + wildcard bins instr_slt = {INSTR_SLT}; \ + wildcard bins instr_sltu = {INSTR_SLTU}; \ + wildcard bins instr_xor = {INSTR_XOR}; \ + wildcard bins instr_srl = {INSTR_SRL}; \ + wildcard bins instr_sra = {INSTR_SRA}; \ + wildcard bins instr_or = {INSTR_OR}; \ + wildcard bins instr_and = {INSTR_AND}; \ + wildcard bins instr_pavg = {INSTR_PAVG}; \ + wildcard bins instr_pavgu = {INSTR_PAVGU}; \ + // SYSTEM \ + wildcard bins instr_csrrw = {INSTR_CSRRW}; \ + wildcard bins instr_csrrs = {INSTR_CSRRS}; \ + wildcard bins instr_csrrc = {INSTR_CSRRC}; \ + wildcard bins instr_csrrwi = {INSTR_CSRRWI}; \ + wildcard bins instr_csrrsi = {INSTR_CSRRSI}; \ + wildcard bins instr_csrrci = {INSTR_CSRRCI}; \ + wildcard bins instr_ecall = {INSTR_ECALL}; \ + wildcard bins instr_ebreak = {INSTR_EBREAK}; \ + // RV32M \ + wildcard bins instr_div = {INSTR_DIV}; \ + wildcard bins instr_divu = {INSTR_DIVU}; \ + wildcard bins instr_rem = {INSTR_REM}; \ + wildcard bins instr_remu = {INSTR_REMU}; \ + wildcard bins instr_pmul = {INSTR_PMUL}; \ + wildcard bins instr_pmuh = {INSTR_PMUH}; \ + wildcard bins instr_pmulhsu = {INSTR_PMULHSU}; \ + wildcard bins instr_pmulhu = {INSTR_PMULHU}; \ + // RV32F \ + wildcard bins instr_fmadd = {INSTR_FMADD}; \ + wildcard bins instr_fmsub = {INSTR_FMSUB}; \ + wildcard bins instr_fnmsub = {INSTR_FNMSUB}; \ + wildcard bins instr_fnmadd = {INSTR_FNMADD}; \ + wildcard bins instr_fadd = {INSTR_FADD}; \ + wildcard bins instr_fsub = {INSTR_FSUB}; \ + wildcard bins instr_fmul = {INSTR_FMUL}; \ + wildcard bins instr_fdiv = {INSTR_FDIV}; \ + wildcard bins instr_fsqrt = {INSTR_FSQRT}; \ + wildcard bins instr_fsgnjs = {INSTR_FSGNJS}; \ + wildcard bins instr_fsgnjns = {INSTR_FSGNJNS}; \ + wildcard bins instr_fsgnjxs = {INSTR_FSGNJXS}; \ + wildcard bins instr_fmin = {INSTR_FMIN}; \ + wildcard bins instr_fmax = {INSTR_FMAX}; \ + wildcard bins instr_fcvtws = {INSTR_FCVTWS}; \ + wildcard bins instr_fcvtwus = {INSTR_FCVTWUS}; \ + wildcard bins instr_fmvxs = {INSTR_FMVXS}; \ + wildcard bins instr_feqs = {INSTR_FEQS}; \ + wildcard bins instr_flts = {INSTR_FLTS}; \ + wildcard bins instr_fles = {INSTR_FLES}; \ + wildcard bins instr_fclass = {INSTR_FCLASS}; \ + wildcard bins instr_fcvtsw = {INSTR_FCVTSW}; \ + wildcard bins instr_fcvtswu = {INSTR_FCVTSWU}; \ + wildcard bins instr_fmvsx = {INSTR_FMVSX}; \ + // LOAD STORE \ + wildcard bins instr_lb = {INSTR_LB}; \ + wildcard bins instr_lh = {INSTR_LH}; \ + wildcard bins instr_lw = {INSTR_LW}; \ + wildcard bins instr_lbu = {INSTR_LBU}; \ + wildcard bins instr_lhu = {INSTR_LHU}; \ + wildcard bins instr_sb = {INSTR_SB}; \ + wildcard bins instr_sh = {INSTR_SH}; \ + wildcard bins instr_sw = {INSTR_SW}; \ + // CUSTOM_0 \ + // Post-Increment Register-Immediate Load \ + wildcard bins instr_cvlbi = {INSTR_CVLBI}; \ + wildcard bins instr_cvlbui = {INSTR_CVLBUI}; \ + wildcard bins instr_cvlhi = {INSTR_CVLHI}; \ + wildcard bins instr_cvlhui = {INSTR_CVLHUI}; \ + wildcard bins instr_cvlwi = {INSTR_CVLWI}; \ + // Event Load \ + wildcard bins instr_cvelw = {INSTR_CVELW}; \ + // CUSTOM_1 \ + // Post-Increment Register-Register Load \ + wildcard bins instr_cvlbr = {INSTR_CVLBR}; \ + wildcard bins instr_cvlbur = {INSTR_CVLBUR}; \ + wildcard bins instr_cvlhr = {INSTR_CVLHR}; \ + wildcard bins instr_cvlhur = {INSTR_CVLHUR}; \ + wildcard bins instr_cvlwr = {INSTR_CVLWR}; \ + // Register-Register Load \ + wildcard bins instr_cvlbrr = {INSTR_CVLBRR}; \ + wildcard bins instr_cvlburr = {INSTR_CVLBURR}; \ + wildcard bins instr_cvlhrr = {INSTR_CVLHRR}; \ + wildcard bins instr_cvlhurr = {INSTR_CVLHURR}; \ + wildcard bins instr_cvlwrr = {INSTR_CVLWRR}; \ + // Post-Increment Register-Immediate Store \ + wildcard bins instr_cvsbi = {INSTR_CVSBI}; \ + wildcard bins instr_cvshi = {INSTR_CVSHI}; \ + wildcard bins instr_cvswi = {INSTR_CVSWI}; \ + // Post-Increment Register-Register Store operations encoding \ + wildcard bins instr_cvsbr = {INSTR_CVSBR}; \ + wildcard bins instr_cvshr = {INSTR_CVSHR}; \ + wildcard bins instr_cvswr = {INSTR_CVSWR}; \ + // Register-Register Store operations \ + wildcard bins instr_cvsbrr = {INSTR_CVSBRR}; \ + wildcard bins instr_cvshrr = {INSTR_CVSHRR}; \ + wildcard bins instr_cvswrr = {INSTR_CVSWRR}; \ + // Hardware Loops \ + wildcard bins instr_cvstarti0 = {INSTR_CVSTARTI0}; \ + wildcard bins instr_cvstart0 = {INSTR_CVSTART0}; \ + wildcard bins instr_cvsendi0 = {INSTR_CVSENDI0}; \ + wildcard bins instr_cvend0 = {INSTR_CVEND0}; \ + wildcard bins instr_cvcounti0 = {INSTR_CVCOUNTI0}; \ + wildcard bins instr_cvcount0 = {INSTR_CVCOUNT0}; \ + wildcard bins instr_cvsetupi0 = {INSTR_CVSETUPI0}; \ + wildcard bins instr_cvsetup0 = {INSTR_CVSETUP0}; \ + wildcard bins instr_cvstarti1 = {INSTR_CVSTARTI1}; \ + wildcard bins instr_cvstart1 = {INSTR_CVSTART1}; \ + wildcard bins instr_cvsendi1 = {INSTR_CVSENDI1}; \ + wildcard bins instr_cvend1 = {INSTR_CVEND1}; \ + wildcard bins instr_cvcounti1 = {INSTR_CVCOUNTI1}; \ + wildcard bins instr_cvcount1 = {INSTR_CVCOUNT1}; \ + wildcard bins instr_cvsetupi1 = {INSTR_CVSETUPI1}; \ + wildcard bins instr_cvsetup1 = {INSTR_CVSETUP1}; \ + wildcard bins instr_ff1 = {INSTR_FF1}; \ + wildcard bins instr_fl1 = {INSTR_FL1}; \ + wildcard bins instr_clb = {INSTR_CLB}; \ + wildcard bins instr_cnt = {INSTR_CNT}; \ + wildcard bins instr_exths = {INSTR_EXTHS}; \ + wildcard bins instr_exthz = {INSTR_EXTHZ}; \ + wildcard bins instr_extbs = {INSTR_EXTBS}; \ + wildcard bins instr_extbz = {INSTR_EXTBZ}; \ + wildcard bins instr_paddnr = {INSTR_PADDNR}; \ + wildcard bins instr_paddunr = {INSTR_PADDUNR}; \ + wildcard bins instr_paddrnr = {INSTR_PADDRNR}; \ + wildcard bins instr_paddurnr = {INSTR_PADDURNR}; \ + wildcard bins instr_psubnr = {INSTR_PSUBNR}; \ + wildcard bins instr_psubunr = {INSTR_PSUBUNR}; \ + wildcard bins instr_psubrnr = {INSTR_PSUBRNR}; \ + wildcard bins instr_psuburnr = {INSTR_PSUBURNR}; \ + wildcard bins instr_pabs = {INSTR_PABS}; \ + wildcard bins instr_pclip = {INSTR_PCLIP}; \ + wildcard bins instr_pclipu = {INSTR_PCLIPU}; \ + wildcard bins instr_pclipr = {INSTR_PCLIPR}; \ + wildcard bins instr_pclipur = {INSTR_PCLIPUR}; \ + wildcard bins instr_pslet = {INSTR_PSLET}; \ + wildcard bins instr_psletu = {INSTR_PSLETU}; \ + wildcard bins instr_pmin = {INSTR_PMIN}; \ + wildcard bins instr_pminu = {INSTR_PMINU}; \ + wildcard bins instr_pmax = {INSTR_PMAX}; \ + wildcard bins instr_pmaxu = {INSTR_PMAXU}; \ + wildcard bins instr_ror = {INSTR_ROR}; \ + wildcard bins instr_pbextr = {INSTR_PBEXTR}; \ + wildcard bins instr_pbextur = {INSTR_PBEXTUR}; \ + wildcard bins instr_pbinsr = {INSTR_PBINSR}; \ + wildcard bins instr_pbclrr = {INSTR_PBCLRR}; \ + wildcard bins instr_pbsetr = {INSTR_PBSETR}; \ + wildcard bins instr_pmac = {INSTR_PMAC}; \ + wildcard bins instr_pmsu = {INSTR_PMSU}; \ + // CUSTOM_2 \ + wildcard bins instr_pbext = {INSTR_PBEXT}; \ + wildcard bins instr_pbextu = {INSTR_PBEXTU}; \ + wildcard bins instr_pbins = {INSTR_PBINS}; \ + wildcard bins instr_pbclr = {INSTR_PBCLR}; \ + wildcard bins instr_pbset = {INSTR_PBSET}; \ + wildcard bins instr_pbrev = {INSTR_PBREV}; \ + wildcard bins instr_paddn = {INSTR_PADDN}; \ + wildcard bins instr_paddun = {INSTR_PADDUN}; \ + wildcard bins instr_paddrn = {INSTR_PADDRN}; \ + wildcard bins instr_paddurn = {INSTR_PADDURN}; \ + wildcard bins instr_psubn = {INSTR_PSUBN}; \ + wildcard bins instr_psubun = {INSTR_PSUBUN}; \ + wildcard bins instr_psubrn = {INSTR_PSUBRN}; \ + wildcard bins instr_psuburn = {INSTR_PSUBURN}; \ + wildcard bins instr_pmulsn = {INSTR_PMULSN}; \ + wildcard bins instr_pmulhhsn = {INSTR_PMULHHSN}; \ + wildcard bins instr_pmulsrn = {INSTR_PMULSRN}; \ + wildcard bins instr_pmulhhsrn = {INSTR_PMULHHSRN}; \ + wildcard bins instr_pmulun = {INSTR_PMULUN}; \ + wildcard bins instr_pmulhhun = {INSTR_PMULHHUN}; \ + wildcard bins instr_pmulurn = {INSTR_PMULURN}; \ + wildcard bins instr_pmulhhurn = {INSTR_PMULHHURN}; \ + wildcard bins instr_pmacsn = {INSTR_PMACSN}; \ + wildcard bins instr_pmachhsn = {INSTR_PMACHHSN}; \ + wildcard bins instr_pmacsrn = {INSTR_PMACSRN}; \ + wildcard bins instr_pmachhsrn = {INSTR_PMACHHSRN}; \ + wildcard bins instr_pmacun = {INSTR_PMACUN}; \ + wildcard bins instr_pmachhun = {INSTR_PMACHHUN}; \ + wildcard bins instr_pmacurn = {INSTR_PMACURN}; \ + wildcard bins instr_pmachhurn = {INSTR_PMACHHURN}; \ + // CUSTOM_3 \ + // SIMD ALU \ + wildcard bins instr_cvaddh = {INSTR_CVADDH}; \ + wildcard bins instr_cvaddsch = {INSTR_CVADDSCH}; \ + wildcard bins instr_cvaddscih = {INSTR_CVADDSCIH}; \ + wildcard bins instr_cvaddb = {INSTR_CVADDB}; \ + wildcard bins instr_cvaddscb = {INSTR_CVADDSCB}; \ + wildcard bins instr_cvaddscib = {INSTR_CVADDSCIB}; \ + wildcard bins instr_cvsubh = {INSTR_CVSUBH}; \ + wildcard bins instr_cvsubsch = {INSTR_CVSUBSCH}; \ + wildcard bins instr_cvsubscih = {INSTR_CVSUBSCIH}; \ + wildcard bins instr_cvsubb = {INSTR_CVSUBB}; \ + wildcard bins instr_cvsubscb = {INSTR_CVSUBSCB}; \ + wildcard bins instr_cvsubscib = {INSTR_CVSUBSCIB}; \ + wildcard bins instr_cvavgh = {INSTR_CVAVGH}; \ + wildcard bins instr_cvavgsch = {INSTR_CVAVGSCH}; \ + wildcard bins instr_cvavgscih = {INSTR_CVAVGSCIH}; \ + wildcard bins instr_cvavgb = {INSTR_CVAVGB}; \ + wildcard bins instr_cvavgscb = {INSTR_CVAVGSCB}; \ + wildcard bins instr_cvavgscib = {INSTR_CVAVGSCIB}; \ + wildcard bins instr_cvavguh = {INSTR_CVAVGUH}; \ + wildcard bins instr_cvavgusch = {INSTR_CVAVGUSCH}; \ + wildcard bins instr_cvavguscih = {INSTR_CVAVGUSCIH}; \ + wildcard bins instr_cvavgub = {INSTR_CVAVGUB}; \ + wildcard bins instr_cvavguscb = {INSTR_CVAVGUSCB}; \ + wildcard bins instr_cvavguscib = {INSTR_CVAVGUSCIB}; \ + wildcard bins instr_cvminh = {INSTR_CVMINH}; \ + wildcard bins instr_cvminsch = {INSTR_CVMINSCH}; \ + wildcard bins instr_cvminscih = {INSTR_CVMINSCIH}; \ + wildcard bins instr_cvminb = {INSTR_CVMINB}; \ + wildcard bins instr_cvminscb = {INSTR_CVMINSCB}; \ + wildcard bins instr_cvminscib = {INSTR_CVMINSCIB}; \ + wildcard bins instr_cvminuh = {INSTR_CVMINUH}; \ + wildcard bins instr_cvminusch = {INSTR_CVMINUSCH}; \ + wildcard bins instr_cvminuscih = {INSTR_CVMINUSCIH}; \ + wildcard bins instr_cvminub = {INSTR_CVMINUB}; \ + wildcard bins instr_cvminuscb = {INSTR_CVMINUSCB}; \ + wildcard bins instr_cvminuscib = {INSTR_CVMINUSCIB}; \ + wildcard bins instr_cvmaxh = {INSTR_CVMAXH}; \ + wildcard bins instr_cvmaxsch = {INSTR_CVMAXSCH}; \ + wildcard bins instr_cvmaxscih = {INSTR_CVMAXSCIH}; \ + wildcard bins instr_cvmaxb = {INSTR_CVMAXB}; \ + wildcard bins instr_cvmaxscb = {INSTR_CVMAXSCB}; \ + wildcard bins instr_cvmaxscib = {INSTR_CVMAXSCIB}; \ + wildcard bins instr_cvmaxuh = {INSTR_CVMAXUH}; \ + wildcard bins instr_cvmaxusch = {INSTR_CVMAXUSCH}; \ + wildcard bins instr_cvmaxuscih = {INSTR_CVMAXUSCIH}; \ + wildcard bins instr_cvmaxub = {INSTR_CVMAXUB}; \ + wildcard bins instr_cvmaxuscb = {INSTR_CVMAXUSCB}; \ + wildcard bins instr_cvmaxuscib = {INSTR_CVMAXUSCIB}; \ + wildcard bins instr_cvsrlh = {INSTR_CVSRLH}; \ + wildcard bins instr_cvsrlsch = {INSTR_CVSRLSCH}; \ + wildcard bins instr_cvsrlscih = {INSTR_CVSRLSCIH}; \ + wildcard bins instr_cvsrlb = {INSTR_CVSRLB}; \ + wildcard bins instr_cvsrlscb = {INSTR_CVSRLSCB}; \ + wildcard bins instr_cvsrlscib = {INSTR_CVSRLSCIB}; \ + wildcard bins instr_cvsrah = {INSTR_CVSRAH}; \ + wildcard bins instr_cvsrasch = {INSTR_CVSRASCH}; \ + wildcard bins instr_cvsrascih = {INSTR_CVSRASCIH}; \ + wildcard bins instr_cvsrab = {INSTR_CVSRAB}; \ + wildcard bins instr_cvsrascb = {INSTR_CVSRASCB}; \ + wildcard bins instr_cvsrascib = {INSTR_CVSRASCIB}; \ + wildcard bins instr_cvsllh = {INSTR_CVSLLH}; \ + wildcard bins instr_cvsllsch = {INSTR_CVSLLSCH}; \ + wildcard bins instr_cvsllscih = {INSTR_CVSLLSCIH}; \ + wildcard bins instr_cvsllb = {INSTR_CVSLLB}; \ + wildcard bins instr_cvsllscb = {INSTR_CVSLLSCB}; \ + wildcard bins instr_cvsllscib = {INSTR_CVSLLSCIB}; \ + wildcard bins instr_cvorh = {INSTR_CVORH}; \ + wildcard bins instr_cvorsch = {INSTR_CVORSCH}; \ + wildcard bins instr_cvorscih = {INSTR_CVORSCIH}; \ + wildcard bins instr_cvorb = {INSTR_CVORB}; \ + wildcard bins instr_cvorscb = {INSTR_CVORSCB}; \ + wildcard bins instr_cvorscib = {INSTR_CVORSCIB}; \ + wildcard bins instr_cvxorh = {INSTR_CVXORH}; \ + wildcard bins instr_cvxorsch = {INSTR_CVXORSCH}; \ + wildcard bins instr_cvxorscih = {INSTR_CVXORSCIH}; \ + wildcard bins instr_cvxorb = {INSTR_CVXORB}; \ + wildcard bins instr_cvxorscb = {INSTR_CVXORSCB}; \ + wildcard bins instr_cvxorscib = {INSTR_CVXORSCIB}; \ + wildcard bins instr_cvandh = {INSTR_CVANDH}; \ + wildcard bins instr_cvandsch = {INSTR_CVANDSCH}; \ + wildcard bins instr_cvandscih = {INSTR_CVANDSCIH}; \ + wildcard bins instr_cvandb = {INSTR_CVANDB}; \ + wildcard bins instr_cvandscb = {INSTR_CVANDSCB}; \ + wildcard bins instr_cvandscib = {INSTR_CVANDSCIB}; \ + wildcard bins instr_cvabsh = {INSTR_CVABSH}; \ + wildcard bins instr_cvabsb = {INSTR_CVABSB}; \ + wildcard bins instr_cvextracth = {INSTR_CVEXTRACTH}; \ + wildcard bins instr_cvextractb = {INSTR_CVEXTRACTB}; \ + wildcard bins instr_cvextractuh = {INSTR_CVEXTRACTUH}; \ + wildcard bins instr_cvextractub = {INSTR_CVEXTRACTUB}; \ + wildcard bins instr_cvinserth = {INSTR_CVINSERTH}; \ + wildcard bins instr_cvinsertb = {INSTR_CVINSERTB}; \ + wildcard bins instr_cvdotuph = {INSTR_CVDOTUPH}; \ + wildcard bins instr_cvdotupsch = {INSTR_CVDOTUPSCH}; \ + wildcard bins instr_cvdotupscih = {INSTR_CVDOTUPSCIH}; \ + wildcard bins instr_cvdotupb = {INSTR_CVDOTUPB}; \ + wildcard bins instr_cvdotupscb = {INSTR_CVDOTUPSCB}; \ + wildcard bins instr_cvdotupscib = {INSTR_CVDOTUPSCIB}; \ + wildcard bins instr_cvdotusph = {INSTR_CVDOTUSPH}; \ + wildcard bins instr_cvdotuspsch = {INSTR_CVDOTUSPSCH}; \ + wildcard bins instr_cvdotuspscih = {INSTR_CVDOTUSPSCIH}; \ + wildcard bins instr_cvdotuspb = {INSTR_CVDOTUSPB}; \ + wildcard bins instr_cvdotuspscb = {INSTR_CVDOTUSPSCB}; \ + wildcard bins instr_cvdotuspscib = {INSTR_CVDOTUSPSCIB}; \ + wildcard bins instr_cvdotsph = {INSTR_CVDOTSPH}; \ + wildcard bins instr_cvdotspsch = {INSTR_CVDOTSPSCH}; \ + wildcard bins instr_cvdotspscih = {INSTR_CVDOTSPSCIH}; \ + wildcard bins instr_cvdotspb = {INSTR_CVDOTSPB}; \ + wildcard bins instr_cvdotspscb = {INSTR_CVDOTSPSCB}; \ + wildcard bins instr_cvdotspscib = {INSTR_CVDOTSPSCIB}; \ + wildcard bins instr_cvsdotuph = {INSTR_CVSDOTUPH}; \ + wildcard bins instr_cvsdotupsch = {INSTR_CVSDOTUPSCH}; \ + wildcard bins instr_cvsdotupscih = {INSTR_CVSDOTUPSCIH}; \ + wildcard bins instr_cvsdotupb = {INSTR_CVSDOTUPB}; \ + wildcard bins instr_cvsdotupscb = {INSTR_CVSDOTUPSCB}; \ + wildcard bins instr_cvsdotupscib = {INSTR_CVSDOTUPSCIB}; \ + wildcard bins instr_cvsdotusph = {INSTR_CVSDOTUSPH}; \ + wildcard bins instr_cvsdotuspsch = {INSTR_CVSDOTUSPSCH}; \ + wildcard bins instr_cvsdotuspscih = {INSTR_CVSDOTUSPSCIH}; \ + wildcard bins instr_cvsdotuspb = {INSTR_CVSDOTUSPB}; \ + wildcard bins instr_cvsdotuspscb = {INSTR_CVSDOTUSPSCB}; \ + wildcard bins instr_cvsdotuspscib = {INSTR_CVSDOTUSPSCIB}; \ + wildcard bins instr_cvsdotsph = {INSTR_CVSDOTSPH}; \ + wildcard bins instr_cvsdotspsch = {INSTR_CVSDOTSPSCH}; \ + wildcard bins instr_cvsdotspscih = {INSTR_CVSDOTSPSCIH}; \ + wildcard bins instr_cvsdotspb = {INSTR_CVSDOTSPB}; \ + wildcard bins instr_cvsdotspscb = {INSTR_CVSDOTSPSCB}; \ + wildcard bins instr_cvsdotspscib = {INSTR_CVSDOTSPSCIB}; \ + wildcard bins instr_cvshuffleh = {INSTR_CVSHUFFLEH}; \ + wildcard bins instr_cvshufflescih = {INSTR_CVSHUFFLESCIH}; \ + wildcard bins instr_cvshuffleb = {INSTR_CVSHUFFLEB}; \ + wildcard bins instr_cvshufflel0scib = {INSTR_CVSHUFFLEL0SCIB}; \ + wildcard bins instr_cvshufflel1scib = {INSTR_CVSHUFFLEL1SCIB}; \ + wildcard bins instr_cvshufflel2scib = {INSTR_CVSHUFFLEL2SCIB}; \ + wildcard bins instr_cvshufflel3scib = {INSTR_CVSHUFFLEL3SCIB}; \ + wildcard bins instr_cvshuffle2h = {INSTR_CVSHUFFLE2H}; \ + wildcard bins instr_cvshuffle2b = {INSTR_CVSHUFFLE2B}; \ + wildcard bins instr_cvpack = {INSTR_CVPACK}; \ + wildcard bins instr_cvpackh = {INSTR_CVPACKH}; \ + wildcard bins instr_cvpackhib = {INSTR_CVPACKHIB}; \ + wildcard bins instr_cvpacklob = {INSTR_CVPACKLOB}; \ + // SIMD COMPARISON \ + wildcard bins instr_cvcmpeqh = {INSTR_CVCMPEQH}; \ + wildcard bins instr_cvcmpeqsch = {INSTR_CVCMPEQSCH}; \ + wildcard bins instr_cvcmpeqscih = {INSTR_CVCMPEQSCIH}; \ + wildcard bins instr_cvcmpeqb = {INSTR_CVCMPEQB}; \ + wildcard bins instr_cvcmpeqscb = {INSTR_CVCMPEQSCB}; \ + wildcard bins instr_cvcmpeqscib = {INSTR_CVCMPEQSCIB}; \ + wildcard bins instr_cvcmpneh = {INSTR_CVCMPNEH}; \ + wildcard bins instr_cvcmpnesch = {INSTR_CVCMPNESCH}; \ + wildcard bins instr_cvcmpnescih = {INSTR_CVCMPNESCIH}; \ + wildcard bins instr_cvcmpneb = {INSTR_CVCMPNEB}; \ + wildcard bins instr_cvcmpnescb = {INSTR_CVCMPNESCB}; \ + wildcard bins instr_cvcmpnescib = {INSTR_CVCMPNESCIB}; \ + wildcard bins instr_cvcmpgth = {INSTR_CVCMPGTH}; \ + wildcard bins instr_cvcmpgtsch = {INSTR_CVCMPGTSCH}; \ + wildcard bins instr_cvcmpgtscih = {INSTR_CVCMPGTSCIH}; \ + wildcard bins instr_cvcmpgtb = {INSTR_CVCMPGTB}; \ + wildcard bins instr_cvcmpgtscb = {INSTR_CVCMPGTSCB}; \ + wildcard bins instr_cvcmpgtscib = {INSTR_CVCMPGTSCIB}; \ + wildcard bins instr_cvcmpgeh = {INSTR_CVCMPGEH}; \ + wildcard bins instr_cvcmpgesch = {INSTR_CVCMPGESCH}; \ + wildcard bins instr_cvcmpgescih = {INSTR_CVCMPGESCIH}; \ + wildcard bins instr_cvcmpgeb = {INSTR_CVCMPGEB}; \ + wildcard bins instr_cvcmpgescb = {INSTR_CVCMPGESCB}; \ + wildcard bins instr_cvcmpgescib = {INSTR_CVCMPGESCIB}; \ + wildcard bins instr_cvcmplth = {INSTR_CVCMPLTH}; \ + wildcard bins instr_cvcmpltsch = {INSTR_CVCMPLTSCH}; \ + wildcard bins instr_cvcmpltscih = {INSTR_CVCMPLTSCIH}; \ + wildcard bins instr_cvcmpltb = {INSTR_CVCMPLTB}; \ + wildcard bins instr_cvcmpltscb = {INSTR_CVCMPLTSCB}; \ + wildcard bins instr_cvcmpltscib = {INSTR_CVCMPLTSCIB}; \ + wildcard bins instr_cvcmpleh = {INSTR_CVCMPLEH}; \ + wildcard bins instr_cvcmplesch = {INSTR_CVCMPLESCH}; \ + wildcard bins instr_cvcmplescih = {INSTR_CVCMPLESCIH}; \ + wildcard bins instr_cvcmpleb = {INSTR_CVCMPLEB}; \ + wildcard bins instr_cvcmplescb = {INSTR_CVCMPLESCB}; \ + wildcard bins instr_cvcmplescib = {INSTR_CVCMPLESCIB}; \ + wildcard bins instr_cvcmpgtuh = {INSTR_CVCMPGTUH}; \ + wildcard bins instr_cvcmpgtusch = {INSTR_CVCMPGTUSCH}; \ + wildcard bins instr_cvcmpgtuscih = {INSTR_CVCMPGTUSCIH}; \ + wildcard bins instr_cvcmpgtub = {INSTR_CVCMPGTUB}; \ + wildcard bins instr_cvcmpgtuscb = {INSTR_CVCMPGTUSCB}; \ + wildcard bins instr_cvcmpgtuscib = {INSTR_CVCMPGTUSCIB}; \ + wildcard bins instr_cvcmpgeuh = {INSTR_CVCMPGEUH}; \ + wildcard bins instr_cvcmpgeusch = {INSTR_CVCMPGEUSCH}; \ + wildcard bins instr_cvcmpgeuscih = {INSTR_CVCMPGEUSCIH}; \ + wildcard bins instr_cvcmpgeub = {INSTR_CVCMPGEUB}; \ + wildcard bins instr_cvcmpgeuscb = {INSTR_CVCMPGEUSCB}; \ + wildcard bins instr_cvcmpgeuscib = {INSTR_CVCMPGEUSCIB}; \ + wildcard bins instr_cvcmpltuh = {INSTR_CVCMPLTUH}; \ + wildcard bins instr_cvcmpltusch = {INSTR_CVCMPLTUSCH}; \ + wildcard bins instr_cvcmpltuscih = {INSTR_CVCMPLTUSCIH}; \ + wildcard bins instr_cvcmpltub = {INSTR_CVCMPLTUB}; \ + wildcard bins instr_cvcmpltuscb = {INSTR_CVCMPLTUSCB}; \ + wildcard bins instr_cvcmpltuscib = {INSTR_CVCMPLTUSCIB}; \ + wildcard bins instr_cvcmpleuh = {INSTR_CVCMPLEUH}; \ + wildcard bins instr_cvcmpleusch = {INSTR_CVCMPLEUSCH}; \ + wildcard bins instr_cvcmpleuscih = {INSTR_CVCMPLEUSCIH}; \ + wildcard bins instr_cvcmpleub = {INSTR_CVCMPLEUB}; \ + wildcard bins instr_cvcmpleuscb = {INSTR_CVCMPLEUSCB}; \ + wildcard bins instr_cvcmpleuscib = {INSTR_CVCMPLEUSCIB}; \ + // SIMD CPLX \ + wildcard bins instr_cvcplxmulr = {INSTR_CVCPLXMULR}; \ + wildcard bins instr_cvcplxmulrdiv2 = {INSTR_CVCPLXMULRDIV2}; \ + wildcard bins instr_cvcplxmulrdiv4 = {INSTR_CVCPLXMULRDIV4}; \ + wildcard bins instr_cvcplxmulrdiv8 = {INSTR_CVCPLXMULRDIV8}; \ + wildcard bins instr_cvcplxmuli = {INSTR_CVCPLXMULI}; \ + wildcard bins instr_cvcplxmulidiv2 = {INSTR_CVCPLXMULIDIV2}; \ + wildcard bins instr_cvcplxmulidiv4 = {INSTR_CVCPLXMULIDIV4}; \ + wildcard bins instr_cvcplxmulidiv8 = {INSTR_CVCPLXMULIDIV8}; \ + wildcard bins instr_cvcplxconj = {INSTR_CVCPLXCONJ}; \ + wildcard bins instr_cvsubrotmj = {INSTR_CVSUBROTMJ}; \ + wildcard bins instr_cvsubrotmjdiv2 = {INSTR_CVSUBROTMJDIV2}; \ + wildcard bins instr_cvsubrotmjdiv4 = {INSTR_CVSUBROTMJDIV4}; \ + wildcard bins instr_cvsubrotmjdiv8 = {INSTR_CVSUBROTMJDIV8}; \ + wildcard bins instr_cvaddiv2 = {INSTR_CVADDIV2}; \ + wildcard bins instr_cvaddiv4 = {INSTR_CVADDIV4}; \ + wildcard bins instr_cvaddiv8 = {INSTR_CVADDIV8}; \ + wildcard bins instr_cvsubiv2 = {INSTR_CVSUBIV2}; \ + wildcard bins instr_cvsubiv4 = {INSTR_CVSUBIV4}; \ + wildcard bins instr_cvsubiv8 = {INSTR_CVSUBIV8}; \ + // Load-Store (RV32F) \ + wildcard bins instr_flw = {INSTR_FLW}; \ + wildcard bins instr_fsw = {INSTR_FSW}; \ + // user-defined instructions \ + wildcard bins instr_illegal_exception = {{INSN_ILLEGAL}}; \ + wildcard bins instr_ebreakm = {{INSN_EBREAKM}}; \ + // Others \ + illegal_bins other_instr = default; \ + } \ + ccp_hwloop_type_setup_insn_list : cross cp_hwloop_type, cp_hwloop_setup, cp_insn_list_in_hwloop; \ + ccp_hwloop_type_irq : cross cp_hwloop_type, cp_hwloop_irq; \ + ccp_hwloop_type_dbg_mode : cross cp_hwloop_type, cp_hwloop_dbg_haltreq; \ + ccp_hwloop_type_dbg_trigger : cross cp_hwloop_type, cp_hwloop_dbg_trigger; \ + ccp_hwloop_type_dbg_step_cnt : cross cp_hwloop_type, cp_hwloop_dbg_step_cnt { \ + bins ccp_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt) intersect {[1:4]} ; \ + bins ccp_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt) intersect {[5:20]} ; \ + bins ccp_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt) intersect {[20:50]} ; \ + bins ccp_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt) intersect {[51:$]} ; \ + } /* todo: x with lpcount */ \ + endgroup : cg_features_of_hwloop_``LOOP_IDX`` + + `DEF_CG_CSR_HWLOOP(0) + `DEF_CG_CSR_HWLOOP(1) + `DEF_CG_FEATURES_OF_HWLOOP(0) + `DEF_CG_FEATURES_OF_HWLOOP(1) + + // COVERGROUPS DEFINE HERE - START + + `uvm_component_utils(uvme_rv32x_hwloop_covg) + + function new(string name="uvme_rv32x_hwloop_covg", uvm_component parent=null); + super.new(name, parent); + `CG_CSR_HWLOOP(0) = new(); `CG_CSR_HWLOOP(0).set_inst_name($sformatf("cg_csr_hwloop_0")); + `CG_CSR_HWLOOP(1) = new(); `CG_CSR_HWLOOP(1).set_inst_name($sformatf("cg_csr_hwloop_1")); + `CG_FEATURES_OF_HWLOOP(0) = new(); `CG_FEATURES_OF_HWLOOP(0).set_inst_name($sformatf("cg_features_of_hwloop_0")); + `CG_FEATURES_OF_HWLOOP(1) = new(); `CG_FEATURES_OF_HWLOOP(1).set_inst_name($sformatf("cg_features_of_hwloop_1")); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + if (!(uvm_config_db#(virtual uvmt_cv32e40p_rvvi_if)::get(this, "", "cv32e40p_rvvi_vif", cv32e40p_rvvi_vif))) begin + `uvm_fatal(_header, "cv32e40p_rvvi_vif no found in uvm_config_db"); + end + endfunction : build_phase + + // task to sample cg_csr_hwloop + `define CHECK_N_SAMPLE_CSR_HWLOOP(TYPE) check_n_sample_csr_hwloop_``TYPE``(); + `define DEF_CHECK_N_SAMPLE_CSR_HWLOOP(TYPE) task check_n_sample_csr_hwloop_``TYPE``(); \ + for (int i=0; i= 0); \ + end \ + if (hwloop_stat_``TYPE``.track_lp_count[i] != hwloop_stat_``TYPE``.hwloop_csr.lp_count[i]) done_insn_list_capture_``TYPE``[i] = 1; \ + end \ + 1 : begin // in nested, skip when executing hwloop0 \ + if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_count[0] != 0) begin \ + in_nested_loop0 = 1; continue; \ + end \ + else if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_count[0] == 0 && in_nested_loop0) begin \ + in_nested_loop0 = 0; continue; \ + end \ + if (!done_insn_list_capture_``TYPE``[i]) begin \ + if (is_illegal) insn_list_in_hwloop_``TYPE``[i].push_back(INSN_ILLEGAL); \ + else if (is_ebreakm) insn_list_in_hwloop_``TYPE``[i].push_back(INSN_EBREAKM); \ + else insn_list_in_hwloop_``TYPE``[i].push_back(cv32e40p_rvvi_vif.insn); \ + end \ + else if (is_ebreakm) begin \ + insn_list_in_hwloop_``TYPE``[i].push_back(INSN_EBREAKM); \ + end \ + if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i)) begin \ + hwloop_stat_``TYPE``.track_lp_count[i]--; \ + assert(hwloop_stat_``TYPE``.track_lp_count[i] >= 0); \ + end \ + if (hwloop_stat_``TYPE``.track_lp_count[i] != hwloop_stat_``TYPE``.hwloop_csr.lp_count[i]) done_insn_list_capture_``TYPE``[i] = 1; \ + end \ + endcase \ + end \ + end // COLLECT_INSTR \ + if ( \ + (hwloop_stat_``TYPE``.hwloop_type == NESTED && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_count[1] == 0) || \ + (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_count[1] == 0) || \ + (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[0] && hwloop_stat_``TYPE``.track_lp_count[0] == 0) \ + ) begin : SAMPLE_END_OF_HWLOOPS \ + for (int i=0; i= csr_hwloop.lp_start[idx] && cv32e40p_rvvi_vif.pc_rdata <= csr_hwloop.lp_end[idx]-4) return 1; + else return 0; + endfunction : is_pc_within_lp + +endclass : uvme_rv32x_hwloop_covg + +`endif diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv index 6bea3b51c8..9bb5c82771 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv @@ -81,6 +81,7 @@ package uvme_cv32e40p_pkg; // Environment components `include "uvma_cv32e40p_core_cntrl_drv.sv" `include "uvma_cv32e40p_core_cntrl_agent.sv" + `include "uvme_rv32x_hwloop_covg.sv" `include "uvme_interrupt_covg.sv" `include "uvme_debug_covg.sv" `include "uvme_rv32isa_covg.sv" diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv b/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv index 13835bf996..a8a3b0eaed 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv @@ -123,4 +123,18 @@ typedef enum { FETCH_RANDOM_TOGGLE } fetch_toggle_t; +typedef enum logic [2:0] { + EBREAKM = 1, + TRIGGER = 2, + HALTREQ = 3, + STEP = 4, + RESETHALTREQ = 5 +} dcsr_cause_t; + +typedef enum logic [4:0] { + CODE_ILLEGAL = 2, + CODE_EBREAK = 3, + CODE_ECALL = 11 +} exception_code_t; + `endif // __UVME_CV32E40P_TDEFS_SV__ diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 15fadf368a..06ed86a768 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -418,7 +418,9 @@ interface uvmt_cv32e40p_rvvi_if #( wire [2:0] csr_dcsr_cause; wire [31:0] csr_trig_pc; - assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; + logic [31:0] irq_onehot_priority; + + assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; // fixme: rvfi misses mip (pending for resolution) assign dbg_req = debug_if.debug_req; assign csr_mcause_irq = csr[`CSR_MCAUSE_ADDR][31]; @@ -443,6 +445,18 @@ interface uvmt_cv32e40p_rvvi_if #( `ASSIGN_CSR_N_WB(`CSR_DCSR_ADDR, dcsr) `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA1_ADDR, tdata, 1); `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA2_ADDR, tdata, 2); + + // irq_onehot_priority assignment + // priority order (high->low) is irq[31]...irq[16], irq[11], irq[3], irq[7] + always @(valid_irq) begin + irq_onehot_priority = 0; + for (int i = 31; i != 0; i--) begin + if (valid_irq[i] && (i inside {31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16, 11,3,7})) begin + if (i == 7 && valid_irq[3]) continue; + else begin irq_onehot_priority[i] = valid_irq[i]; break; end + end + end + end endinterface