From 598fb411ceeaea75ccc71e1f4178faa18d77081f Mon Sep 17 00:00:00 2001
From: luyahan <yahan@iscas.ac.cn>
Date: Mon, 29 Mar 2021 14:45:47 +0900
Subject: [PATCH] riscv64: Add riscv64 configure

 v8 had been add riscv64 backend, so i open this
pr to add riscv64 configure.

Refs: https://github.com/nodejs/node/issues/37856
---
 configure.py                     |  2 +-
 tools/v8_gypfiles/toolchain.gypi |  5 +++++
 tools/v8_gypfiles/v8.gyp         | 17 ++++++++++++++++-
 3 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/configure.py b/configure.py
index 784e21475dfa0e..65fcbc8f28267c 100755
--- a/configure.py
+++ b/configure.py
@@ -47,7 +47,7 @@
 valid_os = ('win', 'mac', 'solaris', 'freebsd', 'openbsd', 'linux',
             'android', 'aix', 'cloudabi')
 valid_arch = ('arm', 'arm64', 'ia32', 'mips', 'mipsel', 'mips64el', 'ppc',
-              'ppc64', 'x32','x64', 'x86', 'x86_64', 's390x')
+              'ppc64', 'x32','x64', 'x86', 'x86_64', 's390x', 'riscv64')
 valid_arm_float_abi = ('soft', 'softfp', 'hard')
 valid_arm_fpu = ('vfp', 'vfpv3', 'vfpv3-d16', 'neon')
 valid_mips_arch = ('loongson', 'r1', 'r2', 'r6', 'rx')
diff --git a/tools/v8_gypfiles/toolchain.gypi b/tools/v8_gypfiles/toolchain.gypi
index 165ba936e562d5..a2def9caef2891 100644
--- a/tools/v8_gypfiles/toolchain.gypi
+++ b/tools/v8_gypfiles/toolchain.gypi
@@ -273,6 +273,11 @@
           }],
         ],
       }],
+      ['v8_target_arch=="riscv64"', {
+        'defines': [
+          'V8_TARGET_ARCH_RISCV64',
+        ],
+      }],
       ['v8_target_arch=="s390x"', {
         'defines': [
           'V8_TARGET_ARCH_S390',
diff --git a/tools/v8_gypfiles/v8.gyp b/tools/v8_gypfiles/v8.gyp
index 2b2d4234a665ea..ef5319fa08f0db 100644
--- a/tools/v8_gypfiles/v8.gyp
+++ b/tools/v8_gypfiles/v8.gyp
@@ -274,6 +274,11 @@
             '<(V8_ROOT)/src/builtins/mips/builtins-mips.cc',
           ],
         }],
+        ['v8_target_arch=="riscv64" or v8_target_arch=="riscv64"', {
+          'sources': [
+            '<(V8_ROOT)/src/builtins/riscv64/builtins-riscv64.cc',
+          ],
+        }],        
         ['v8_target_arch=="mips64" or v8_target_arch=="mips64el"', {
           'sources': [
             '<(V8_ROOT)/src/builtins/mips64/builtins-mips64.cc',
@@ -686,6 +691,11 @@
             '<!@pymod_do_main(GN-scraper "<(V8_ROOT)/BUILD.gn"  "\\"v8_base_without_compiler.*?v8_current_cpu == \\"mips\\".*?sources \+= ")',
           ],
         }],
+        ['v8_target_arch=="riscv64"', {
+          'sources': [  ### gcmole(arch:riscv64) ###
+            '<!@pymod_do_main(GN-scraper "<(V8_ROOT)/BUILD.gn"  "\\"v8_base_without_compiler.*?v8_current_cpu == \\"riscv64.*?sources \+= ")',
+          ],
+        }],        
         ['v8_target_arch=="mips64" or v8_target_arch=="mips64el"', {
           'sources': [  ### gcmole(arch:mips64el) ###
             '<!@pymod_do_main(GN-scraper "<(V8_ROOT)/BUILD.gn"  "\\"v8_base_without_compiler.*?v8_current_cpu == \\"mips64\\".*?sources \+= ")',
@@ -764,7 +774,7 @@
         }],
         # Platforms that don't have Compare-And-Swap (CAS) support need to link atomic library
         # to implement atomic memory access
-        ['v8_current_cpu in ["mips", "mipsel", "mips64", "mips64el", "ppc", "arm"]', {
+        ['v8_current_cpu in ["mips", "mipsel", "mips64", "mips64el", "ppc", "arm", "riscv64"]', {
           'link_settings': {
             'libraries': ['-latomic', ],
           },
@@ -1410,6 +1420,11 @@
                   '<(V8_ROOT)/src/heap/base/asm/mips64/push_registers_asm.cc',
                 ],
               }],
+              ['_toolset == "host" and host_arch == "riscv64" or _toolset == "target" and target_arch=="riscv64"', {
+                'sources': [
+                  '<(V8_ROOT)/src/heap/base/asm/riscv64/push_registers_asm.cc',
+                ],
+              }],
             ]
           }],
           ['OS=="win"', {