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Stumbled into this problem when simulating a Xilinx primitive (FIFO18E1). I've reduced to a minimal reproducible example:
library ieee; use ieee.std_logic_1164.all; entity folded_bug is generic ( DATA_WIDTH: integer := 4; FIFO_SIZE: integer := 36 ); end entity; architecture sim of folded_bug is function GetWidth ( rdwr_width : in integer ) return integer is variable func_width : integer; begin return rdwr_width; end; constant mem_width : integer := GetWidth(DATA_WIDTH); type Two_D_array_type is array (1 downto 0) of std_logic_vector((mem_width - 1) downto 0); signal mem : Two_D_array_type; begin process begin mem(0) <= (others => '1'); wait for 1 ns; mem(0) <= (others => '0'); wait for 1 ns; std.env.finish; end process; end architecture;
$ nvc --work=work --std=2008 -a folded_bug.vhd $ nvc --std=2008 -e --no-collapse folded_bug $ nvc -r --dump-arrays --exit-severity=error folded_bug --wave=folded_bug.fst --format=fst ** Fatal: expression cannot be folded to an integer constant > /tmp/nvc_folded_bug/folded_bug.vhd:20 | 20 | type Two_D_array_type is array (1 downto 0) of std_logic_vector((mem_width - 1) downto 0); | ^^^^^^^^^^^^^
nvc_folded_bug.zip
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Fixed in d0f7b34
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Stumbled into this problem when simulating a Xilinx primitive (FIFO18E1). I've reduced to a minimal reproducible example:
nvc_folded_bug.zip
The text was updated successfully, but these errors were encountered: