Missing hides constant warning

[BrunoJJE]

With the following code, ghdl gives a "hides constant" warning, but nvc gives no warning.

$ nvc --version         
nvc 1.12.2 (764659a) (Using LLVM 10.0.0)
Copyright (C) 2011-2024  Nick Gasson
This program comes with ABSOLUTELY NO WARRANTY. This is free software, and
you are welcome to redistribute it under certain conditions. See the GNU
General Public Licence for details.

$ nvc -a const_hides.vhd

$ ghdl -a const_hides.vhd
const_hides.vhd:40:33:warning: declaration of "i" hides constant "i" [-Whide]
                loop_part : for i in 0 to i loop
                                ^

"const_hides.vhd" code :

library ieee;
use ieee.std_logic_1164.all;


entity const_hides is
    port (
        rst      : in  std_logic;
        clk      : in  std_logic;

        i_part   : in  std_logic;
        o_result : out std_logic

    );
end entity const_hides;


architecture rtl of const_hides is

    constant C_NB : positive := 4;
    signal partA : std_logic_vector(C_NB downto 0);
    signal partB : std_logic_vector(C_NB downto 0);

begin

    partA(0) <= i_part;

    gen_i : for i in 0 to C_NB-1 generate

        proc_i : process(clk, rst)
        begin
            if (rst = '1') then

                partA(i+1) <= '0';

            elsif rising_edge(clk) then

                partA(i+1) <= partA(i);

                --loop_part : for k in 0 to i loop
                loop_part : for i in 0 to i loop  -- reusing the same generate loop index by accident 

                    if (partA(i) = '1') then
                        --partB(k+1) <= partB(k);
                        partB(i+1) <= partB(i);
                    end if;

                end loop loop_part;

            end if;
        end process proc_i;

    end generate gen_i;

    o_result <= partB(C_NB);

end architecture rtl;

[nickg]

I'm not a huge fan of these kinds of warnings as they tend to generate many false positives which are annoying. However in this case I think a warning would be helpful. I've tried to implement it in such a way that it only warns when the hidden declaration has the same type, and it doesn't warn if a declaration in a subprogram hides something outside the subprogram (e.g. if a parameter and an entity port have the same name). For your example it now reports:

** Warning: declaration of I hides an earlier declaration with the same type
    > test.vhd:40
    |
 27 |     gen_i : for i in 0 to C_NB-1 generate
    |                 ^ this declaration is hidden
 ...
 40 |                 loop_part : for i in 0 to i loop  -- reusing the same generate loop index by accident
    |                                 ^ by the constant declaration here