Waveforms available when UVVM-based testbench is simulated by nvc vs. ghdl

[yikkrubz]

When UVVM-based testbenches are simulated, nvc ships out only a subset of the waveforms
that are present when the design is simulated by ghdl or Questa. For example, for the testbench uart_vvc_demo_tb included with the UVVM distribution in the directory bitvis_uart, only the signals in the hierarchy below uart_vvc_demo_tb are available (see attached figures).

Is there a way to include the "missing" traces and generate the full set of waveforms like ghdl or Questa do? Am I missing something?

ghdl:

nvc 1.13-devel (1.12.0.r119.g4978acf1) (Using LLVM 18.1.3):

[nickg]

Signals from packages are dumped now.