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Vivado 2022.2 unisim library issue #646
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I think this is a regression. Although it's not strictly valid VHDL it used to work with |
Agreed, Vivado 2022.2 was working (in this respect) back when I raised issue #566. |
Can you try again with the latest master? I'd test it myself but the Vivado download is massive. |
OK that's improved. The reported error is now a warning, and the Vivado library install process completes. I did, however, see the following in the middle of the build process for NVC itself:
The above happened after checking out the latest master. I then tried a clean clone, and got a tiny change - errors after the CCLD step:
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I've seen that before while building the MSYS2 package. I'm not sure what causes it but it seems to be harmless. Presumably configuring with |
Confirmed.
Will do. |
The source for the unisim odelaye3 primitive has changed between Vivado 2022.1 and 2022.2. NVC does not like at least one change:
The PER_BIT_FINE_DELAY signal is declared with an initial value (5), in case this is relevant.
EDIT: observed using nvc 1.9-devel (1.8.0.r142.g65200f34) (Using LLVM 15.0.7)
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