diff --git a/vta/hardware/chisel/src/main/scala/shell/VME.scala b/vta/hardware/chisel/src/main/scala/shell/VME.scala
index 862e9810c510..db46295eeb34 100644
--- a/vta/hardware/chisel/src/main/scala/shell/VME.scala
+++ b/vta/hardware/chisel/src/main/scala/shell/VME.scala
@@ -191,7 +191,7 @@ class VME(implicit p: Parameters) extends Module {
       }
     }
     is (sWriteData) {
-      when (io.mem.w.ready && wr_cnt === io.vme.wr(0).cmd.bits.len) {
+      when (io.vme.wr(0).data.valid && io.mem.w.ready && wr_cnt === io.vme.wr(0).cmd.bits.len) {
         wstate := sWriteResp
       }
     }