From 2560ae616075e1ddadac76507a4e95d011f2ad5b Mon Sep 17 00:00:00 2001
From: Luis Vega <vegaluisjose@users.noreply.github.com>
Date: Mon, 27 May 2019 21:29:55 -0700
Subject: [PATCH] [VTA][TSIM] Use Module instead of RawModule for testbench by
 creating an empty bundle for the IO (#3242)

* use Module instead of RawModule for testbench by creating an empty bundle for the IO

* change default back to verilog
---
 .../chisel/src/test/scala/dut/TestAccel.scala | 26 +++++++------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/vta/apps/tsim_example/hardware/chisel/src/test/scala/dut/TestAccel.scala b/vta/apps/tsim_example/hardware/chisel/src/test/scala/dut/TestAccel.scala
index 45f81d50a50b..2c02ff36a631 100644
--- a/vta/apps/tsim_example/hardware/chisel/src/test/scala/dut/TestAccel.scala
+++ b/vta/apps/tsim_example/hardware/chisel/src/test/scala/dut/TestAccel.scala
@@ -20,7 +20,6 @@
 package test
 
 import chisel3._
-import chisel3.experimental.{RawModule, withClockAndReset}
 import vta.dpi._
 import accel._
 
@@ -29,21 +28,19 @@ import accel._
   * Instantiate Host and Memory DPI modules.
   *
   */
-class VTASimShell extends RawModule {
+class VTASimShell extends Module {
   val io = IO(new Bundle {
-    val clock = Input(Clock())
-    val reset = Input(Bool())
     val host = new VTAHostDPIMaster
     val mem = new VTAMemDPIClient
   })
   val host = Module(new VTAHostDPI)
   val mem = Module(new VTAMemDPI)
-  mem.io.reset := io.reset
-  mem.io.clock := io.clock
-  host.io.reset := io.reset
-  host.io.clock := io.clock
-  io.mem <> mem.io.dpi
+  mem.io.dpi <> io.mem
+  mem.io.reset := reset
+  mem.io.clock := clock
   io.host <> host.io.dpi
+  host.io.reset := reset
+  host.io.clock := clock
 }
 
 /** Test accelerator.
@@ -51,15 +48,10 @@ class VTASimShell extends RawModule {
   * Instantiate and connect the simulation-shell and the accelerator.
   *
   */
-class TestAccel extends RawModule {
-  val clock = IO(Input(Clock()))
-  val reset = IO(Input(Bool()))
-
+class TestAccel extends Module {
+  val io = IO(new Bundle {})
   val sim_shell = Module(new VTASimShell)
-  val vta_accel = withClockAndReset(clock, reset) { Module(new Accel) }
-
-  sim_shell.io.clock := clock
-  sim_shell.io.reset := reset
+  val vta_accel = Module(new Accel)
   vta_accel.io.host <> sim_shell.io.host
   sim_shell.io.mem <> vta_accel.io.mem
 }