From 147180b45e422a914fceeef16604417e3b8d3b8d Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 27 Oct 2020 12:48:36 +0100 Subject: [PATCH 01/15] rimage: update rimage: add configuration and extended manifest rimage dropped its "-m" parameter and switched over to using "-c" for a configuration file, including a target name. Add support for extended manifest for all cAVS versions. Signed-off-by: Guennadi Liakhovetski --- scripts/west_commands/sign.py | 19 +++++++++++++++++-- .../intel_adsp/cavs_v15/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v15/linker.ld | 15 +++++++++++++++ .../intel_adsp/cavs_v18/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v18/linker.ld | 15 +++++++++++++++ .../intel_adsp/cavs_v20/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v20/linker.ld | 14 ++++++++++++++ .../intel_adsp/cavs_v25/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v25/linker.ld | 15 +++++++++++++++ 9 files changed, 84 insertions(+), 2 deletions(-) diff --git a/scripts/west_commands/sign.py b/scripts/west_commands/sign.py index d37757c2d4c746..2539b512072d61 100644 --- a/scripts/west_commands/sign.py +++ b/scripts/west_commands/sign.py @@ -420,19 +420,34 @@ def sign(self, command, build_dir, bcfg, formats): board = cache['CACHED_BOARD'] log.inf('Signing for board ' + board) target = self.edt_get_rimage_target(board) - log.inf('Signing for SOC target ' + target) + conf = target + '.toml' + log.inf('Signing for SOC target ' + target + ' using ' + conf) if not args.quiet: log.inf('Signing with tool {}'.format(tool_path)) + s = pathlib.Path(os.environ.get('ZEPHYR_BASE')) + bootloader = str(b / 'zephyr' / 'bootloader.elf.mod') kernel = str(b / 'zephyr' / 'zephyr.elf.mod') out_bin = str(b / 'zephyr' / 'zephyr.ri') + out_xman = str(b / 'zephyr' / 'zephyr.ri.xman') + out_tmp = str(b / 'zephyr' / 'zephyr.rix') + conf_path = str(s / '..' / 'modules' / 'audio' / 'sof' / 'rimage' / 'config' / conf) sign_base = ([tool_path] + args.tool_args + - ['-o', out_bin, '-m', target, '-i', '3'] + + ['-o', out_bin, '-c', conf_path, '-i', '3', '-e'] + [bootloader, kernel]) if not args.quiet: log.inf(quote_sh_list(sign_base)) subprocess.check_call(sign_base) + + filenames = [out_xman, out_bin] + with open(out_tmp, 'wb') as outfile: + for fname in filenames: + with open(fname, 'rb') as infile: + outfile.write(infile.read()) + + os.remove(out_bin) + os.rename(out_tmp, out_bin) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 616654b588e3d9..d852fb80ad5b4a 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -142,6 +142,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index a7044ae04bee34..8586340c06faf4 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -132,6 +132,9 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE } PHDRS @@ -161,6 +164,7 @@ PHDRS ucram_phdr PT_LOAD; static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; } _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); @@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222; _memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2; PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + SECTIONS { @@ -567,4 +576,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index d496097b4b675f..473814e7d3c4d7 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -139,6 +139,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld index 7ab8a51d5fac80..e0141e203fca70 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld @@ -112,6 +112,9 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE } PHDRS @@ -141,6 +144,7 @@ PHDRS static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; } _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); @@ -194,6 +198,11 @@ _memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2; #endif PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + SECTIONS { @@ -532,4 +541,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 1a9983b03dce43..34b4a9d463a7b3 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -139,6 +139,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v20/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld index c24adfeb7c3e5a..b144b121039b71 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v20/linker.ld @@ -112,8 +112,15 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE } +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + PHDRS { vector_memory_lit_phdr PT_LOAD; @@ -141,6 +148,7 @@ PHDRS static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; } _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); @@ -532,4 +540,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 6c448a84189fa2..1ad6d443617844 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -139,6 +139,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld index 39a4c99b190644..a5c7cb46ea5b85 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld @@ -112,6 +112,9 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE lpsram_alt_reset_vec_seg : org = LP_SRAM_ALT_RESET_VEC_BASE, @@ -154,6 +157,7 @@ PHDRS static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; lpsram_mem_phdr PT_LOAD; sram_alt_fw_reset_vec_phdr PT_LOAD; @@ -214,6 +218,11 @@ _memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2; #endif PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + SECTIONS { @@ -600,4 +609,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } From 3d93fd97c5a19c6679bb62e16d0110e2c694aed2 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:28:56 +0200 Subject: [PATCH 02/15] cavs: fix manifest base address On cAVS 1.5, 2.0 and 2.5 platforms the correct manifest address is 0xB0032000. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 2 +- soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 2 +- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 473814e7d3c4d7..faa3f876bae55a 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -127,7 +127,7 @@ #define BOOT_LDR_STACK_SIZE (4 * 0x1000) /* Manifest base address in IMR - used by boot loader copy procedure. */ -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 /* Manifest size (seems unused). */ #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 34b4a9d463a7b3..0f96fa22922bd0 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -127,7 +127,7 @@ #define BOOT_LDR_STACK_SIZE (4 * 0x1000) /* Manifest base address in IMR - used by boot loader copy procedure. */ -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 /* Manifest size (seems unused). */ #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 1ad6d443617844..35dd0fbdfc83f7 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -127,7 +127,7 @@ #define BOOT_LDR_STACK_SIZE (4 * 0x1000) /* Manifest base address in IMR - used by boot loader copy procedure. */ -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 /* Manifest size (seems unused). */ #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 From 78c28b795f57ee341270982eac3d9173978d491f Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 3 Nov 2020 12:32:24 +0100 Subject: [PATCH 03/15] sof: remove superfluous and duplicate code 1. SOF doesn't have to be built in .bin format 2. don't include soc.c and soc_mp.c twice in cmake 3. remove an unused mailbox.h header Signed-off-by: Guennadi Liakhovetski --- samples/audio/sof/prj.conf | 1 + soc/xtensa/intel_adsp/common/CMakeLists.txt | 2 - soc/xtensa/intel_adsp/common/adsp.c | 2 - .../intel_adsp/common/include/cavs/mailbox.h | 62 ------------------- 4 files changed, 1 insertion(+), 66 deletions(-) delete mode 100644 soc/xtensa/intel_adsp/common/include/cavs/mailbox.h diff --git a/samples/audio/sof/prj.conf b/samples/audio/sof/prj.conf index 74c52d4a3e1eb8..2be9a027b56e9b 100644 --- a/samples/audio/sof/prj.conf +++ b/samples/audio/sof/prj.conf @@ -2,6 +2,7 @@ CONFIG_SOF=y CONFIG_SMP=n CONFIG_LOG=y CONFIG_MP_NUM_CPUS=1 +CONFIG_BUILD_OUTPUT_BIN=n # Requires heap_info() be implemented, but no Zephyr wrapper CONFIG_DEBUG_MEMORY_USAGE_SCAN=n diff --git a/soc/xtensa/intel_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/common/CMakeLists.txt index 8a323c21bc7046..d49817183ead2f 100644 --- a/soc/xtensa/intel_adsp/common/CMakeLists.txt +++ b/soc/xtensa/intel_adsp/common/CMakeLists.txt @@ -27,7 +27,5 @@ if(CONFIG_SOC_SERIES_INTEL_CAVS_V15 OR CONFIG_SOC_SERIES_INTEL_CAVS_V18 OR CONFIG_SOC_SERIES_INTEL_CAVS_V20 OR CONFIG_SOC_SERIES_INTEL_CAVS_V25) - zephyr_library_sources(soc.c) - zephyr_library_sources(soc_mp.c) include(bootloader.cmake) endif() diff --git a/soc/xtensa/intel_adsp/common/adsp.c b/soc/xtensa/intel_adsp/common/adsp.c index f5bab48fa892d5..6ed4f93b5a494f 100644 --- a/soc/xtensa/intel_adsp/common/adsp.c +++ b/soc/xtensa/intel_adsp/common/adsp.c @@ -17,8 +17,6 @@ LOG_MODULE_REGISTER(sof); #include #include -#include - /* * Sets up the host windows so that the host can see the memory * content on the DSP SRAM. diff --git a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h b/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h deleted file mode 100644 index fe06ab66037990..00000000000000 --- a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifndef __CAVS_MAILBOX_H__ -#define __CAVS_MAILBOX_H__ - -#include -#include - -/* - * The Window Region on HPSRAM for cAVS platforms is organised like this :- - * +--------------------------------------------------------------------------+ - * | Offset | Region | Size | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE | - * +---------------------+----------------+-----------------------------------+ - * - * Note: For suecreek SRAM_SW_REG window does not exist - MAILBOX_SW_REG_BASE - * and MAILBOX_SW_REG_BASE are equal to 0 - */ - - /* window 3 - trace */ -#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE -#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE - - /* window 2 debug, exception and stream */ -#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE -#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE - -#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE -#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE -#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE - -#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE -#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE -#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE) - - /* window 1 inbox/downlink and FW registers */ -#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE -#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE - - /* window 0 */ -#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE -#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE - -#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE -#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE - -#endif /* __CAVS_MAILBOX_H__ */ From 44afeb90180f3c4d115462f59e416d468cb5fae2 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 08:22:07 +0200 Subject: [PATCH 04/15] cavs: disable all interrupts when configuring interrupt controllers Some interrupts can be enabled by the ROM, e.g. the timer interrupt. When then in Zephyr the interrupt controller is enabled, before individual interrupts are configured, interrupts can arrive and lead to the spurious interrupt handler being invoked. Fix thid by disabling all child interrupts when configuring cAVS interrupt controllers. Signed-off-by: Guennadi Liakhovetski --- drivers/interrupt_controller/intc_cavs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c index c7b5205fba7207..38331e43ae3c33 100644 --- a/drivers/interrupt_controller/intc_cavs.c +++ b/drivers/interrupt_controller/intc_cavs.c @@ -132,6 +132,11 @@ static const struct irq_next_level_api cavs_apis = { #define CAVS_ICTL_INIT(n) \ static int cavs_ictl_##n##_initialize(const struct device *port) \ { \ + struct cavs_ictl_runtime *context = port->data; \ + volatile struct cavs_registers * const regs = \ + (struct cavs_registers *)context->base_addr; \ + regs->disable_il = ~0; \ + \ return 0; \ } \ \ From c8a3ecea46e758e2b14fb68bd45f00471eaf9d6e Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:34:59 +0200 Subject: [PATCH 05/15] xtensa: disable unused memory power down The current unused memory calculation is broken because it doesn't take into account the stack area, allocated at the top of HP SRAM. Until this is fixed disable powering down unused RAM. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/bootloader/boot_loader.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index a2f88ff9b61929..3319db295eef86 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -27,6 +27,7 @@ extern void __start(void); #if !defined(CONFIG_SOC_INTEL_S1000) #define MANIFEST_SEGMENT_COUNT 3 +#undef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static inline void idelay(int n) { @@ -125,6 +126,7 @@ static void parse_module(struct sof_man_fw_header *hdr, #define MAN_SKIP_ENTRIES 1 #endif +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static uint32_t get_fw_size_in_use(void) { struct sof_man_fw_desc *desc = @@ -153,6 +155,7 @@ static uint32_t get_fw_size_in_use(void) return fw_size_in_use; } +#endif /* parse FW manifest and copy modules */ static void parse_manifest(void) @@ -256,11 +259,13 @@ static uint32_t hp_sram_power_on_memory(uint32_t memory_size) return hp_sram_pm_banks(ebb_in_use); } +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size) { /* keep enabled only memory banks used by FW */ return hp_sram_power_on_memory(memory_size); } +#endif static int32_t hp_sram_init(void) { @@ -269,10 +274,12 @@ static int32_t hp_sram_init(void) #else +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size) { return 0; } +#endif static uint32_t hp_sram_init(void) { @@ -340,7 +347,9 @@ void boot_master_core(void) /* parse manifest and copy modules */ parse_manifest(); +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED hp_sram_power_off_unused_banks(get_fw_size_in_use()); +#endif #endif /* now call SOF entry */ __start(); From d3537db80744e98d30ea26c4e791e52ef8c0a5ae Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:40:33 +0200 Subject: [PATCH 06/15] cavs: fix shim register location on 1.8 and above Shim register location on cAVS 1.5 is different than on 1.8 and up, fix it. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/include/soc.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/xtensa/intel_adsp/common/include/soc.h index 0cfbf0815c63f7..4fc9b6c7df0d12 100644 --- a/soc/xtensa/intel_adsp/common/include/soc.h +++ b/soc/xtensa/intel_adsp/common/include/soc.h @@ -7,6 +7,8 @@ #include #include +#include + #include #include @@ -61,10 +63,14 @@ #define SSP_MN_DIV_BASE(x) \ (0x00078D00 + ((x) * SSP_MN_DIV_SIZE)) -#define PDM_BASE 0x00010000 +#define PDM_BASE DMIC_BASE /* SOC DSP SHIM Registers */ +#if CAVS_VERSION == CAVS_VERSION_1_5 #define SOC_DSP_SHIM_REG_BASE 0x00001000 +#else +#define SOC_DSP_SHIM_REG_BASE 0x00071f00 +#endif /* SOC DSP SHIM Register - Clock Control */ #define SOC_CLKCTL_REQ_AUDIO_PLL_CLK BIT(31) From 23798c6ca01bedfbbfcc62d86077d0f5832a2634 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:43:29 +0200 Subject: [PATCH 07/15] xtensa: IPM is only required if SMP is enabled A configuration with CONFIG_MP_NUM_CPUS > 1 and CONFIG_IPM_CAVS_IDC not defined is valid if COMFIG_SMP is disabled. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/soc_mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c index 5c0b811a7ee48c..f56c05f95d2897 100644 --- a/soc/xtensa/intel_adsp/common/soc_mp.c +++ b/soc/xtensa/intel_adsp/common/soc_mp.c @@ -25,7 +25,7 @@ LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL); #include #include -#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC) +#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC) && defined(CONFIG_SMP) #error Need to enable the IPM driver for multiprocessing #endif From 098b2a2add9ffcfbf10797245020c65903458d58 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:47:48 +0200 Subject: [PATCH 08/15] cavs: (cosmetic) clean up and simplification of intc_cavs.c 1. don't use "inline" in .c, let the compiler decide 2. remove superfluous parentheses 3. simplify a function by directly returning the result of a boolean operation Signed-off-by: Guennadi Liakhovetski --- drivers/interrupt_controller/intc_cavs.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c index 38331e43ae3c33..3afe1f70d66c66 100644 --- a/drivers/interrupt_controller/intc_cavs.c +++ b/drivers/interrupt_controller/intc_cavs.c @@ -67,7 +67,7 @@ static void cavs_ictl_isr(const struct device *port) config->isr_table_offset); } -static inline void cavs_ictl_irq_enable(const struct device *dev, +static void cavs_ictl_irq_enable(const struct device *dev, unsigned int irq) { struct cavs_ictl_runtime *context = dev->data; @@ -75,10 +75,10 @@ static inline void cavs_ictl_irq_enable(const struct device *dev, volatile struct cavs_registers * const regs = (struct cavs_registers *)context->base_addr; - regs->enable_il = (1 << irq); + regs->enable_il = 1 << irq; } -static inline void cavs_ictl_irq_disable(const struct device *dev, +static void cavs_ictl_irq_disable(const struct device *dev, unsigned int irq) { struct cavs_ictl_runtime *context = dev->data; @@ -86,10 +86,10 @@ static inline void cavs_ictl_irq_disable(const struct device *dev, volatile struct cavs_registers * const regs = (struct cavs_registers *)context->base_addr; - regs->disable_il = (1 << irq); + regs->disable_il = 1 << irq; } -static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev) +static unsigned int cavs_ictl_irq_get_state(const struct device *dev) { struct cavs_ictl_runtime *context = dev->data; @@ -100,11 +100,7 @@ static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev) * corresponding interrupts are disabled. This function * returns 0 only if ALL the interrupts are disabled. */ - if (regs->disable_state_il == 0xFFFFFFFF) { - return 0; - } - - return 1; + return regs->disable_state_il != 0xFFFFFFFF; } static int cavs_ictl_irq_get_line_state(const struct device *dev, From 952cf124f8075a5462a20e079ac824cf3d997362 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 16:08:57 +0100 Subject: [PATCH 09/15] cavs_v18, v20, v25: calculate trace base address correctly RAM window layout differs between cAVS versions. Fix apparent copy-paste definition blocks to match cAVS 1.8, 2.0 and 2.5. Signed-off-by: Guennadi Liakhovetski --- .../intel_adsp/cavs_v18/include/soc/memory.h | 37 ++++++++-------- .../intel_adsp/cavs_v20/include/soc/memory.h | 42 ++++++++++--------- .../intel_adsp/cavs_v25/include/soc/memory.h | 41 +++++++++--------- 3 files changed, 63 insertions(+), 57 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index faa3f876bae55a..612ae6198f1c0b 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -176,15 +176,22 @@ /* HP SRAM windows */ -/* window 3 */ -#define SRAM_TRACE_BASE 0xbe000000 -#define SRAM_TRACE_SIZE 0x2000 +/* window 0 */ +#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) +#define SRAM_SW_REG_SIZE 0x1000 -#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE -#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE +#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) +#define SRAM_OUTBOX_SIZE 0x1000 + +#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE +#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) + +/* window 1 */ +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x2000 /* window 2 */ -#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) #define SRAM_DEBUG_SIZE 0x800 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) @@ -193,20 +200,12 @@ #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) #define SRAM_STREAM_SIZE 0x1000 -/* window 1 */ -#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) -#define SRAM_INBOX_SIZE 0x2000 - -/* window 0 */ -#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) -#define SRAM_SW_REG_SIZE 0x1000 - -#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) -#define SRAM_OUTBOX_SIZE 0x1000 - -#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE -#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) +/* window 3 */ +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x2000 +#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE +#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE #define SOF_TEXT_START 0xbe010400 diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 0f96fa22922bd0..7a35852a6b3aa1 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -176,15 +176,23 @@ /* HP SRAM windows */ -/* window 3 */ -#define SRAM_TRACE_BASE 0xbe000000 -#define SRAM_TRACE_SIZE 0x2000 +/* HP SRAM windows */ +/* window 0 */ +#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) +#define SRAM_SW_REG_SIZE 0x1000 -#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE -#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE +#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) +#define SRAM_OUTBOX_SIZE 0x1000 + +#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE +#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) + +/* window 1 */ +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x2000 /* window 2 */ -#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) #define SRAM_DEBUG_SIZE 0x800 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) @@ -193,20 +201,16 @@ #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) #define SRAM_STREAM_SIZE 0x1000 -/* window 1 */ -#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) -#define SRAM_INBOX_SIZE 0x2000 - -/* window 0 */ -#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) -#define SRAM_SW_REG_SIZE 0x1000 - -#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) -#define SRAM_OUTBOX_SIZE 0x1000 - -#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE -#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) +/* window 3 */ +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#if CONFIG_TRACE +#define SRAM_TRACE_SIZE 0x2000 +#else +#define SRAM_TRACE_SIZE 0x0 +#endif +#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE +#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE #define SOF_TEXT_START 0xbe010400 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 35dd0fbdfc83f7..cd365bf539f7f3 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -176,15 +176,22 @@ /* HP SRAM windows */ -/* window 3 */ -#define SRAM_TRACE_BASE 0xbe000000 -#define SRAM_TRACE_SIZE 0x2000 +/* window 0 */ +#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) +#define SRAM_SW_REG_SIZE 0x1000 + +#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) +#define SRAM_OUTBOX_SIZE 0x1000 -#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE -#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE +#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE +#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) + +/* window 1 */ +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x2000 /* window 2 */ -#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) #define SRAM_DEBUG_SIZE 0x800 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) @@ -193,20 +200,16 @@ #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) #define SRAM_STREAM_SIZE 0x1000 -/* window 1 */ -#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) -#define SRAM_INBOX_SIZE 0x2000 - -/* window 0 */ -#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) -#define SRAM_SW_REG_SIZE 0x1000 - -#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) -#define SRAM_OUTBOX_SIZE 0x1000 - -#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE -#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) +/* window 3 */ +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#if CONFIG_TRACE +#define SRAM_TRACE_SIZE 0x2000 +#else +#define SRAM_TRACE_SIZE 0x0 +#endif +#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE +#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE #define SOF_TEXT_START 0xbe010400 From 14abcaf0a1216987aa4e027feaf8579cf9d7bcc1 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 16:30:47 +0100 Subject: [PATCH 10/15] cavs_v25: switch over to Tigerlake H configuration Tigerlake H has less RAM and fewer cores. Both should be supported, selectable at the board level. For now use the H configuration as more readily available for testing. Signed-off-by: Guennadi Liakhovetski --- dts/xtensa/intel/intel_cavs25.dtsi | 2 +- samples/audio/sof/boards/intel_adsp_cavs25.conf | 3 ++- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 5 ++--- soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/dts/xtensa/intel/intel_cavs25.dtsi b/dts/xtensa/intel/intel_cavs25.dtsi index c5ca9fd0b0ac73..632163164060a8 100644 --- a/dts/xtensa/intel/intel_cavs25.dtsi +++ b/dts/xtensa/intel/intel_cavs25.dtsi @@ -41,7 +41,7 @@ sram0: memory@be000000 { device_type = "memory"; compatible = "mmio-sram"; - reg = <0xbe000000 DT_SIZE_K(3008)>; + reg = <0xbe000000 DT_SIZE_K(1920)>; }; sram1: memory@be800000 { diff --git a/samples/audio/sof/boards/intel_adsp_cavs25.conf b/samples/audio/sof/boards/intel_adsp_cavs25.conf index 8c5d4e912b5856..7ec23d23729a22 100644 --- a/samples/audio/sof/boards/intel_adsp_cavs25.conf +++ b/samples/audio/sof/boards/intel_adsp_cavs25.conf @@ -3,4 +3,5 @@ CONFIG_INTEL_DMIC=y CONFIG_INTEL_SSP=y CONFIG_INTEL_ALH=y CONFIG_LP_MEMORY_BANKS=1 -CONFIG_HP_MEMORY_BANKS=46 +CONFIG_HP_MEMORY_BANKS=30 +CONFIG_RIMAGE_SIGNING_SCHEMA="tgl-h" diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index cd365bf539f7f3..42b9ca81d5326a 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -97,11 +97,12 @@ /* low power ram where DMA buffers are typically placed */ #define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) #define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) +#define SRAM_BANK_SIZE (64 * 1024) /* bootloader */ #define HP_SRAM_BASE 0xbe000000 -#define HP_SRAM_SIZE (3008 * 1024) +#define HP_SRAM_SIZE (30 * SRAM_BANK_SIZE) #define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE) /* boot loader in IMR */ @@ -224,8 +225,6 @@ /* Host page size */ #define HOST_PAGE_SIZE 4096 -#define SRAM_BANK_SIZE (64 * 1024) - /* LP SRAM */ #define LP_SRAM_BASE 0xBE800000 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h index 9db1670f6b70ba..767c609a2ae08b 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h @@ -19,7 +19,7 @@ #define MAX_CORE_COUNT 4 -#define PLATFORM_HPSRAM_EBB_COUNT 47 +#define PLATFORM_HPSRAM_EBB_COUNT 30 #define EBB_SEGMENT_SIZE 32 From a6c77869071a0f48bc7af4cab6844fded14b91b1 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 16:37:53 +0100 Subject: [PATCH 11/15] cavs_v25: fix copy-pasted definitions shim.h on cAVS 2.5 contains register definitions, copy-pasted from other architectures. Fix them to correct values. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h index 9e1ab07d914482..ad097dce5a00a3 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h @@ -247,11 +247,11 @@ /** \brief LDO Control */ #define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) +#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16) #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) +#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) +#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16)) #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) #define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) #define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) From 96d3cd0c2d8f591a0853a1d70e89c402867ba035 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 16:40:50 +0100 Subject: [PATCH 12/15] cavs: fix invalid expressions CONFIG_BOOTLOADER_MCUBOOT is never defined in cAVS builds, code, built only when that option is enabled, contains invalid expressions. Fix them. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h | 4 ++-- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 4 ++-- soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 4 ++-- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index d852fb80ad5b4a..0cc9ee3dc7d595 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -18,8 +18,8 @@ #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1024) +#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1024) #else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 612ae6198f1c0b..8912515f9ece90 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -15,8 +15,8 @@ #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1024) +#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1024) #else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 7a35852a6b3aa1..00bb2f86190aeb 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -15,8 +15,8 @@ #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1024) +#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1024) #else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 42b9ca81d5326a..7a611ce22b8687 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -15,8 +15,8 @@ #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1024) +#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1024) #else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) From e3fdce639b1aca2028c9326b6b70872480720d78 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 17:22:36 +0100 Subject: [PATCH 13/15] cavs: fix LSPGISTS and LSPGCTL access On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a different shim register range, they cannot be accessed, using the usual SHIM_BASE offset. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h | 1 + soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h | 4 ---- soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h | 4 ---- soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h | 4 ---- soc/xtensa/intel_adsp/common/bootloader/boot_loader.c | 4 ++-- 5 files changed, 3 insertions(+), 14 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h index 2338f91afce3af..bf36b8bd564b2f 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h @@ -204,6 +204,7 @@ #define SHIM_HSPGCTL 0x80 #define SHIM_LSPGCTL 0x84 #define SHIM_SPSREQ 0xa0 +#define LSPGCTL (SHIM_BASE + SHIM_LSPGCTL) #define SHIM_SPSREQ_RVNNP BIT(0) diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h index 98787f14c461fa..6ea6641868d60a 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h @@ -236,10 +236,6 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_LSPGCTL 0x50 -#define SHIM_LSPGISTS 0x58 - - #define SHIM_L2_MECS (SHIM_BASE + 0xd0) /** \brief LDO Control */ diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h index 19bf8952410e78..42f603b201e8b1 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h @@ -230,10 +230,6 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_LSPGCTL 0x50 -#define SHIM_LSPGISTS 0x58 - - #define SHIM_L2_MECS (SHIM_BASE + 0xd0) /** \brief LDO Control */ diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h index ad097dce5a00a3..ba44d95ecc85c0 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h @@ -239,10 +239,6 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_LSPGCTL 0x50 -#define SHIM_LSPGISTS 0x58 - - #define SHIM_L2_MECS (SHIM_BASE + 0xd0) /** \brief LDO Control */ diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index 3319db295eef86..3a8eda3da05120 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -301,8 +301,8 @@ static int32_t lp_sram_init(void) /* add some delay before writing power registers */ idelay(delay_count); - lspgctl_value = shim_read(SHIM_LSPGISTS); - shim_write(SHIM_LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0)); + lspgctl_value = io_reg_read(LSPGISTS); + io_reg_write(LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0)); /* add some delay before checking the status */ idelay(delay_count); From 692d3dd798f5b2c903fce166c76ff9ec0bd74fea Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 5 Jan 2021 12:07:38 +0100 Subject: [PATCH 14/15] cavs: (cosmetic) remove redundant LPRAM_* macros LPRAM_BASE and LPRAM_SIZE are duplicates of LP_SRAM_BASE and LP_SRAM_SIZE respectively. Remove them and use LP_SRAM_* consistently everywhere. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h | 8 ++++---- soc/xtensa/intel_adsp/cavs_v15/linker.ld | 8 ++++---- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 8 ++++---- soc/xtensa/intel_adsp/cavs_v18/linker.ld | 8 ++++---- soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 8 ++++---- soc/xtensa/intel_adsp/cavs_v20/linker.ld | 8 ++++---- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 10 +++------- soc/xtensa/intel_adsp/cavs_v25/linker.ld | 9 +++++---- 8 files changed, 32 insertions(+), 35 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 0cc9ee3dc7d595..2f2264cdf9a8aa 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -97,10 +97,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) - /* bootloader */ #define HP_SRAM_BASE 0xbe000000 @@ -220,4 +216,8 @@ /* Host page size */ #define HOST_PAGE_SIZE 4096 +/* low power ram where DMA buffers are typically placed */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) + #endif /* __INC_MEMORY_H */ diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index 8586340c06faf4..dd27ba428c3a46 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -25,7 +25,7 @@ OUTPUT_ARCH(xtensa) PROVIDE(__memctl_default = 0x00000000); PROVIDE(_MemErrorHandler = 0x00000000); -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram /* DSP RAM regions (all of them) are mapped twice on the DSP: once in * a 512MB region from 0x80000000-0x9fffffff and again from @@ -123,8 +123,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -509,7 +509,7 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 8912515f9ece90..496822296403a8 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -94,10 +94,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) - /* bootloader */ #define HP_SRAM_BASE 0xbe000000 @@ -222,4 +218,8 @@ #define SRAM_BANK_SIZE (64 * 1024) +/* low power ram where DMA buffers are typically placed */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) + #endif /* __INC_MEMORY_H */ diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld index e0141e203fca70..e62de5c0edcdde 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld @@ -27,7 +27,7 @@ PROVIDE(_MemErrorHandler = 0x00000000); #define RAMABLE_REGION ram :ram_phdr #define ROMABLE_REGION ram :ram_phdr -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram MEMORY { @@ -103,8 +103,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -474,7 +474,7 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 00bb2f86190aeb..a7209791ff26e9 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -94,10 +94,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) - /* bootloader */ #define HP_SRAM_BASE 0xbe000000 @@ -226,4 +222,8 @@ #define SRAM_BANK_SIZE (64 * 1024) +/* low power ram where DMA buffers are typically placed */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) + #endif /* __INC_MEMORY_H */ diff --git a/soc/xtensa/intel_adsp/cavs_v20/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld index b144b121039b71..d7152189115f45 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v20/linker.ld @@ -27,7 +27,7 @@ PROVIDE(_MemErrorHandler = 0x00000000); #define RAMABLE_REGION ram :ram_phdr #define ROMABLE_REGION ram :ram_phdr -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram MEMORY { @@ -103,8 +103,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -473,7 +473,7 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 7a611ce22b8687..898d0b51c21e9e 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -94,9 +94,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) #define SRAM_BANK_SIZE (64 * 1024) /* bootloader */ @@ -225,10 +222,9 @@ /* Host page size */ #define HOST_PAGE_SIZE 4096 -/* LP SRAM */ -#define LP_SRAM_BASE 0xBE800000 - -#define LP_SRAM_SIZE (0x10000 * 2) +/* low power RAM where DMA buffers are typically placed, used by linker.ld */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) /* alternate reset vector */ #define LP_SRAM_ALT_RESET_VEC_BASE LP_SRAM_BASE diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld index a5c7cb46ea5b85..dd47c82d8e9cb1 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld @@ -27,7 +27,7 @@ PROVIDE(_MemErrorHandler = 0x00000000); #define RAMABLE_REGION ram :ram_phdr #define ROMABLE_REGION ram :ram_phdr -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram MEMORY { @@ -103,8 +103,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -542,7 +542,8 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION + _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } From 623d235bb9ebe7f64e495c8dff50aeb277eda59b Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 5 Jan 2021 12:19:43 +0100 Subject: [PATCH 15/15] bootloader: use ceiling_fraction() instead of open-coding it Use the existing ceiling_fraction() function instead of open- coding it. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/bootloader/boot_loader.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index 3a8eda3da05120..13919c093062c9 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -252,9 +252,7 @@ static uint32_t hp_sram_power_on_memory(uint32_t memory_size) /* calculate total number of used SRAM banks (EBB) * to power up only necessary banks */ - ebb_in_use = (!(memory_size % SRAM_BANK_SIZE)) ? - (memory_size / SRAM_BANK_SIZE) : - (memory_size / SRAM_BANK_SIZE) + 1; + ebb_in_use = ceiling_fraction(memory_size, SRAM_BANK_SIZE); return hp_sram_pm_banks(ebb_in_use); }