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Optimize the ALU + operand forwarding #4

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mbitsnbites opened this issue Jul 31, 2018 · 3 comments
Open

Optimize the ALU + operand forwarding #4

mbitsnbites opened this issue Jul 31, 2018 · 3 comments

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@mbitsnbites
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There are too many levels of MUX:ing going on, especially around the compare logic.

@mbitsnbites
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One alternative would be to turn certain ALU operations into 2-cycle operations, which would reduce the ALU MUX preasure. This could include seldom used instructions (such as CLZ) and packed operations (.b, .h).

@mbitsnbites
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Another possible optimization is to refactor the operand forwarding logic to reduce the number of MUX levels, if possible. E.g. don't select the value to forward in the operand forwarding entity, but in the final source selection MUX in the register_fetch entity.

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Investigate Mr. Gisselquist's result indexing optimization: http://zipcpu.com/zipcpu/2019/03/28/return-decoding.html

@mbitsnbites mbitsnbites changed the title vhdl: Optimize the ALU A1: Optimize the ALU May 20, 2019
@mbitsnbites mbitsnbites transferred this issue from mrisc32/mrisc32 Nov 29, 2019
@mbitsnbites mbitsnbites changed the title A1: Optimize the ALU Optimize the ALU + operand forwarding Jan 4, 2021
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