rcc.cpp.in

/*
 * Copyright (c) 2009, Martin Rosekeit
 * Copyright (c) 2009-2012, Fabian Greif
 * Copyright (c) 2011, Georgi Grinshpun
 * Copyright (c) 2012, 2016, Sascha Schade
 * Copyright (c) 2012, 2014-2019, 2021, Niklas Hauser
 * Copyright (c) 2013-2014, Kevin Läufer
 * Copyright (c) 2018, 2021, Christopher Durand
 *
 * This file is part of the modm project.
 *
 * This Source Code Form is subject to the terms of the Mozilla Public
 * License, v. 2.0. If a copy of the MPL was not distributed with this
 * file, You can obtain one at http://mozilla.org/MPL/2.0/.
 */
// ----------------------------------------------------------------------------

#include "rcc.hpp"

// CMSIS Core compliance
constinit uint32_t modm_fastdata SystemCoreClock(modm::platform::Rcc::BootFrequency);
modm_weak void SystemCoreClockUpdate() { /* Nothing to update */ }

namespace modm::platform
{
constinit uint16_t modm_fastdata delay_fcpu_MHz(computeDelayMhz(Rcc::BootFrequency));
constinit uint16_t modm_fastdata delay_ns_per_loop(computeDelayNsPerLoop(Rcc::BootFrequency));

// ----------------------------------------------------------------------------
%% if target.family == "f0"
bool
Rcc::enableInternalClockMHz14(uint32_t waitCycles)
{
	bool retval;
	RCC->CR2 |= RCC_CR2_HSI14ON;
	while (not (retval = (RCC->CR2 & RCC_CR2_HSI14RDY)) and --waitCycles)
		;
	return retval;
}
%% endif

%% if hsi48
bool
Rcc::enableInternalClockMHz48(uint32_t waitCycles)
{
	bool retval;
	RCC->{{hsi48_cr}} |= RCC_{{hsi48_cr}}_HSI48ON;
	while (not (retval = (RCC->{{hsi48_cr}} & RCC_{{hsi48_cr}}_HSI48RDY)) and --waitCycles)
		;
	return retval;
}
%% endif

bool
Rcc::enableInternalClock(uint32_t waitCycles)
{
	bool retval;
	RCC->CR |= RCC_CR_HSION;
	while (not (retval = (RCC->CR & RCC_CR_HSIRDY)) and --waitCycles)
		;
	return retval;
}

%% if target.family in ["l0", "l1", "l4", "l5"]
bool
Rcc::enableMultiSpeedInternalClock(MsiFrequency msi_frequency, uint32_t waitCycles)
{
	bool retval;
%% if target.family in ["l0", "l1"]
	RCC->ICSCR = (RCC->ICSCR & ~RCC_ICSCR_MSIRANGE) | static_cast<uint32_t>(msi_frequency);
	RCC->CR |= RCC_CR_MSION;
	while (not (retval = (RCC->CR & RCC_CR_MSIRDY)) and --waitCycles)
%% else
	RCC->CR = (RCC->CR & ~RCC_CR_MSIRANGE) | static_cast<uint32_t>(msi_frequency) | RCC_CR_MSIRGSEL | RCC_CR_MSION;
	while (not (retval = (RCC->CR & RCC_CR_MSIRDY)) and --waitCycles)
%% endif
		;
	return retval;
}
%% endif

%% if target.family in ["u5"]
// MSIxRANGE can be modified when MSIx is OFF (MSISON = 0) or when MSIx is
// ready (MSIxRDY = 1). MSIxRANGE must NOT be modified when MSIx is ON
// and NOT ready (MSIxON = 1 and MSIxRDY = 0)
%% for msi in ["S", "K"]
bool
Rcc::enableMultiSpeedInternalClock{{msi}}(MsiFrequency msi_frequency, uint32_t waitCycles)
{
	bool retval;
	uint32_t waitCycles_ = waitCycles;
	while ((not (retval = (((RCC->CR & RCC_CR_MSI{{msi}}ON) == 0) || ((RCC->CR & RCC_CR_MSI{{msi}}RDY) == RCC_CR_MSI{{msi}}RDY)))) || --waitCycles_)
		;
	if (!retval)
		return false;
	RCC->ICSCR1 = (RCC->ICSCR1 & ~RCC_ICSCR1_MSI{{msi}}RANGE_Msk) | RCC_ICSCR1_MSIRGSEL | (static_cast<uint32_t>(msi_frequency) << RCC_ICSCR1_MSI{{msi}}RANGE_Pos);
	RCC->CR |= RCC_CR_MSI{{msi}}ON;
	waitCycles_ = waitCycles;
	while (not (retval = (RCC->CR & RCC_CR_MSI{{msi}}RDY)) and --waitCycles)
		;
	return retval;
}

%% endfor
%% endif

bool
Rcc::enableExternalClock(uint32_t waitCycles)
{
	bool retval;
	RCC->CR |= RCC_CR_HSEBYP | RCC_CR_HSEON;
	while (not (retval = (RCC->CR & RCC_CR_HSERDY)) and --waitCycles)
		;
	return retval;
}

bool
Rcc::enableExternalCrystal(uint32_t waitCycles)
{
	bool retval;
	RCC->CR = (RCC->CR & ~RCC_CR_HSEBYP) | RCC_CR_HSEON;
	while (not (retval = (RCC->CR & RCC_CR_HSERDY)) and --waitCycles)
		;
	return retval;
}


%% set lsi_cr="CSR2" if target.family in ["c0"] else "BDCR" if target.family in ["u5"] else "CSR"
bool
Rcc::enableLowSpeedInternalClock(uint32_t waitCycles)
{
	bool retval;
	RCC->{{lsi_cr}} |= RCC_{{lsi_cr}}_LSION;
	while (not (retval = (RCC->{{lsi_cr}} & RCC_{{lsi_cr}}_LSIRDY)) and --waitCycles)
		;
	return retval;
}

bool
Rcc::enableLowSpeedExternalClock(uint32_t waitCycles)
{
	bool retval;
	RCC->{{bdcr}} |= RCC_{{bdcr}}_LSEBYP | RCC_{{bdcr}}_LSEON;
	while (not (retval = (RCC->{{bdcr}} & RCC_{{bdcr}}_LSERDY)) and --waitCycles)
		;
	return retval;
}

bool
Rcc::enableLowSpeedExternalCrystal(uint32_t waitCycles)
{
	bool retval;
	RCC->{{bdcr}} = (RCC->{{bdcr}} & ~RCC_{{bdcr}}_LSEBYP) | RCC_{{bdcr}}_LSEON;
	while (not (retval = (RCC->{{bdcr}} & RCC_{{bdcr}}_LSERDY)) and --waitCycles)
		;
	return retval;
}

%% for id in pll_ids
bool
Rcc::enablePll{{id}}(PllSource source, const PllFactors& pllFactors, uint32_t waitCycles)
{
%% if target.family == "h7"
	// set the PLL{{id}} source and DIVM{{id}} prescaler
	uint32_t tmp = RCC->PLLCKSELR & ~(RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM{{id}});
	tmp |= uint32_t(source);
	tmp |= (uint32_t(pllFactors.pllM) << RCC_PLLCKSELR_DIVM{{id}}_Pos) & RCC_PLLCKSELR_DIVM{{id}};
	RCC->PLLCKSELR = tmp;

	// Set Frequency Range
	tmp = RCC->PLLCFGR & ~(RCC_PLLCFGR_PLL{{id}}RGE | RCC_PLLCFGR_PLL{{id}}VCOSEL);
	tmp |= uint32_t(pllFactors.range) << RCC_PLLCFGR_PLL{{id}}RGE_Pos;
	if (pllFactors.range == PllInputRange::MHz1_2) tmp |= RCC_PLLCFGR_PLL{{id}}VCOSEL;
	RCC->PLLCFGR = tmp;

	// Using integer mode
	RCC->PLL{{id}}FRACR = pllFactors.pllFrac;
	// Set PLL Dividers
	RCC->PLL{{id}}DIVR =
			((uint32_t(pllFactors.pllR - 1u) << RCC_PLL{{id}}DIVR_R{{id}}_Pos) & RCC_PLL{{id}}DIVR_R{{id}}) |
			((uint32_t(pllFactors.pllQ - 1u) << RCC_PLL{{id}}DIVR_Q{{id}}_Pos) & RCC_PLL{{id}}DIVR_Q{{id}}) |
			((uint32_t(pllFactors.pllP - 1u) << RCC_PLL{{id}}DIVR_P{{id}}_Pos) & RCC_PLL{{id}}DIVR_P{{id}}) |
			((uint32_t(pllFactors.pllN - 1u) << RCC_PLL{{id}}DIVR_N{{id}}_Pos) & RCC_PLL{{id}}DIVR_N{{id}});

	// enable pll
	RCC->CR |= RCC_CR_PLL{{id}}ON;

	while (not (tmp = (RCC->CR & RCC_CR_PLL{{id}}RDY)) and --waitCycles)
		;

	return tmp;
%% elif target.family in ["u5"]
	RCC->PLL{{id}}CFGR = 0;

	%% if id == "1"
	// Voltage scaling is selected through the VOS[1:0] bits in the PWR_VOSR
	// register. The EPOD (embedded power distribution) booster must be enabled
	// and ready before increasing the system clock frequency above 55 MHz in
	// range 1 and range 2.
	//
	// Configure the PLL1MBOOST in RCC->PLL1CFGR to generate a booster clock
	// frequency between 4 and 16 MHz
	RCC->PLL1CFGR = (RCC->PLL1CFGR & ~RCC_PLL1CFGR_PLL1MBOOST_Msk) | uint32_t(pllFactors.epodPrescaler);
	%% endif

	// Select clock source
	RCC->PLL{{id}}CFGR |= (uint32_t(source) & RCC_PLL{{id}}CFGR_PLL{{id}}SRC_Msk);

	// Init pre-divider
	RCC->PLL{{id}}CFGR |= ((uint32_t(pllFactors.pllM - 1u) << RCC_PLL{{id}}CFGR_PLL{{id}}M_Pos) & RCC_PLL{{id}}CFGR_PLL{{id}}M_Msk);

	// Set PLL fractional value
	RCC->PLL{{id}}FRACR = pllFactors.pllFrac << RCC_PLL{{id}}FRACR_PLL{{id}}FRACN_Pos;

	// PLL config
	RCC->PLL{{id}}CFGR |= (uint32_t(pllFactors.range) << RCC_PLL{{id}}CFGR_PLL{{id}}RGE_Pos) |
		((pllFactors.pllFrac > 0) ? RCC_PLL{{id}}CFGR_PLL{{id}}FRACEN : 0) |
		RCC_PLL{{id}}CFGR_PLL{{id}}PEN |
		RCC_PLL{{id}}CFGR_PLL{{id}}QEN |
		RCC_PLL{{id}}CFGR_PLL{{id}}REN;

	// Set PLL Dividers
	RCC->PLL{{id}}DIVR =
			((uint32_t(pllFactors.pllR - 1u) << RCC_PLL{{id}}DIVR_PLL{{id}}R_Pos) & RCC_PLL{{id}}DIVR_PLL{{id}}R_Msk) |
			((uint32_t(pllFactors.pllQ - 1u) << RCC_PLL{{id}}DIVR_PLL{{id}}Q_Pos) & RCC_PLL{{id}}DIVR_PLL{{id}}Q_Msk) |
			((uint32_t(pllFactors.pllP - 1u) << RCC_PLL{{id}}DIVR_PLL{{id}}P_Pos) & RCC_PLL{{id}}DIVR_PLL{{id}}P_Msk) |
			((uint32_t(pllFactors.pllN - 1u) << RCC_PLL{{id}}DIVR_PLL{{id}}N_Pos) & RCC_PLL{{id}}DIVR_PLL{{id}}N_Msk);

	// enable pll
	RCC->CR |= RCC_CR_PLL{{id}}ON;

	uint32_t tmp;
	while (not (tmp = (RCC->CR & RCC_CR_PLL{{id}}RDY)) and --waitCycles)
		;

	return tmp;
%% elif target.family in ["f2", "f4", "f7"]
	// Read reserved values and clear all other values
	uint32_t tmp = RCC->PLLCFGR & ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM
			| RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP);

	// PLLSRC source for pll and for plli2s
	tmp |= static_cast<uint32_t>(source);

	// PLLM (0) = factor is user defined VCO input frequency must be configured to 2MHz
	tmp |= ((uint32_t) pllFactors.pllM) & RCC_PLLCFGR_PLLM;

	// PLLN (6) = factor is user defined
	tmp |= (((uint32_t) pllFactors.pllN) << RCC_PLLCFGR_PLLN_Pos) & RCC_PLLCFGR_PLLN;

	// PLLP (16) divider for CPU frequency; (00: PLLP = 2, 01: PLLP = 4, etc.)
	tmp |= (((uint32_t) (pllFactors.pllP / 2) - 1) << RCC_PLLCFGR_PLLP_Pos) & RCC_PLLCFGR_PLLP;

	// PLLQ (24) divider for USB frequency; (0-15)
	if (pllFactors.pllQ != 0xff) {
		tmp &= ~RCC_PLLCFGR_PLLQ;
		tmp |= (((uint32_t) pllFactors.pllQ) << RCC_PLLCFGR_PLLQ_Pos) & RCC_PLLCFGR_PLLQ;
	}

	RCC->PLLCFGR = tmp;

	// enable pll
	RCC->CR |= RCC_CR_PLLON;

	while (not (tmp = (RCC->CR & RCC_CR_PLLRDY)) and --waitCycles)
		;

	return tmp;
%% elif target.family in ["g0", "l4", "l5", "g4"]
	// Read reserved values and clear all other values
	uint32_t tmp = RCC->PLLCFGR & ~(
			RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |
%% if pll_p
			// RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLP |
%% endif
			RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLR);

	// PLLSRC source for pll
	tmp |= static_cast<uint32_t>(source);

	// PLLM factor is user defined VCO input frequency must be configured between 4MHz and 16Mhz
	tmp |= (uint32_t(pllFactors.pllM - 1) << RCC_PLLCFGR_PLLM_Pos) & RCC_PLLCFGR_PLLM;

	// PLLN factor is user defined: between 64 and 344 MHz
	tmp |= (uint32_t(pllFactors.pllN) << RCC_PLLCFGR_PLLN_Pos) & RCC_PLLCFGR_PLLN;

	// PLLR divider for CPU frequency
%% if target.family in ["g0"]
	tmp |= ((uint32_t(pllFactors.pllR) - 1) << RCC_PLLCFGR_PLLR_Pos) & RCC_PLLCFGR_PLLR;
	// PLLP divider for P frequency
	// tmp |= ((uint32_t(pllP) - 1) << RCC_PLLCFGR_PLLP_Pos) & RCC_PLLCFGR_PLLP;
%% else
	tmp |= ((uint32_t(pllFactors.pllR / 2) - 1) << RCC_PLLCFGR_PLLR_Pos) & RCC_PLLCFGR_PLLR;
	// PLLQ (21) divider for USB frequency; (00: PLLQ = 2, 01: PLLQ = 4, etc.)
	if (pllFactors.pllQ != 0xff) {
		tmp &= ~RCC_PLLCFGR_PLLQ;
		tmp |= (((uint32_t) (pllFactors.pllQ / 2) - 1) << RCC_PLLCFGR_PLLQ_Pos) & RCC_PLLCFGR_PLLQ;
		// enable pll USB clock output
		tmp |= RCC_PLLCFGR_PLLQEN;
	}
%% endif

	// enable pll CPU clock output
	tmp |= RCC_PLLCFGR_PLLREN;

	RCC->PLLCFGR = tmp;

	// enable pll
	RCC->CR |= RCC_CR_PLLON;

	while (not (tmp = (RCC->CR & RCC_CR_PLLRDY)) and --waitCycles)
		;

	return tmp;
%% elif target.family in ["l0", "l1"]
%% if target.family == "l0"
	setHsiPredivider4Enabled(pllFactors.enableHsiPrediv4);
%% endif

	uint32_t tmp = RCC->CFGR & ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV);
	// PLLSRC source for pll
	tmp |= static_cast<uint32_t>(source);
	// Pll multiplication factor
	tmp |= static_cast<uint32_t>(pllFactors.pllMul);
	tmp |= (static_cast<uint32_t>(pllFactors.pllDiv - 1) << RCC_CFGR_PLLDIV_Pos) & RCC_CFGR_PLLDIV;
	RCC->CFGR = tmp;

	// enable pll
	RCC->CR |= RCC_CR_PLLON;
	while (not (tmp = (RCC->CR & RCC_CR_PLLRDY)) and --waitCycles)
		;

	return tmp;
%% else
%% set pullmul = 'RCC_CFGR_PLLMULL' if target.family == "f1" else 'RCC_CFGR_PLLMUL'
	// Read reserved values and clear all other values
%% if usbprescaler
	uint32_t tmp = RCC->CFGR & ~(RCC_CFGR_USBPRE | {{pullmul}} | RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE);

	// Divide Output for USB Clock by 1.5?
	tmp |= static_cast<uint32_t>(pllFactors.usbPrediv);
%% else
	uint32_t tmp = RCC->CFGR & ~({{pullmul}} | RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE);
%% endif

	// PLLSRC source for pll
	tmp |= static_cast<uint32_t>(source);

	// Pll multiplication factor
	tmp |= (static_cast<uint32_t>(pllFactors.pllMul - 2) << 18) & {{pullmul}};

%% if pll_hse_prediv2
	if(pllFactors.enableHsePllPrediv2) {
		tmp |= RCC_CFGR_PLLXTPRE;
	}
%% endif

	RCC->CFGR = tmp;

%% if pllprediv
	%% set mask = 'RCC_CFGR2_PREDIV1' if target.family == "f1" else 'RCC_CFGR2_PREDIV'
	// HSE PREDIV division factor
	RCC->CFGR2 = (RCC->CFGR2 & ~({{mask}})) | (uint32_t(pllFactors.pllPrediv - 1) & {{mask}});
%% endif
%% if pllprediv2
	RCC->CFGR2 = (RCC->CFGR2 & ~(RCC_CFGR2_PREDIV2)) | ((uint32_t(pllFactors.pllPrediv2 - 1) << 4) & RCC_CFGR2_PREDIV2);
%% endif
	// enable pll
	RCC->CR |= RCC_CR_PLLON;

	while (not (tmp = (RCC->CR & RCC_CR_PLLRDY)) and --waitCycles)
		;

	return tmp;
%% endif
}

bool
Rcc::disablePll{{id}}(uint32_t waitCycles)
{
	RCC->CR &= ~RCC_CR_PLL{{id}}ON;
	while ((RCC->CR & RCC_CR_PLL{{id}}RDY) and --waitCycles)
		;
	return waitCycles > 0;
}

%% endfor

%% if pllsai_p_usb
bool
Rcc::enablePllSai(const PllSaiFactors& pllFactors, uint32_t waitCycles)
{
	// Read reserved values and clear all other values
	uint32_t tmp = RCC->PLLSAICFGR & ~(
%% if target.family == "f4" and target.name in "46"
		RCC_PLLSAICFGR_PLLSAIM |
%% endif
		RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP);

%% if target.family == "f4" and target.name in "46"
	// PLLSAIM (0) = factor is user defined VCO input frequency must be configured to 2MHz
	tmp |= ((uint32_t) pllFactors.pllSaiM) & RCC_PLLSAICFGR_PLLSAIM;
%% endif

	// PLLSAIN (6) = factor is user defined
	tmp |= (((uint32_t) pllFactors.pllSaiN) << RCC_PLLSAICFGR_PLLSAIN_Pos) & RCC_PLLSAICFGR_PLLSAIN;

	// PLLSAIP (16) divider for CLK48 frequency; (00: PLLP = 2, 01: PLLP = 4, etc.)
	tmp |= (((uint32_t) (pllFactors.pllSaiP / 2) - 1) << RCC_PLLCFGR_PLLP_Pos) & RCC_PLLCFGR_PLLP;

	RCC->PLLSAICFGR = tmp;

	// enable pll
	RCC->CR |= RCC_CR_PLLSAION;

	while (not (tmp = (RCC->CR & RCC_CR_PLLSAIRDY)) and --waitCycles)
		;

	return tmp;
}

bool
Rcc::disablePllSai(uint32_t waitCycles)
{
	RCC->CR &= ~RCC_CR_PLLSAION;
	while ((RCC->CR & RCC_CR_PLLSAIRDY) and --waitCycles)
		;
	return waitCycles > 0;
}
%% endif

%% if overdrive
bool
Rcc::enableOverdriveMode(uint32_t waitCycles)
{
%% set suffix = '1' if target["family"] == "f7" else ''

	PWR->CR{{suffix}} |= PWR_CR{{suffix}}_ODEN;
	auto waitCounter = waitCycles;
	while (!(PWR->CSR{{suffix}} & PWR_CSR{{suffix}}_ODRDY))
		if (--waitCounter == 0) return false;

	PWR->CR{{suffix}} |= PWR_CR{{suffix}}_ODSWEN;
	while (!(PWR->CSR{{suffix}} & PWR_CSR{{suffix}}_ODSWRDY))
		if (--waitCycles == 0) return false;

	return true;
}
%% endif

%% if has_r1mode
bool
Rcc::setVoltageScaling(VoltageScaling voltage, uint32_t waitCycles)
{
	const auto currentSetting = PWR->CR1 & PWR_CR1_VOS;
	if (voltage == VoltageScaling::Boost) {
		PWR->CR5 &= ~PWR_CR5_R1MODE;
	} else {
		PWR->CR5 |= PWR_CR5_R1MODE;
	}
	if (voltage != VoltageScaling::Scale2) {
		if(static_cast<VoltageScaling>(currentSetting) == VoltageScaling::Scale2) {
			PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS) | PWR_CR1_VOS_0;
			while (PWR->SR2 & PWR_SR2_VOSF)
				if (--waitCycles == 0) return false;
		}
	} else {
		PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS) | PWR_CR1_VOS_1;
	}

	return true;
}
%% elif target.family == "l5"
bool
Rcc::setVoltageScaling(VoltageScaling voltage, uint32_t waitCycles)
{
	// TODO: check if low power mode is active and reject changing range if active
	// Implemented according to STHAL HAL_PWREx_ControlVoltageScaling()
	// TODO: The reference manual describes a more complicated procedure
	// but the CubeHal also does not implement that ...
	const auto currentSetting = PWR->CR1 & PWR_CR1_VOS;
	if (voltage == static_cast<VoltageScaling>(currentSetting)) {
		return true;
	}
	PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS) | uint32_t(voltage);
	while (PWR->SR2 & PWR_SR2_VOSF)
		if (--waitCycles == 0) return false;
	return true;
}
%% elif target.family in ["u5"]
bool
Rcc::setVoltageScaling(VoltageScaling voltage, uint32_t waitCycles)
{
	const auto currentSetting = PWR->VOSR & PWR_VOSR_VOS_Msk;
	if (voltage == static_cast<VoltageScaling>(currentSetting)) {
		return true;
	}
	const bool sysclkOver55MHz = (voltage == VoltageScaling::Range1) || (voltage == VoltageScaling::Range2);
	const uint32_t boosten = sysclkOver55MHz ? PWR_VOSR_BOOSTEN : 0;
	PWR->VOSR = (PWR->VOSR & ~PWR_VOSR_VOS_Msk) | uint32_t(voltage) | boosten;

	const uint32_t rdy = sysclkOver55MHz ? (PWR_VOSR_BOOSTEN | PWR_VOSR_VOSRDY) : PWR_VOSR_VOSRDY;
	while (PWR->VOSR & rdy)
		if (--waitCycles == 0) return false;
	return true;
}
%% elif target.family == "h7"
bool
Rcc::setVoltageScaling(VoltageScaling voltage, uint32_t waitCycles)
{
	auto waitCounter = waitCycles;
	// wait for power supply to be ready to set VOS setting
	while(!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
		if (--waitCounter == 0) return false;

%% if vos0_overdrive
	if (voltage == VoltageScaling::Scale0) {
		// set VOS1
		waitCounter = waitCycles;
		PWR->{{d3}}CR = static_cast<uint32_t>(VoltageScaling::Scale1);
		while (!(PWR->{{d3}}CR & PWR_{{d3}}CR_VOSRDY))
			if (--waitCounter == 0) return false;

		// set overdrive
		SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN;
		while (!(PWR->{{d3}}CR & PWR_{{d3}}CR_VOSRDY))
			if (--waitCycles == 0) return false;
	} else {
		// disable overdrive
		SYSCFG->PWRCR &= ~SYSCFG_PWRCR_ODEN;
		// set voltage scale
		PWR->{{d3}}CR = static_cast<uint32_t>(voltage);
		while (!(PWR->{{d3}}CR & PWR_{{d3}}CR_VOSRDY))
			if (--waitCycles == 0) return false;
	}
%% else
	// set voltage scale
	PWR->{{d3}}CR = static_cast<uint32_t>(voltage);
	waitCounter = waitCycles;
	while (!(PWR->{{d3}}CR & PWR_{{d3}}CR_VOSRDY))
		if (--waitCycles == 0) return false;
%% endif

	return true;
}

bool
Rcc::configurePowerSource(PowerSource source, uint32_t waitCycles)
{
	constexpr auto mask = PWR_CR3_LDOEN |
%% if has_smps
		PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN |
%% endif
		PWR_CR3_BYPASS;

	PWR->CR3 = (PWR->CR3 & ~mask) | static_cast<uint32_t>(source);

	// wait for power supply to be ready to set VOS setting
	while(!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
		if (--waitCycles == 0) return false;

	return true;
}
%% endif

%% if target["family"] == "l0"
bool
Rcc::setHsiPredivider4Enabled(bool divideBy4, uint32_t waitCycles)
{
	const uint32_t enableFlag = divideBy4 ? RCC_CR_HSIDIVEN : 0;
	RCC->CR = (RCC->CR & ~RCC_CR_HSIDIVEN) | enableFlag;
	while (isHsiPredivider4Active() != divideBy4)
		if (waitCycles-- == 0) return false;

	return true;
}
%% endif

%% set sysclksrcf_cfgr="CFGR1" if target.family in ["u5"] else "CFGR"
bool
Rcc::enableSystemClock(SystemClockSource src, uint32_t waitCycles)
{
	RCC->{{sysclksrcf_cfgr}} = (RCC->{{sysclksrcf_cfgr}} & ~RCC_{{sysclksrcf_cfgr}}_SW) | uint32_t(src);

	// Wait till the main PLL is used as system clock source
	src = SystemClockSource(uint32_t(src) << RCC_{{sysclksrcf_cfgr}}_SWS_Pos);
	while ((RCC->{{sysclksrcf_cfgr}} & RCC_{{sysclksrcf_cfgr}}_SWS) != uint32_t(src))
		if (not --waitCycles) return false;

	return true;
}

%% if target.family in ["g4", "l5"]
bool
Rcc::setCanPrescaler(CanPrescaler prescaler)
{
	enable<Peripheral::Fdcan1>();

	// FDCAN1 must enter initialization mode to configure common divider.
	// This will stop operation of FDCAN1.
	// The setting only takes effect after resetting INIT in FDCAN1_CCCR
	if (FDCAN_CONFIG->CKDIV != uint32_t(prescaler)) {
		FDCAN1->CCCR = FDCAN_CCCR_INIT;

		// Wait until the initialization mode is entered
		int deadlockPreventer = 10'000; // max ~10ms
		while (((FDCAN1->CCCR & FDCAN_CCCR_INIT) == 0) and (deadlockPreventer-- > 0)) {
			modm::delay_us(1);
		}

		if(deadlockPreventer == 0) {
			return false;
		}

		FDCAN1->CCCR |= FDCAN_CCCR_CCE;
		FDCAN_CONFIG->CKDIV = uint32_t(prescaler);

		FDCAN1->CCCR &= ~FDCAN_CCCR_INIT;
	}
	return true;
}
%% endif

}