From 90b9b7d3dd30fd5f9e65b08f3b6315c13824e2d8 Mon Sep 17 00:00:00 2001 From: Carlos Pereira Atencio Date: Tue, 16 Apr 2024 14:36:45 +0100 Subject: [PATCH] codal_port/ticks_cpu: Check CoreDebug DEMCR trace enable bit. The DAPLink controlled reset button performs a target reset via SWD, and the CoreDebug trace enable bit seems to be cleared while the DWT->CTRL cycle count enable bit is not. https://github.com/microbit-foundation/micropython-microbit-v2/issues/179#issuecomment-2059077656 --- src/codal_port/mphalport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/codal_port/mphalport.h b/src/codal_port/mphalport.h index cf5f546..a4d5405 100644 --- a/src/codal_port/mphalport.h +++ b/src/codal_port/mphalport.h @@ -46,7 +46,7 @@ static inline void enable_irq(uint32_t state) { } static inline mp_uint_t mp_hal_ticks_cpu(void) { - if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) { + if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) || !(CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)) { CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; DWT->CYCCNT = 0; DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;