PLIC support needed?

[AnttiLukats]

Full PLIC support is not required by the rules/zephyr, PLIC support can be disable in the zephyr option, then machine timer would be used as os tick source. You need to provide then two 64 memory mapped registers for the machine timer as specified in privileged ISM document.

[Dolu1990]

The current riscv port of Zephyr work with two 32 bits counters (mtime + mtimecmp), the spec also say that the upper 32 bits can be emulated.
Also the current zephyr implementation of the MTIME reading seem broken :
zephyrproject-rtos/zephyr#10788

[AnttiLukats]

I can not find in the spec that the 64 bit MEMORY mapped counters can be implemented as 32 bit ones. Sure it says the CSR can be 32 bit, and upper bits emulated but nothing about their memory mapped regs.

broken thing in zephyr is not funny of course..

[Dolu1990]

@AnttiLukats
I was reffering to RISC-V User-Level ISA V2.2 page 24 (as you spotted it)

For a low-end implementation, the upper 32
bits of each counter can be implemented using software counters incremented by a trap handler
triggered by over
ow of the lower 32 bits. The sample code described above shows how the full
64-bit width value can be safely read using the individual 32-bit instructions.
In some applications, it is important to be able to read multiple counters at

So it would require to have a custom riscv_machine_timer driver :)

[AnttiLukats]

it would be easier to just implement it so that the zephyr interrupt and timer drivers work without modifications.

if you want to know how much is needed to pass ALL requirements you can look at

engine-V-simulator

This simulator was written from scratch to implement the absolute minimum requirements for the contest. It currently passed all tests 100% clean except misaligned load/store tests.

[Dolu1990]

@AnttiLukats You mean implementing the PLIC ?

[AnttiLukats]

engine-v simulator runs zephyr, no PLIC minimal machine timer interrupt support, you disable PLIC in zephyr and use riscv machine timer.