-
Notifications
You must be signed in to change notification settings - Fork 62
/
ops.d
5203 lines (4321 loc) · 137 KB
/
ops.d
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*****************************************************************************
*
* Higgs JavaScript Virtual Machine
*
* This file is part of the Higgs project. The project is distributed at:
* https://github.com/maximecb/Higgs
*
* Copyright (c) 2012-2015, Maxime Chevalier-Boisvert. All rights reserved.
*
* This software is licensed under the following license (Modified BSD
* License):
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
module jit.ops;
import core.memory;
import core.stdc.string;
import core.stdc.math;
import std.stdio;
import std.string;
import std.array;
import std.stdint;
import std.conv;
import std.algorithm;
import std.traits;
import std.datetime;
import options;
import stats;
import parser.parser;
import ir.ir;
import ir.ops;
import ir.ast;
import ir.livevars;
import ir.analysis;
import runtime.vm;
import runtime.layout;
import runtime.object;
import runtime.string;
import runtime.gc;
import jit.codeblock;
import jit.x86;
import jit.moves;
import jit.util;
import jit.jit;
import core.sys.posix.dlfcn;
/// Instruction code generation function
alias GenFn = void function(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
);
/// Get an argument by index
void gen_get_arg(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
// Get the first argument slot
auto argSlot = instr.block.fun.argcVal.outSlot + 1;
// Get the argument index
auto idxOpnd = ctx.getWordOpnd(as, instr, 0, 32, scrRegs[0].opnd(32), false);
assert (idxOpnd.isGPR);
auto idxReg32 = idxOpnd.reg.opnd(32);
auto idxReg64 = idxOpnd.reg.opnd(64);
// Get the output operand
auto opndOut = ctx.getOutOpnd(as, instr, 64);
// Zero-extend the index to 64-bit
as.mov(idxReg32, idxReg32);
// Copy the word value
auto wordSlot = X86Opnd(64, wspReg, 8 * argSlot, 8, idxReg64.reg);
as.genMove(opndOut, wordSlot, scrRegs[1].opnd(64));
// Copy the type value
auto typeSlot = X86Opnd(8, tspReg, 1 * argSlot, 1, idxReg64.reg);
as.mov(scrRegs[1].opnd(8), typeSlot);
ctx.setOutTag(as, instr, scrRegs[1].reg(8));
}
void gen_make_value(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
// Move the word value into the output word,
// allow reusing the input register
auto wordOpnd = ctx.getWordOpnd(as, instr, 0, 64, scrRegs[0].opnd(64), true);
auto outOpnd = ctx.getOutOpnd(as, instr, 64, true);
if (outOpnd != wordOpnd)
as.mov(outOpnd, wordOpnd);
// Get the type value from the second operand
auto tagOpnd = ctx.getWordOpnd(as, instr, 1, 8, scrRegs[0].opnd(8));
assert (tagOpnd.isGPR);
ctx.setOutTag(as, instr, tagOpnd.reg);
}
void gen_get_word(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
auto wordOpnd = ctx.getWordOpnd(as, instr, 0, 64, scrRegs[0].opnd(64), true);
auto outOpnd = ctx.getOutOpnd(as, instr, 64);
as.mov(outOpnd, wordOpnd);
ctx.setOutTag(as, instr, Tag.INT64);
}
void gen_get_tag(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
auto tagOpnd = ctx.getTagOpnd(as, instr, 0, scrRegs[0].opnd(8), true);
auto outOpnd = ctx.getOutOpnd(as, instr, 32);
if (tagOpnd.isImm)
{
as.mov(outOpnd, tagOpnd);
}
else if (outOpnd.isGPR)
{
as.movzx(outOpnd, tagOpnd);
}
else
{
as.movzx(scrRegs[0].opnd(32), tagOpnd);
as.mov(outOpnd, scrRegs[0].opnd(32));
}
ctx.setOutTag(as, instr, Tag.INT32);
}
void gen_i32_to_f64(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 32, scrRegs[0].opnd(32), false, false);
assert (opnd0.isReg);
auto outOpnd = ctx.getOutOpnd(as, instr, 64);
// Sign-extend the 32-bit integer to 64-bit
as.movsx(scrRegs[1].opnd(64), opnd0);
as.cvtsi2sd(X86Opnd(XMM0), opnd0);
as.movq(outOpnd, X86Opnd(XMM0));
ctx.setOutTag(as, instr, Tag.FLOAT64);
}
void gen_f64_to_i32(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 64, X86Opnd(XMM0), false, false);
auto outOpnd = ctx.getOutOpnd(as, instr, 32);
if (!opnd0.isXMM)
as.movq(X86Opnd(XMM0), opnd0);
// Cast to int64 and truncate to int32 (to match JS semantics)
as.cvttsd2si(scrRegs[0].opnd(64), X86Opnd(XMM0));
as.mov(outOpnd, scrRegs[0].opnd(32));
ctx.setOutTag(as, instr, Tag.INT32);
}
void RMMOp(string op, size_t numBits, Tag tag)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
// Should be mem or reg
auto opnd0 = ctx.getWordOpnd(
as,
instr,
0,
numBits,
scrRegs[0].opnd(numBits),
true
);
// May be reg or immediate
auto opnd1 = ctx.getWordOpnd(
as,
instr,
1,
numBits,
scrRegs[1].opnd(numBits),
true
);
// Get type information about the first argument
auto arg0Type = ctx.getType(instr.getArg(0));
// Allow reusing an input register for the output,
// except for subtraction which is not commutative
auto opndOut = ctx.getOutOpnd(as, instr, numBits, op != "sub");
if (op == "imul")
{
// imul does not support memory operands as output
auto outReg = opndOut.isReg? opndOut:scrRegs[2].opnd(numBits);
// TODO: handle this at the peephole level, assert not happening here
if (opnd0.isImm && opnd1.isImm)
{
as.mov(outReg, opnd0);
as.mov(scrRegs[0].opnd(numBits), opnd1);
as.imul(outReg, scrRegs[0].opnd(numBits));
}
else if (opnd0.isImm)
{
as.imul(outReg, opnd1, opnd0);
}
else if (opnd1.isImm)
{
as.imul(outReg, opnd0, opnd1);
}
else if (opnd0 == opndOut)
{
as.imul(outReg, opnd1);
}
else if (opnd1 == opndOut)
{
as.imul(outReg, opnd0);
}
else
{
as.mov(outReg, opnd0);
as.imul(outReg, opnd1);
}
if (outReg != opndOut)
as.mov(opndOut, outReg);
}
else
{
if (opnd0 == opndOut)
{
mixin(format("as.%s(opndOut, opnd1);", op));
}
else if (opnd1 == opndOut)
{
// Note: the operation has to be commutative for this to work
mixin(format("as.%s(opndOut, opnd0);", op));
}
else
{
// Neither input operand is the output
as.mov(opndOut, opnd0);
mixin(format("as.%s(opndOut, opnd1);", op));
}
}
// Set the output type tag
ctx.setOutTag(as, instr, tag);
// If the instruction has no exception/overflow target, stop
if (instr.getTarget(0) is null)
return;
// If this is an add operation
static if (op == "add")
{
// If we are adding something to 1 and there can be no overflow
auto arg1Cst = cast(IRConst)instr.getArg(1);
if (arg1Cst && arg1Cst.isInt32 &&
arg1Cst.int32Val == 1 &&
arg0Type.subMax)
{
// Jump directly to the successor block
//writeln("BBV ovf elim: ", instr.block.fun.getName);
return gen_jump(ver, ctx, instr, as);
}
}
// Increment the count of overflow checks
if (opts.stats)
{
as.pushfq();
as.incStatCnt(&stats.numOvfChecks, scrRegs[0]);
as.popfq();
}
auto branchNO = getBranchEdge(instr.getTarget(0), ctx, false);
auto branchOV = getBranchEdge(instr.getTarget(1), ctx, false);
// Generate the branch code
ver.genBranch(
as,
branchNO,
branchOV,
delegate void(
CodeBlock as,
BlockVersion block,
CodeFragment target0,
CodeFragment target1,
BranchShape shape
)
{
final switch (shape)
{
case BranchShape.NEXT0:
jo32Ref(as, vm, block, target1, 1);
break;
case BranchShape.NEXT1:
jno32Ref(as, vm, block, target0, 0);
break;
case BranchShape.DEFAULT:
jo32Ref(as, vm, block, target1, 1);
jmp32Ref(as, vm, block, target0, 0);
}
}
);
}
alias gen_add_i32 = RMMOp!("add", 32, Tag.INT32);
alias gen_sub_i32 = RMMOp!("sub", 32, Tag.INT32);
alias gen_mul_i32 = RMMOp!("imul", 32, Tag.INT32);
alias gen_and_i32 = RMMOp!("and", 32, Tag.INT32);
alias gen_or_i32 = RMMOp!("or", 32, Tag.INT32);
alias gen_xor_i32 = RMMOp!("xor", 32, Tag.INT32);
alias gen_add_i32_ovf = RMMOp!("add", 32, Tag.INT32);
alias gen_sub_i32_ovf = RMMOp!("sub", 32, Tag.INT32);
alias gen_mul_i32_ovf = RMMOp!("imul", 32, Tag.INT32);
void gen_add_ptr_i32(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
// Should be mem or reg
auto opnd0 = ctx.getWordOpnd(
as,
instr,
0,
64,
scrRegs[0].opnd(64),
false
);
// May be reg or immediate
auto opnd1 = ctx.getWordOpnd(
as,
instr,
1,
32,
scrRegs[1].opnd(32),
true
);
auto opndOut = ctx.getOutOpnd(as, instr, 64);
// Zero-extend the integer operand to 64-bits
as.mov(scrRegs[1].opnd(32), opnd1);
as.mov(opndOut, opnd0);
as.add(opndOut, scrRegs[1].opnd);
// Set the output type tag
ctx.setOutTag(as, instr, Tag.RAWPTR);
}
void divOp(string op)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
// Spill EAX and EDX (used by the idiv instruction)
ctx.spillReg(as, EAX);
ctx.spillReg(as, EDX);
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 32, X86Opnd.NONE, true, false);
auto opnd1 = ctx.getWordOpnd(as, instr, 1, 32, scrRegs[1].opnd(32), false, false);
auto outOpnd = ctx.getOutOpnd(as, instr, 32);
as.mov(EAX.opnd, opnd0);
if (opnd1 == EDX.opnd(32))
{
assert (scrRegs[1] != RAX && scrRegs[1] != RDX);
as.mov(scrRegs[1].opnd(32), opnd1);
opnd1 = scrRegs[1].opnd(32);
}
// Sign-extend EAX into EDX:EAX
as.cdq();
// Signed divide/quotient EDX:EAX by r/m32
as.idiv(opnd1);
// Store the divisor or remainder into the output operand
static if (op == "div")
as.mov(outOpnd, EAX.opnd);
else if (op == "mod")
as.mov(outOpnd, EDX.opnd);
else
assert (false);
// Set the output type tag
ctx.setOutTag(as, instr, Tag.INT32);
}
alias gen_div_i32 = divOp!("div");
alias gen_mod_i32 = divOp!("mod");
void gen_not_i32(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 32, scrRegs[0].opnd(32), true);
auto outOpnd = ctx.getOutOpnd(as, instr, 32);
as.mov(outOpnd, opnd0);
as.not(outOpnd);
// Set the output type tag
ctx.setOutTag(as, instr, Tag.INT32);
}
void ShiftOp(string op)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
//auto startPos = as.getWritePos;
// TODO: need way to allow reusing arg 0 reg only, but not arg1
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 32, X86Opnd.NONE, true);
auto opnd1 = ctx.getWordOpnd(as, instr, 1, 8, X86Opnd.NONE, true);
auto outOpnd = ctx.getOutOpnd(as, instr, 32, false);
auto shiftOpnd = outOpnd;
// If the shift amount is a constant
if (opnd1.isImm)
{
// Truncate the shift amount bits
opnd1 = X86Opnd(opnd1.imm.imm & 31);
// If opnd0 is not shiftOpnd (or is a constant)
if (opnd0 != shiftOpnd)
as.mov(shiftOpnd, opnd0);
}
else
{
// Spill the CL register if needed
if (opnd1 != CL.opnd(8) && outOpnd != CL.opnd(32))
ctx.spillReg(as, CL);
// If outOpnd is CL, the shift amount register
if (outOpnd == CL.opnd(32))
{
// Use a different register for the shiftee
shiftOpnd = scrRegs[0].opnd(32);
}
// If opnd0 is not shiftOpnd (or is a constant)
if (opnd0 != shiftOpnd)
as.mov(shiftOpnd, opnd0);
// If the shift amount is not already in CL
if (opnd1 != CL.opnd(8))
{
as.mov(CL.opnd, opnd1);
opnd1 = CL.opnd;
}
}
static if (op == "sal")
as.sal(shiftOpnd, opnd1);
else if (op == "sar")
as.sar(shiftOpnd, opnd1);
else if (op == "shr")
as.shr(shiftOpnd, opnd1);
else
assert (false);
if (shiftOpnd != outOpnd)
as.mov(outOpnd, shiftOpnd);
// Set the output type tag
ctx.setOutTag(as, instr, Tag.INT32);
}
alias gen_lsft_i32 = ShiftOp!("sal");
alias gen_rsft_i32 = ShiftOp!("sar");
alias gen_ursft_i32 = ShiftOp!("shr");
void FPOp(string op)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
X86Opnd opnd0 = ctx.getWordOpnd(as, instr, 0, 64, X86Opnd(XMM0));
X86Opnd opnd1 = ctx.getWordOpnd(as, instr, 1, 64, X86Opnd(XMM1));
auto outOpnd = ctx.getOutOpnd(as, instr, 64);
assert (opnd0.isReg && opnd1.isReg);
if (opnd0.isGPR)
as.movq(X86Opnd(XMM0), opnd0);
if (opnd1.isGPR)
as.movq(X86Opnd(XMM1), opnd1);
static if (op == "add")
as.addsd(X86Opnd(XMM0), X86Opnd(XMM1));
else if (op == "sub")
as.subsd(X86Opnd(XMM0), X86Opnd(XMM1));
else if (op == "mul")
as.mulsd(X86Opnd(XMM0), X86Opnd(XMM1));
else if (op == "div")
as.divsd(X86Opnd(XMM0), X86Opnd(XMM1));
else
assert (false);
as.movq(outOpnd, X86Opnd(XMM0));
// Set the output type tag
ctx.setOutTag(as, instr, Tag.FLOAT64);
}
alias gen_add_f64 = FPOp!("add");
alias gen_sub_f64 = FPOp!("sub");
alias gen_mul_f64 = FPOp!("mul");
alias gen_div_f64 = FPOp!("div");
void HostFPOp(alias cFPFun, size_t arity = 1)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
assert (arity is 1 || arity is 2);
// Spill the values live before the instruction
ctx.spillValues(
as,
delegate bool(LiveInfo liveInfo, IRDstValue value)
{
return liveInfo.liveBefore(value, instr);
}
);
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 64, X86Opnd.NONE, false, false);
as.movq(X86Opnd(XMM0), opnd0);
static if (arity is 2)
{
auto opnd1 = ctx.getWordOpnd(as, instr, 1, 64, X86Opnd.NONE, false, false);
as.movq(X86Opnd(XMM1), opnd1);
}
auto outOpnd = ctx.getOutOpnd(as, instr, 64);
// Call the host function
// Note: we do not save the JIT regs because they are callee-saved
as.ptr(scrRegs[0], &cFPFun);
as.call(scrRegs[0]);
// Store the output value into the output operand
as.movq(outOpnd, X86Opnd(XMM0));
ctx.setOutTag(as, instr, Tag.FLOAT64);
}
alias gen_sin_f64 = HostFPOp!(core.stdc.math.sin);
alias gen_cos_f64 = HostFPOp!(core.stdc.math.cos);
alias gen_sqrt_f64 = HostFPOp!(core.stdc.math.sqrt);
alias gen_ceil_f64 = HostFPOp!(core.stdc.math.ceil);
alias gen_floor_f64 = HostFPOp!(core.stdc.math.floor);
alias gen_log_f64 = HostFPOp!(core.stdc.math.log);
alias gen_exp_f64 = HostFPOp!(core.stdc.math.exp);
alias gen_pow_f64 = HostFPOp!(core.stdc.math.pow, 2);
alias gen_mod_f64 = HostFPOp!(core.stdc.math.fmod, 2);
void FPToStr(string fmt)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
extern (C) static refptr toStrFn(IRInstr curInstr, double f)
{
vm.setCurInstr(curInstr);
auto str = getString(vm, to!wstring(format(fmt, f)));
vm.setCurInstr(null);
return str;
}
// Spill the values that are live before this instruction
ctx.spillLiveBefore(as, instr);
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 64, X86Opnd.NONE, false, false);
auto outOpnd = ctx.getOutOpnd(as, instr, 64);
as.saveJITRegs();
// Call the host function
as.ptr(cargRegs[0], instr);
as.movq(cfpArgRegs[0].opnd, opnd0);
as.ptr(scrRegs[0], &toStrFn);
as.call(scrRegs[0]);
as.loadJITRegs();
// Store the output value into the output operand
as.mov(outOpnd, cretReg.opnd);
ctx.setOutTag(as, instr, Tag.STRING);
}
alias gen_f64_to_str = FPToStr!("%G");
alias gen_f64_to_str_lng = FPToStr!(format("%%.%sf", float64.dig));
void LoadOp(size_t memSize, bool signed, Tag tag)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
// The pointer operand must be a register
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 64, scrRegs[0].opnd(64));
assert (opnd0.isGPR);
// The offset operand may be a register or an immediate
auto opnd1 = ctx.getWordOpnd(as, instr, 1, 32, scrRegs[1].opnd(32), true);
auto outOpnd = ctx.getOutOpnd(as, instr, (memSize < 64)? 32:64);
// Create the memory operand
X86Opnd memOpnd;
if (opnd1.isImm)
{
memOpnd = X86Opnd(memSize, opnd0.reg, cast(int32_t)opnd1.imm.imm);
}
else if (opnd1.isGPR)
{
// Zero-extend the offset from 32 to 64 bits
as.mov(opnd1, opnd1);
memOpnd = X86Opnd(memSize, opnd0.reg, 0, 1, opnd1.reg.reg(64));
}
else
{
assert (false, "invalid offset operand");
}
// If the output operand is a memory location
if (outOpnd.isMem)
{
auto scrReg = scrRegs[2].opnd((memSize < 64)? 32:64);
// Load to a scratch register first
static if (memSize < 32)
{
static if (signed)
as.movsx(scrReg, memOpnd);
else
as.movzx(scrReg, memOpnd);
}
else
{
as.mov(scrReg, memOpnd);
}
// Move the scratch register to the output
as.mov(outOpnd, scrReg);
}
else
{
// Load to the output register directly
static if (memSize == 8 || memSize == 16)
{
static if (signed)
as.movsx(outOpnd, memOpnd);
else
as.movzx(outOpnd, memOpnd);
}
else
{
as.mov(outOpnd, memOpnd);
}
}
// Set the output type tag
ctx.setOutTag(as, instr, tag);
}
alias gen_load_u8 = LoadOp!(8, false, Tag.INT32);
alias gen_load_u16 = LoadOp!(16, false, Tag.INT32);
alias gen_load_u32 = LoadOp!(32, false, Tag.INT32);
alias gen_load_u64 = LoadOp!(64, false, Tag.INT64);
alias gen_load_i8 = LoadOp!(8, true , Tag.INT32);
alias gen_load_i16 = LoadOp!(16, true , Tag.INT32);
alias gen_load_i32 = LoadOp!(32, true , Tag.INT32);
alias gen_load_i64 = LoadOp!(64, true , Tag.INT64);
alias gen_load_f64 = LoadOp!(64, false, Tag.FLOAT64);
alias gen_load_refptr = LoadOp!(64, false, Tag.REFPTR);
alias gen_load_string = LoadOp!(64, false, Tag.STRING);
alias gen_load_rawptr = LoadOp!(64, false, Tag.RAWPTR);
alias gen_load_funptr = LoadOp!(64, false, Tag.FUNPTR);
void StoreOp(size_t memSize, Tag tag)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
// The pointer operand must be a register
auto opnd0 = ctx.getWordOpnd(as, instr, 0, 64, scrRegs[0].opnd(64));
assert (opnd0.isGPR);
// The offset operand may be a register or an immediate
auto opnd1 = ctx.getWordOpnd(as, instr, 1, 32, scrRegs[1].opnd(32), true);
// The value operand may be a register or an immediate
auto opnd2 = ctx.getWordOpnd(as, instr, 2, memSize, scrRegs[2].opnd(memSize), true);
// Create the memory operand
X86Opnd memOpnd;
if (opnd1.isImm)
{
memOpnd = X86Opnd(memSize, opnd0.reg, cast(int32_t)opnd1.imm.imm);
}
else if (opnd1.isGPR)
{
// Zero-extend the offset from 32 to 64 bits
as.mov(opnd1, opnd1);
memOpnd = X86Opnd(memSize, opnd0.reg, 0, 1, opnd1.reg.reg(64));
}
else
{
assert (false, "invalid offset operand");
}
// Store the value into the memory location
as.mov(memOpnd, opnd2);
}
alias gen_store_u8 = StoreOp!(8, Tag.INT32);
alias gen_store_u16 = StoreOp!(16, Tag.INT32);
alias gen_store_u32 = StoreOp!(32, Tag.INT32);
alias gen_store_u64 = StoreOp!(64, Tag.INT64);
alias gen_store_i8 = StoreOp!(8, Tag.INT32);
alias gen_store_i16 = StoreOp!(16, Tag.INT32);
alias gen_store_i32 = StoreOp!(32, Tag.INT32);
alias gen_store_i64 = StoreOp!(64, Tag.INT64);
alias gen_store_f64 = StoreOp!(64, Tag.FLOAT64);
alias gen_store_refptr = StoreOp!(64, Tag.REFPTR);
alias gen_store_rawptr = StoreOp!(64, Tag.RAWPTR);
alias gen_store_funptr = StoreOp!(64, Tag.FUNPTR);
void TagTestOp(Tag tag)(
BlockVersion ver,
CodeGenCtx ctx,
IRInstr instr,
CodeBlock as
)
{
//as.printStr(instr.toString);
//as.printStr(" " ~ instr.block.fun.getName);
if (opts.save_tag_tests)
regTagTest(ver);
// Get an operand for the value's type
auto tagOpnd = ctx.getTagOpnd(as, instr, 0, X86Opnd.NONE, true);
auto testResult = TestResult.UNKNOWN;
// If the type is available through basic block versioning
if (tagOpnd.isImm)
{
// Get the known type
auto knownTag = cast(Tag)tagOpnd.imm.imm;
// Get the test result
testResult = (tag is knownTag)? TestResult.TRUE:TestResult.FALSE;
}
// If the type analysis was run
if (opts.load_tag_tests)
{
// Get the type analysis result for this value at this instruction
auto anaResult = getTagTestResult(ver);
//writeln("result: ", anaResult);
// If the analysis yields a known result
if (anaResult != TestResult.UNKNOWN)
{
// If there is a contradiction between versioning and the analysis
if (testResult != TestResult.UNKNOWN && anaResult != testResult)
{
writeln(
"type analysis contradiction for:\n",
instr, "\n",
"analysis result:\n",
anaResult, "\n",
"versioning result:\n",
testResult, "\n",
"in:\n",
instr.block,
"\n"
);
assert (false);
}
testResult = anaResult;
}
}
// If the type test result is known
if (testResult != TestResult.UNKNOWN)
{
// Get the boolean value of the test
auto boolResult = testResult is TestResult.TRUE;
// If this instruction has many uses or is not followed by an if
if (instr.hasManyUses || ifUseNext(instr) is false)
{
auto outOpnd = ctx.getOutOpnd(as, instr, 64);
auto outVal = boolResult? TRUE:FALSE;
as.mov(outOpnd, X86Opnd(outVal.word.int8Val));
ctx.setOutTag(as, instr, Tag.BOOL);
}
// If our only use is an immediately following if_true
if (ifUseNext(instr) is true)
{
// Get the branch edge
auto targetIdx = boolResult? 0:1;
auto branch = getBranchEdge(instr.next.getTarget(targetIdx), ctx, true);
// Generate the branch code
ver.genBranch(
as,
branch,
null,
delegate void(
CodeBlock as,
BlockVersion block,
CodeFragment target0,
CodeFragment target1,
BranchShape shape
)
{
final switch (shape)
{
case BranchShape.NEXT0:
break;
case BranchShape.NEXT1:
case BranchShape.DEFAULT:
jmp32Ref(as, vm, block, target0, 0);
}
}
);
}
return;
}
// Increment the stat counter for this specific kind of type test
as.incStatCnt(stats.getTagTestCtr(instr.opcode.mnem), scrRegs[1]);
if (opts.log_tag_tests)
{
writeln(instr);
writeln(" ", instr.block.fun.getName);
}
// Compare against the tested type
as.cmp(tagOpnd, X86Opnd(tag));
// If this instruction has many uses or is not followed by an if_true
if (instr.hasManyUses || ifUseNext(instr) is false)
{
// We must have a register for the output (so we can use cmov)
auto outOpnd = ctx.getOutOpnd(as, instr, 64);
X86Opnd outReg = outOpnd.isReg? outOpnd.reg.opnd(32):scrRegs[0].opnd(32);
// Generate a boolean output value
as.mov(outReg, X86Opnd(FALSE.word.int8Val));
as.mov(scrRegs[1].opnd(32), X86Opnd(TRUE.word.int8Val));
as.cmove(outReg.reg, scrRegs[1].opnd(32));
// If the output register is not the output operand
if (outReg != outOpnd)
as.mov(outOpnd, outReg.reg.opnd(64));
// Set the output type tag
ctx.setOutTag(as, instr, Tag.BOOL);
}
// If our only use is an immediately following if_true
if (ifUseNext(instr) is true)
{
// If the argument is not a constant, add type information
// about the argument's type along the true branch
CodeGenCtx trueCtx = ctx;
if (auto dstArg = cast(IRDstValue)instr.getArg(0))
{
trueCtx = new CodeGenCtx(trueCtx);
trueCtx.setTag(dstArg, tag);
}
// Get branch edges for the true and false branches
auto branchT = getBranchEdge(instr.next.getTarget(0), trueCtx, false);
auto branchF = getBranchEdge(instr.next.getTarget(1), ctx, false);
// Generate the branch code
ver.genBranch(
as,
branchT,
branchF,
delegate void(
CodeBlock as,
BlockVersion block,
CodeFragment target0,
CodeFragment target1,
BranchShape shape
)
{
final switch (shape)
{
case BranchShape.NEXT0:
jne32Ref(as, vm, block, target1, 1);
break;