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[dv/chip] some required changes to chip_if and chip tb
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Signed-off-by: Eitan Shapira <[email protected]>
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@eshapira
eshapira committed Jul 8, 2024
1 parent 2e5d86c commit 4a9afc9
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Showing 2 changed files with 58 additions and 30 deletions.
28 changes: 19 additions & 9 deletions hw/top_earlgrey/dv/env/chip_if.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -707,13 +707,25 @@ interface chip_if;
// sensor_ctrl alert ack output.
task static trigger_sensor_ctrl_wkup();
`uvm_info(MsgId, "forcing sensor_ctrl ast_alert_i[0] to 1", UVM_MEDIUM)
`ifdef GATE_LEVEL
force `SENSOR_CTRL_HIER.ast_alert_i[1:1] = 1'b1;
`else
force `SENSOR_CTRL_HIER.ast_alert_i.alerts[0].p = 1'b1;
`endif
// Release the alert when an ack cycle is done, so wait for ack to rise
// and release when it falls, with a timeout of 20 micro seconds.
`ifdef GATE_LEVEL
`DV_WAIT(`SENSOR_CTRL_HIER.alert_event_p[0:0] == 1'b1, , 20_000_000, "chip_if")
`else
`DV_WAIT(`SENSOR_CTRL_HIER.ast_alert_o.alerts_ack[0].p == 1'b1, , 20_000_000, "chip_if")
`endif
`uvm_info(MsgId, "releasing sensor_ctrl ast_alert_i[0]", UVM_MEDIUM)
@(posedge `SENSOR_CTRL_HIER.clk_i);
`ifdef GATE_LEVEL
release `SENSOR_CTRL_HIER.ast_alert_i[1:1];
`else
release `SENSOR_CTRL_HIER.ast_alert_i.alerts[0].p;
`endif
endtask

// alert_esc_if alert_if[NUM_ALERTS](.clk (`ALERT_HANDLER_HIER.clk_i),
Expand Down Expand Up @@ -1160,12 +1172,9 @@ interface chip_if;
`define _ADC_FSM_STATE_Q(i) \
`ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.fsm_state_q_``i``_

assign adc_ctrl_state = {`ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.fsm_state_q_CDR1_4_
,`ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.fsm_state_q_CDR1_3_
,`ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.fsm_state_q[2]
,`ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.fsm_state_q_CDR1_1_
,`ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.fsm_state_q[0]
};
//RTL has "assign aon_fsm_state_o = fsm_state_q;"
assign adc_ctrl_state = `ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.aon_fsm_state_o;

`undef _ADC_FSM_STATE_Q
`else
assign adc_ctrl_state = `ADC_CTRL_HIER.u_adc_ctrl_core.u_adc_ctrl_fsm.fsm_state_q;
Expand Down Expand Up @@ -1221,9 +1230,10 @@ assign spi_host_1_state = {tb.dut.top_earlgrey.u_spi_host1.u_spi_core.u_fsm.stat
// Signal probe function for `st_q` of HMAC
wire [2:0] hmac_fsm_state;
`ifdef GATE_LEVEL
assign hmac_fsm_state = {`HMAC_HIER.u_hmac.dftopt19
,`HMAC_HIER.u_hmac.dftopt10
,`HMAC_HIER.u_hmac.dftopt1
assign hmac_fsm_state = {
`HMAC_HIER.u_hmac.st_q_reg_2_.Q,
`HMAC_HIER.u_hmac.st_q_reg_1_.Q,
`HMAC_HIER.u_hmac.st_q_reg_0_.Q
};
`else
assign hmac_fsm_state = `HMAC_HIER.u_hmac.st_q;
Expand Down
60 changes: 39 additions & 21 deletions hw/top_earlgrey/dv/tb/tb.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -257,8 +257,13 @@ module tb;

// The gpiodpi module allows the host to directly control gpio when enabled.
gpiodpi u_gpiodpi(
`ifdef GATE_LEVEL
.clk_i(dut.top_earlgrey.u_clkmgr_aon.clocks_o_clk_io_div4_peri),
.rst_ni(dut.top_earlgrey.u_rstmgr_aon.resets_o_rst_lc_io_div4_n_1_),
`else
.clk_i(dut.top_earlgrey.u_clkmgr_aon.clocks_o.clk_io_div4_peri),
.rst_ni(dut.top_earlgrey.u_rstmgr_aon.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
`endif
.active(u_tb_dpi_if.enable_gpiodpi),
.gpio_p2d(gpiodpi_p2d),
.gpio_d2p(gpiodpi_d2p),
Expand Down Expand Up @@ -291,6 +296,7 @@ module tb;
assign gpiodpi_pull_en_d2p[gi_] = 1'b0; \
assign gpiodpi_pull_sel_d2p[gi_] = 1'b0

`ifndef GATE_LEVEL
`ASSIGN_GPIODPI_D2P(0, MioPadIob6);
`ASSIGN_GPIODPI_D2P(1, MioPadIob7);
`ASSIGN_GPIODPI_D2P(2, MioPadIob8);
Expand All @@ -305,6 +311,16 @@ module tb;
`ASSIGN_GPIODPI_D2P(11, MioPadIor11);
`ASSIGN_GPIODPI_D2P(12, MioPadIor12);
`ASSIGN_GPIODPI_D2P(13, MioPadIor13);
// SW straps
`ASSIGN_GPIODPI_D2P(22, MioPadIoc0);
`ASSIGN_GPIODPI_D2P(23, MioPadIoc1);
`ASSIGN_GPIODPI_D2P(24, MioPadIoc2);
// TAP straps
`ASSIGN_GPIODPI_D2P(27, MioPadIoc5);

`ASSIGN_GPIODPI_D2P(30, MioPadIoc8);
`endif

`ASSIGN_UNUSED_GPIODPI_D2P(14);
`ASSIGN_UNUSED_GPIODPI_D2P(15);
`ASSIGN_UNUSED_GPIODPI_D2P(16);
Expand All @@ -313,17 +329,13 @@ module tb;
`ASSIGN_UNUSED_GPIODPI_D2P(19);
`ASSIGN_UNUSED_GPIODPI_D2P(20);
`ASSIGN_UNUSED_GPIODPI_D2P(21);
// SW straps
`ASSIGN_GPIODPI_D2P(22, MioPadIoc0);
`ASSIGN_GPIODPI_D2P(23, MioPadIoc1);
`ASSIGN_GPIODPI_D2P(24, MioPadIoc2);

`ASSIGN_UNUSED_GPIODPI_D2P(25);
`ASSIGN_UNUSED_GPIODPI_D2P(26);
// TAP straps
`ASSIGN_GPIODPI_D2P(27, MioPadIoc5);

`ASSIGN_UNUSED_GPIODPI_D2P(28);
`ASSIGN_UNUSED_GPIODPI_D2P(29);
`ASSIGN_GPIODPI_D2P(30, MioPadIoc8);

`ASSIGN_UNUSED_GPIODPI_D2P(31);

`undef ASSIGN_GPIODPI_D2P
Expand All @@ -337,8 +349,13 @@ module tb;
.BAUD('d1_000_000),
.FREQ('d24_000_000)
) u_uartdpi0(
.clk_i(dut.top_earlgrey.u_clkmgr_aon.clocks_o.clk_io_div4_peri),
.rst_ni(dut.top_earlgrey.u_rstmgr_aon.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
`ifdef GATE_LEVEL
.clk_i(dut.top_earlgrey.u_clkmgr_aon.clocks_o_clk_io_div4_peri),
.rst_ni(dut.top_earlgrey.u_rstmgr_aon.resets_o_rst_lc_io_div4_n_1_),
`else
.clk_i(dut.top_earlgrey.u_clkmgr_aon.clocks_o.clk_io_div4_peri),
.rst_ni(dut.top_earlgrey.u_rstmgr_aon.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
`endif
.active(u_tb_dpi_if.enable_uartdpi),
.tx_o(uartdpi_tx),
.rx_i(uartdpi_rx)
Expand Down Expand Up @@ -684,16 +701,17 @@ module tb;
`include "../autogen/tb__xbar_connect.sv"
`include "../autogen/tb__alert_handler_connect.sv"

// Gatesim initial
`ifdef GATE_LEVEL
initial begin
// unconnected ports
tb.dut.chip_if.disable_mios_x_check = 1'b1;

// Ignore 0 time x
$assertoff();
#5ns;
$asserton();
end
`endif
// Gatesim initial
`ifdef GATE_LEVEL
initial begin
// unconnected ports
tb.dut.chip_if.disable_mios_x_check = 1'b1;

// Ignore 0 time x
$assertoff();
#5ns;
$asserton();
end
`endif

endmodule

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