From ed7dc91686f6c340dc8b14e5a119d5e4bbcf9339 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 20 Jan 2020 12:04:26 +0800
Subject: [PATCH] add phy_done diagnostics register

---
 jesd204b/core.py | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/jesd204b/core.py b/jesd204b/core.py
index 1a6f563..24fe046 100644
--- a/jesd204b/core.py
+++ b/jesd204b/core.py
@@ -18,6 +18,7 @@ def __init__(self, phys, jesd_settings, converter_data_width):
         self.enable = Signal()
         self.jsync = Signal()
         self.jref = Signal()
+        self.phy_done = Signal()
         self.ready = Signal()
         self.restart = Signal()
 
@@ -55,8 +56,8 @@ def __init__(self, phys, jesd_settings, converter_data_width):
             )
 
         links = []
-        link_reset = Signal()
-        self.comb += link_reset.eq(~reduce(and_, [phy.transmitter.init.done for phy in phys]))
+        phy_done = Signal()
+        self.comb += phy_done.eq(reduce(and_, [phy.transmitter.init.done for phy in phys]))
         for n, (phy, lane) in enumerate(zip(phys, transport.source.flatten())):
             phy_name = "phy{}".format(n)
             phy_cd = phy_name + "_tx"
@@ -72,7 +73,7 @@ def __init__(self, phys, jesd_settings, converter_data_width):
             self.submodules += link
             links.append(link)
             self.comb += [
-                link.reset.eq(link_reset),
+                link.reset.eq(~phy_done),
                 link.jsync.eq(self.jsync_jesd),
                 link.jref.eq(self.jref)
             ]
@@ -95,7 +96,10 @@ def __init__(self, phys, jesd_settings, converter_data_width):
                                       phy_cd)
         ready = Signal()
         self.comb += ready.eq(reduce(and_, [link.ready for link in links]))
-        self.specials += MultiReg(ready, self.ready)
+        self.specials += [
+            MultiReg(phy_done, self.phy_done),
+            MultiReg(ready, self.ready)
+        ]
 
     # JSYNC is asynchronous and the I/O can be passed directly to the core.
     def register_jsync(self, jsync):
@@ -121,6 +125,7 @@ def do_finalize(self):
 class JESD204BCoreTXControl(Module, AutoCSR):
     def __init__(self, core):
         self.enable = CSRStorage()
+        self.phy_done = CSRStatus()
         self.ready = CSRStatus()
 
         self.prbs_config = CSRStorage(4)
@@ -141,6 +146,7 @@ def __init__(self, core):
 
             self.jsync.status.eq(core.jsync_sys),
 
+            self.phy_done.status.eq(core.phy_done),
             self.ready.status.eq(core.ready)
         ]