These builtins targets on rvv 0.9 and trying to document rvv_intrinsics programming model.
Please see rvv-intrinsic-rfc.md
Keep this chapter none to aligned to riscv-v-spec chapters
Keep this chapter none to aligned to riscv-v-spec chapters
Please see rvv-intrinsic-rfc.md
- vsetvli
- vsetvl
Reinterpret the contents of a data as a different type, without changing any bits and generating any RVV instructions.
enum RVV_CSR {
RVV_VSTART = 0,
RVV_VXSAT,
RVV_VXRM,
RVV_VCSR,
};
unsigned long vread_csr(enum RVV_CSR csr);
void vwrite_csr(enum RVV_CSR csr, unsigned long value);
- vle<eew>.v
- vse<eew>.v
- vlse<eew>.v
- vsse<eew>.v
- vlxei<eew>.v
- vsxei<eew>.v
- vsuxei<eew>.v
- vle<eew>ff.v
- Execute a regular load and stop load operation if there is 0 value of element, and then set vl equals the index of last non-zero value.
- vlsege<eew>.v
- vssege<eew>.v
- vlssege<eew>.v
- vsssege<eew>.v
- vlxsegei<eew>.v
- vsxsegei<eew>.v
- vamoswapei<eew>.v
- vamoaddei<eew>.v
- vamoxorei<eew>.v
- vamoandei<eew>.v
- vamoorei<eew>.v
- vamominei<eew>.v
- vamomaxei<eew>.v
- vamominuei<eew>.v
- vamomaxuei<eew>.v
Keep this chapter none to aligned to riscv-v-spec chapters
Keep this chapter none to aligned to riscv-v-spec chapters
Keep this chapter none to aligned to riscv-v-spec chapters
- vadd.{vv,vx,vi}
- vsub.{vv,vx}
- vrsub.{vx,vi}
- vwaddu.{vv,vx,wv,wx}
- vwsubu.{vv,vx,wv,wx}
- vwadd.{vv,vx,wv,wx}
- vwsub.{vv,vx,wv,wx}
- vzext.vf{2,4,8}
- vsext.vf{2,4,8}
- vadc.{vvm,vxm,vim}
- vmadc.{vvm,vxm,vim}
- vsbc.{vvm,vxm}
- vmsbc.{vvm,vxm}
- vand.{vv,vx,vi}
- vxor.{vv,vx,vi}
- vor.{vv,vx,vi}
- vsll.{vv,vx,vi}
- vsrl.{vv,vx,vi}
- vsra.{vv,vx,vi}
- A full complement of vector shift instructions are provided, including logical shift left, and logical (zero-extending) and arithmetic (sign-extending) shift right.
- vnsra.{vv,vx,vi}
- vnsrl.{vv,vx,vi}
- vmseq.{vv,vx,vi}
- vmsne.{vv,vx,vi}
- vmsltu.{vv,vx}
- vmslt.{vv,vx}
- vmsleu.{vv,vx,vi}
- vmsle.{vv,vx,vi}
- vmsgtu.{vx,vi}
- vmsgt.{vx,vi}
- vminu_{vv,vx}
- vmin_{vv,vx}
- vmaxu_{vv,vx}
- vmax_{vv,vx}
- vmul_{vv,vx}
- vmulh_{vv,vx}
- vmulhu_{vv,vx}
- vmulhsu_{vv,vx}
- vdivu.{vv,vx}
- vdiv.{vv,vx}
- vremu.{vv,vx}
- vrem.{vv,vx}
- vwmul.{vv,vx}
- vwmulu.{vv,vx}
- vwmulsu.{vv,vx}
- vmacc_{vv,vx}
- vnmsac_{vv,vx}
- vmadd_{vv,vx}
- vnmsub_{vv,vx}
- vwmaccu.{vv,vx}
- vwmacc.{vv,vx}
- vwmaccsu.{vv,vx}
- vwmaccus.{vv,vx}
- vqmaccu.{vv,vx}
- vqmacc.{vv,vx}
- vqmaccsu.{vv,vx}
- vqmaccus.vx
- vmerge.{vvm,vxm,vim}
- vmv.v.v
- vmv.v.x
- vmv.v.i
- vsaddu.{vv,vx,vi}
- vsadd.{vv,vx,vi}
- vssubu.{vv,vx}
- vssub.{vv,vx}
- vaadd.{vv,vx,vi}
- vasub.{vv,vx}
- vsmul.{vv,vx}
- vssrl.{vv,vx,vi}
- vssra.{vv,vx,vi}
- vnclipu.{wx,wv,wi}
- vnclip.{wx,wv,wi}
- vfadd.{vv,vf}
- vfsub.{vv,vf}
- vfrsub.vf
- vfwadd.{vv,vf,wv,wf}
- vfwsub.{vv,vf,wv,wf}
- vfmul.{vv,vf}
- vfdiv.{vv,vf}
- vfrdiv.{vv,vf}
- vfwmul.{vv,vf}
- vfmacc.{vv,vf}
- vfnmacc.{vv,vf}
- vfmsac.{vv,vf}
- vfnmsac.{vv,vf}
- vfmadd.{vv,vf}
- vfnmadd.{vv,vf}
- vfmsub.{vv,vf}
- vfnmsub.{vv,vf}
- vfwmacc.{vv,vf}
- vfwnmacc.{vv,vf}
- vfwmsac.{vv,vf}
- vfwnmsac.{vv,vf}
- vfsqrt.v
- vfmin.{vv,vf}
- vfmax.{vv,vf}
- vfsgnj.{vv,vf}
- vfsgnjn.{vv,vf}
- vfsgnjx.{vv,vf}
- vmfeq.{vv,vf}
- vmfne.{vv,vf}
- vmflt.{vv,vf}
- vmfle.{vv,vf}
- vmfgt.vf
- vmfge.vf
- vfclass.v
- vfmerge.vfm
- vfmv.v.f
- vfcvt.xu.f.v
- vfcvt.x.f.v
- vfcvt.f.xu.v
- vfcvt.f.x.v
- vfwcvt.xu.f.v
- vfwcvt.x.f.v
- vfwcvt.f.xu.v
- vfwcvt.f.x.v
- vfwcvt.f.f.v
- vfncvt.xu.f.w
- vfncvt.x.f.w
- vfncvt.f.xu.w
- vfncvt.f.x.w
- vfncvt.f.f.w
- vfncvt.rod.f.f.w
- vredsum.vs
- vredmaxu.vs
- vredmax.vs
- vredminu.vs
- vredmin.vs
- vredand.vs
- vredor.vs
- vredxor.vs
- vwredsumu.vs
- vwredsum.vs
- vfredosum.vs
- vfredsum.vs
- vfredmax.vs
- vfredmin.vs
- vfwredosum.vs
- vfwredsum.vs
- vmand.mm
- vmnand.mm
- vmandnot.mm
- vmxor.mm
- vmor.mm
- vmnor.mm
- vmornot.mm
- vmxnor.mm
- vmmv.m
- vmclr.m
- vmset.m
- vmnot.m
- vpopc.m
- vfirst.m
- vmsbf.m
- vmsif.m
- vmsof.m
- viota.m
- vid.v
- vmv.s.x
- vmv.x.s
- vfmv.f.s
- vfmv.s.f
- vslideup.{vx,vi}
- vslidedown.{vx,vi}
- vslide1up.vx
- vslide1down.vx
- vfslide1up.vx
- vfslide1down.vx
- vrgather.{vx,vi}
- vcompress.vm
Keep this chapter none to aligned to riscv-v-spec chapters
- vdotu.vv
- vdot.vv
TODO
- vfdotu.vv
TODO