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boot_stub.elf.lst
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/Users/Luppy/PineTime/pinetime-rust-mynewt/bin/targets/nrf52_boot/app/apps/boot_stub/boot_stub.elf: file format elf32-littlearm
/Users/Luppy/PineTime/pinetime-rust-mynewt/bin/targets/nrf52_boot/app/apps/boot_stub/boot_stub.elf
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x000000d9
Program Header:
0x70000001 off 0x00010b48 vaddr 0x00000b48 paddr 0x00000b48 align 2**2
filesz 0x00000018 memsz 0x00000018 flags r--
LOAD off 0x00010000 vaddr 0x00000000 paddr 0x00000000 align 2**16
filesz 0x00000b60 memsz 0x00000b60 flags r-x
LOAD off 0x000200d8 vaddr 0x200000d8 paddr 0x00000b60 align 2**16
filesz 0x00000018 memsz 0x00000044 flags rw-
LOAD off 0x00030000 vaddr 0x20000000 paddr 0x20000000 align 2**16
filesz 0x00000000 memsz 0x000000d8 flags rw-
private flags = 5000200: [Version5 EABI] [soft-float ABI]
Sections:
Idx Name Size VMA LMA File off Algn Flags
0 .text 00000b48 00000000 00000000 00010000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .ARM.extab 00000000 00000b48 00000b48 000200f0 2**0 CONTENTS
2 .ARM.exidx 00000018 00000b48 00000b48 00010b48 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .vector_relocation 000000d8 20000000 20000000 00030000 2**0 ALLOC
4 .rtt 00000000 200000d8 200000d8 000200f0 2**0 CONTENTS
5 .data 00000018 200000d8 00000b60 000200d8 2**2 CONTENTS, ALLOC, LOAD, DATA
6 .bssnz 00000000 200000f0 200000f0 000200f0 2**0 CONTENTS
7 .bss 0000002c 200000f0 00000b78 000200f0 2**2 ALLOC
8 .stack_dummy 000001b0 20000120 20000120 000200f0 2**3 CONTENTS, READONLY
9 .ARM.attributes 0000002f 00000000 00000000 000202a0 2**0 CONTENTS, READONLY
10 .comment 0000007f 00000000 00000000 000202cf 2**0 CONTENTS, READONLY
11 .svc_table 00000004 00000000 00000000 0002034e 2**0 CONTENTS, READONLY
12 .debug_line 00004909 00000000 00000000 00020352 2**0 CONTENTS, READONLY, DEBUGGING
13 .debug_info 0000a2ad 00000000 00000000 00024c5b 2**0 CONTENTS, READONLY, DEBUGGING
14 .debug_abbrev 00001ffa 00000000 00000000 0002ef08 2**0 CONTENTS, READONLY, DEBUGGING
15 .debug_aranges 000004f0 00000000 00000000 00030f08 2**3 CONTENTS, READONLY, DEBUGGING
16 .debug_str 0000248c 00000000 00000000 000313f8 2**0 CONTENTS, READONLY, DEBUGGING
17 .debug_loc 00001e98 00000000 00000000 00033884 2**0 CONTENTS, READONLY, DEBUGGING
18 .debug_ranges 000003b0 00000000 00000000 0003571c 2**0 CONTENTS, READONLY, DEBUGGING
19 .debug_frame 000009d4 00000000 00000000 00035acc 2**2 CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00000000 l d .text 00000000 .text
00000b48 l d .ARM.extab 00000000 .ARM.extab
00000b48 l d .ARM.exidx 00000000 .ARM.exidx
20000000 l d .vector_relocation 00000000 .vector_relocation
200000d8 l d .rtt 00000000 .rtt
200000d8 l d .data 00000000 .data
200000f0 l d .bssnz 00000000 .bssnz
200000f0 l d .bss 00000000 .bss
20000120 l d .stack_dummy 00000000 .stack_dummy
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .comment 00000000 .comment
00000000 l d .svc_table 00000000 .svc_table
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l df *ABS* 00000000 gcc_startup_nrf52.o
000001b0 l *ABS* 00000000 Stack_Size
00000000 l *ABS* 00000000 Heap_Size
000000e0 l .text 00000000 .bss_zero_loop
00000000 l df *ABS* 00000000 sbrk.c
200000d8 l O .data 00000004 sbrkBase
200000dc l O .data 00000004 sbrkLimit
200000e0 l O .data 00000004 brk
00000000 l df *ABS* 00000000 hal_system.c
00000000 l df *ABS* 00000000 system_nrf52.c
000001ec l F .text 0000003c errata_16
00000228 l F .text 0000004c errata_31
00000274 l F .text 0000003c errata_32
000002b0 l F .text 0000004c errata_36
000002fc l F .text 0000003c errata_37
00000338 l F .text 0000003c errata_57
00000374 l F .text 0000003c errata_66
000003b0 l F .text 0000004c errata_108
00000000 l df *ABS* 00000000 start.c
00000000 l df *ABS* 00000000 boot.c
00000000 l df *ABS* 00000000 hal_bsp.c
00000000 l df *ABS* 00000000 cmsis_nvic.c
00000000 l df *ABS* 00000000 hal_common.c
00000000 l df *ABS* 00000000 hal_system_start.c
00000000 l df *ABS* 00000000 nrf52_periph.c
00000640 l F .text 00000034 nrf52_periph_create_timers
00000000 l df *ABS* 00000000 hal_timer.c
0000067c l F .text 0000000a nrf_read_timer_cntr
00000688 l F .text 000000b4 nrf_timer_set_ocmp
0000073c l F .text 0000000a nrf_timer_disable_ocmp
00000746 l F .text 0000000a nrf_rtc_disable_ocmp
00000750 l F .text 00000054 hal_timer_read_bsptimer
000007a4 l F .text 00000076 hal_timer_chk_queue
0000081a l F .text 0000002c hal_timer_irq_handler
00000ae8 l O .text 00000018 nrf52_hal_timers
00000000 l df *ABS* 00000000 os_fault.c
00000000 l df *ABS* 00000000 os_cputime.c
00000000 l df *ABS* 00000000 os_arch_arm.c
00000000 l df *ABS* 00000000 os_time.c
00000000 l df *ABS* 00000000 HAL_CM4.o
00000a5c l .text 00000000 SVC_User
00000a7a l .text 00000000 SVC_Done
00000000 l df *ABS* 00000000 nrf52_boot-sysflash.c
00000000 l df *ABS* 00000000 os_sched.c
00000000 l df *ABS* 00000000 SVC_Table.S
00000000 l .svc_table 00000000 SVC_End
20000120 g .bss 00000000 __HeapBase
00000000 g .svc_table 00000000 SVC_Count
00000144 w F .text 00000002 TIMER2_IRQHandler
00000144 w F .text 00000002 RTC0_IRQHandler
200000d8 g .data 00000000 __data_start__
00000144 w F .text 00000002 SWI0_EGU0_IRQHandler
00000136 w F .text 00000002 HardFault_Handler
00000858 g F .text 00000060 hal_timer_init
00000636 g F .text 0000000a hal_system_start
00000144 w F .text 00000002 SWI2_EGU2_IRQHandler
00000aaa g F .text 0000000c SysTick_Handler
00000144 w F .text 00000002 GPIOTE_IRQHandler
00000848 g F .text 00000010 nrf52_timer0_irq_handler
00000144 w F .text 00000002 PWM1_IRQHandler
00000a80 g F .text 0000002a PendSV_Handler
00000134 w F .text 00000002 NMI_Handler
00000b60 g .ARM.exidx 00000000 __exidx_end
00000000 g .text 00000000 __isr_vector_start
00000174 g F .text 0000002c hal_system_reset
200000f0 g .data 00000000 __aeabi_unwind_cpp_pr0
00000144 w F .text 00000002 POWER_CLOCK_IRQHandler
00000b60 g .ARM.exidx 00000000 __etext
00000144 w F .text 00000002 RADIO_IRQHandler
200000f0 g .bssnz 00000000 __bssnz_start__
00000144 w F .text 00000002 PDM_IRQHandler
00000144 w F .text 00000002 TEMP_IRQHandler
00000144 w F .text 00000002 QDEC_IRQHandler
00000144 w F .text 00000002 TIMER3_IRQHandler
000009f8 g F .text 0000000a timer_handler
000009ec g F .text 0000000c os_cputime_init
00000000 g *ABS* 00000000 _imghdr_size
200000e4 g O .data 00000004 SystemCoreClock
00000158 g F .text 0000000c hal_system_init
00000144 w F .text 00000002 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
000009b0 g F .text 00000024 __assert_func
0000013c w F .text 00000002 UsageFault_Handler
00000144 w F .text 00000002 UARTE0_UART0_IRQHandler
2000fe50 g *ABS* 00000000 __HeapLimit
200000f0 g .bss 00000000 __bss_start__
00000164 g F .text 00000010 hal_debugger_connected
00000144 w F .text 00000002 TIMER4_IRQHandler
20000110 g O .bss 00000004 g_current_task
00000a02 g F .text 0000000c os_arch_save_sr
00000b48 g .text 00000000 __exidx_start
00000a20 g F .text 00000014 os_set_env
00000674 g F .text 00000008 nrf52_periph_create
00000144 w F .text 00000002 I2S_IRQHandler
000005da g F .text 00000002 _init
00000144 w F .text 00000002 SWI4_EGU4_IRQHandler
00000144 w F .text 00000002 TIMER0_IRQHandler
000000d8 g F .text 0000005c Reset_Handler
00000ab6 g F .text 0000001e os_default_irq_asm
00000148 g F .text 00000010 _sbrkInit
200000f0 g .bssnz 00000000 __bssnz_end__
00000144 w F .text 00000002 TIMER1_IRQHandler
20000000 g .bss 00000000 _ram_start
20000000 g .vector_relocation 00000000 __vector_tbl_reloc__
00000144 w F .text 00000002 PWM2_IRQHandler
200000f0 g .data 00000000 __data_end__
00000144 w F .text 00000002 ECB_IRQHandler
20000118 g O .bss 00000004 g_os_time
2000011c g .bss 00000000 __bss_end__
00000144 w F .text 00000002 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
00000144 g F .text 00000002 Default_Handler
000005cc g F .text 0000000e _start
00000a34 g F .text 00000006 os_arch_init_task_stack
000009d4 g F .text 00000018 os_default_irq
20000114 g O .bss 00000004 g_os_last_ctx_sw_time
000008b8 g F .text 000000f8 hal_timer_config
00000144 w F .text 00000002 SAADC_IRQHandler
00000000 g .text 000000d8 __isr_vector
000005dc g F .text 00000014 main
00000144 w F .text 00000002 CCM_AAR_IRQHandler
00000144 w F .text 00000002 WDT_IRQHandler
00000a3a g F .text 00000046 SVC_Handler
00000144 w F .text 00000002 SWI5_EGU5_IRQHandler
00000000 g .text 00000000 __text
0000040c g F .text 000001c0 SystemInit
00000144 w F .text 00000002 RNG_IRQHandler
00000000 g .svc_table 00000000 SVC_Table
00000144 w F .text 00000002 RTC2_IRQHandler
20010000 g .bss 00000000 __StackTop
00000144 w F .text 00000002 PWM0_IRQHandler
00000144 w F .text 00000002 SWI3_EGU3_IRQHandler
00000b00 g O .text 00000048 sysflash_map_dflt
200000f4 g O .bss 0000001c nrf52_hal_timer0
000000d8 g .text 00000000 __isr_vector_end
00000144 w F .text 00000002 RTC1_IRQHandler
00000144 w F .text 00000002 SWI1_EGU1_IRQHandler
200000e8 g O .data 00000008 g_os_run_list
000005fc g F .text 00000034 NVIC_Relocate
200000f0 g O .bss 00000004 os_flags
2000fe50 g *ABS* 000001b0 __StackLimit
00000144 w F .text 00000002 SPIM2_SPIS2_SPI2_IRQHandler
00000144 w F .text 00000002 NFCT_IRQHandler
000003fc g F .text 00000010 SystemCoreClockUpdate
00000630 g F .text 00000006 _exit
000001a0 g F .text 0000004c hal_system_clock_start
0000013a w F .text 00000002 BusFault_Handler
00000a10 g F .text 00000010 os_time_advance
00000144 w F .text 00000002 MWU_IRQHandler
00000138 w F .text 00000002 MemoryManagement_Handler
00000144 w F .text 00000002 COMP_LPCOMP_IRQHandler
000005f0 g F .text 0000000c hal_bsp_init
Disassembly of section .text:
00000000 <__isr_vector>:
* NOTE: must be called with interrupts disabled! This function does not call
* the scheduler
*/
int
os_sched_sleep(struct os_task *t, os_time_t nticks)
{
0: 20010000 .word 0x20010000
4: 000000d9 .word 0x000000d9
struct os_task *entry;
entry = NULL;
TAILQ_REMOVE(&g_os_run_list, t, t_os_list);
8: 00000135 .word 0x00000135
c: 00000137 .word 0x00000137
...
if (nticks == OS_TIMEOUT_NEVER) {
t->t_flags |= OS_TASK_FLAG_NO_TIMEOUT;
TAILQ_INSERT_TAIL(&g_os_sleep_list, t, t_os_list);
} else {
TAILQ_FOREACH(entry, &g_os_sleep_list, t_os_list) {
if ((entry->t_flags & OS_TASK_FLAG_NO_TIMEOUT) ||
2c: 00000a3b .word 0x00000a3b
...
38: 00000a81 .word 0x00000a81
TAILQ_FOREACH(entry, &g_os_sleep_list, t_os_list) {
3c: 00000aab .word 0x00000aab
TAILQ_REMOVE(&g_os_run_list, t, t_os_list);
40: 00000145 .word 0x00000145
44: 00000145 .word 0x00000145
t->t_flags |= OS_TASK_FLAG_NO_TIMEOUT;
48: 00000145 .word 0x00000145
4c: 00000145 .word 0x00000145
TAILQ_INSERT_TAIL(&g_os_sleep_list, t, t_os_list);
50: 00000145 .word 0x00000145
54: 00000145 .word 0x00000145
58: 00000145 .word 0x00000145
5c: 00000145 .word 0x00000145
60: 00000145 .word 0x00000145
OS_TIME_TICK_GT(entry->t_next_wakeup, t->t_next_wakeup)) {
break;
}
}
if (entry) {
TAILQ_INSERT_BEFORE(entry, t, t_os_list);
64: 00000145 .word 0x00000145
68: 00000145 .word 0x00000145
6c: 00000145 .word 0x00000145
70: 00000145 .word 0x00000145
}
}
os_trace_task_stop_ready(t, OS_TASK_SLEEP);
return (0);
}
74: 00000145 .word 0x00000145
TAILQ_INSERT_TAIL(&g_os_sleep_list, t, t_os_list);
78: 00000145 .word 0x00000145
7c: 00000145 .word 0x00000145
80: 00000145 .word 0x00000145
84: 00000145 .word 0x00000145
88: 00000145 .word 0x00000145
8c: 00000145 .word 0x00000145
90: 00000145 .word 0x00000145
94: 00000145 .word 0x00000145
98: 00000145 .word 0x00000145
9c: 00000145 .word 0x00000145
a0: 00000145 .word 0x00000145
a4: 00000145 .word 0x00000145
a8: 00000145 .word 0x00000145
ac: 00000145 .word 0x00000145
b0: 00000145 .word 0x00000145
b4: 00000145 .word 0x00000145
...
c0: 00000145 .word 0x00000145
c4: 00000145 .word 0x00000145
c8: 00000145 .word 0x00000145
cc: 00000145 .word 0x00000145
d0: 00000145 .word 0x00000145
d4: 00000145 .word 0x00000145
000000d8 <Reset_Handler>:
.type Reset_Handler, %function
Reset_Handler:
.fnstart
/* Clear BSS */
mov r0, #0
d8: f04f 0000 mov.w r0, #0
ldr r2, =__bss_start__
dc: 4a0c ldr r2, [pc, #48] ; (110 <.bss_zero_loop+0x30>)
ldr r3, =__bss_end__
de: 4b0d ldr r3, [pc, #52] ; (114 <.bss_zero_loop+0x34>)
000000e0 <.bss_zero_loop>:
.bss_zero_loop:
cmp r2, r3
e0: 429a cmp r2, r3
itt lt
e2: bfbc itt lt
strlt r0, [r2], #4
e4: f842 0b04 strlt.w r0, [r2], #4
blt .bss_zero_loop
e8: e7fa blt.n e0 <.bss_zero_loop>
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ea: 490b ldr r1, [pc, #44] ; (118 <.bss_zero_loop+0x38>)
ldr r2, =__data_start__
ec: 4a0b ldr r2, [pc, #44] ; (11c <.bss_zero_loop+0x3c>)
ldr r3, =__data_end__
ee: 4b0c ldr r3, [pc, #48] ; (120 <.bss_zero_loop+0x40>)
subs r3, r2
f0: 1a9b subs r3, r3, r2
ble .LC0
f2: dd03 ble.n fc <.bss_zero_loop+0x1c>
.LC1:
subs r3, 4
f4: 3b04 subs r3, #4
ldr r0, [r1,r3]
f6: 58c8 ldr r0, [r1, r3]
str r0, [r2,r3]
f8: 50d0 str r0, [r2, r3]
bgt .LC1
fa: dcfb bgt.n f4 <.bss_zero_loop+0x14>
.LC0:
LDR R0, =__HeapBase
fc: 4809 ldr r0, [pc, #36] ; (124 <.bss_zero_loop+0x44>)
LDR R1, =__HeapLimit
fe: 490a ldr r1, [pc, #40] ; (128 <.bss_zero_loop+0x48>)
BL _sbrkInit
100: f000 f822 bl 148 <_sbrkInit>
LDR R0, =SystemInit
104: 4809 ldr r0, [pc, #36] ; (12c <.bss_zero_loop+0x4c>)
BLX R0
106: 4780 blx r0
BL hal_system_init
108: f000 f826 bl 158 <hal_system_init>
LDR R0, =_start
10c: 4808 ldr r0, [pc, #32] ; (130 <.bss_zero_loop+0x50>)
BX R0
10e: 4700 bx r0
ldr r2, =__bss_start__
110: 200000f0 .word 0x200000f0
ldr r3, =__bss_end__
114: 2000011c .word 0x2000011c
ldr r1, =__etext
118: 00000b60 .word 0x00000b60
ldr r2, =__data_start__
11c: 200000d8 .word 0x200000d8
ldr r3, =__data_end__
120: 200000f0 .word 0x200000f0
LDR R0, =__HeapBase
124: 20000120 .word 0x20000120
LDR R1, =__HeapLimit
128: 2000fe50 .word 0x2000fe50
LDR R0, =SystemInit
12c: 0000040d .word 0x0000040d
LDR R0, =_start
130: 000005cd .word 0x000005cd
00000134 <NMI_Handler>:
/* Dummy Exception Handlers (infinite loops which can be modified) */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
134: e7fe b.n 134 <NMI_Handler>
00000136 <HardFault_Handler>:
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
136: e7fe b.n 136 <HardFault_Handler>
00000138 <MemoryManagement_Handler>:
.weak MemoryManagement_Handler
.type MemoryManagement_Handler, %function
MemoryManagement_Handler:
B .
138: e7fe b.n 138 <MemoryManagement_Handler>
0000013a <BusFault_Handler>:
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
B .
13a: e7fe b.n 13a <BusFault_Handler>
0000013c <UsageFault_Handler>:
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
B .
13c: e7fe b.n 13c <UsageFault_Handler>
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
13e: e7fe b.n 13e <UsageFault_Handler+0x2>
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
140: e7fe b.n 140 <UsageFault_Handler+0x4>
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
142: e7fe b.n 142 <UsageFault_Handler+0x6>
00000144 <Default_Handler>:
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
144: e7fe b.n 144 <Default_Handler>
146: bf00 nop
00000148 <_sbrkInit>:
static char *sbrkLimit __attribute__ ((section (".data")));
static char *brk __attribute__ ((section (".data")));
void
_sbrkInit(char *base, char *limit) {
sbrkBase = base;
148: 4b02 ldr r3, [pc, #8] ; (154 <_sbrkInit+0xc>)
14a: 6018 str r0, [r3, #0]
sbrkLimit = limit;
14c: 6059 str r1, [r3, #4]
brk = base;
14e: 6098 str r0, [r3, #8]
}
150: 4770 bx lr
152: bf00 nop
154: 200000d8 .word 0x200000d8
00000158 <hal_system_init>:
*/
void
hal_system_init(void)
{
#if MYNEWT_VAL(MCU_DCDC_ENABLED)
NRF_POWER->DCDCEN = 1;
158: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
15c: 2201 movs r2, #1
15e: f8c3 2578 str.w r2, [r3, #1400] ; 0x578
#endif
}
162: 4770 bx lr
00000164 <hal_debugger_connected>:
}
int
hal_debugger_connected(void)
{
return CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk;
164: 4b02 ldr r3, [pc, #8] ; (170 <hal_debugger_connected+0xc>)
166: 6818 ldr r0, [r3, #0]
}
168: f000 0001 and.w r0, r0, #1
16c: 4770 bx lr
16e: bf00 nop
170: e000edf0 .word 0xe000edf0
00000174 <hal_system_reset>:
{
174: b508 push {r3, lr}
if (hal_debugger_connected()) {
176: f7ff fff5 bl 164 <hal_debugger_connected>
17a: b100 cbz r0, 17e <hal_system_reset+0xa>
asm("bkpt");
17c: be00 bkpt 0x0000
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
17e: f3bf 8f4f dsb sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
182: 4905 ldr r1, [pc, #20] ; (198 <hal_system_reset+0x24>)
184: 68ca ldr r2, [r1, #12]
186: f402 62e0 and.w r2, r2, #1792 ; 0x700
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
18a: 4b04 ldr r3, [pc, #16] ; (19c <hal_system_reset+0x28>)
18c: 4313 orrs r3, r2
18e: 60cb str r3, [r1, #12]
190: f3bf 8f4f dsb sy
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
194: bf00 nop
196: e7fd b.n 194 <hal_system_reset+0x20>
198: e000ed00 .word 0xe000ed00
19c: 05fa0004 .word 0x05fa0004
000001a0 <hal_system_clock_start>:
}
}
#endif
/* Check if this clock source is already running */
if ((NRF_CLOCK->LFCLKSTAT & regmsk) != regval) {
1a0: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
1a4: f8d3 2418 ldr.w r2, [r3, #1048] ; 0x418
1a8: 4b0f ldr r3, [pc, #60] ; (1e8 <Stack_Size+0x38>)
1aa: 4013 ands r3, r2
1ac: f1b3 1f01 cmp.w r3, #65537 ; 0x10001
1b0: d018 beq.n 1e4 <Stack_Size+0x34>
NRF_CLOCK->TASKS_LFCLKSTOP = 1;
1b2: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
1b6: 2201 movs r2, #1
1b8: 60da str r2, [r3, #12]
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
1ba: 2100 movs r1, #0
1bc: f8c3 1104 str.w r1, [r3, #260] ; 0x104
NRF_CLOCK->LFCLKSRC = clksrc;
1c0: f8c3 2518 str.w r2, [r3, #1304] ; 0x518
NRF_CLOCK->TASKS_LFCLKSTART = 1;
1c4: 609a str r2, [r3, #8]
/* Wait here till started! */
while (1) {
if (NRF_CLOCK->EVENTS_LFCLKSTARTED) {
1c6: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
1ca: f8d3 3104 ldr.w r3, [r3, #260] ; 0x104
1ce: 2b00 cmp r3, #0
1d0: d0f9 beq.n 1c6 <Stack_Size+0x16>
if ((NRF_CLOCK->LFCLKSTAT & regmsk) == regval) {
1d2: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
1d6: f8d3 2418 ldr.w r2, [r3, #1048] ; 0x418
1da: 4b03 ldr r3, [pc, #12] ; (1e8 <Stack_Size+0x38>)
1dc: 4013 ands r3, r2
1de: f1b3 1f01 cmp.w r3, #65537 ; 0x10001
1e2: d1f0 bne.n 1c6 <Stack_Size+0x16>
}
}
}
}
#endif
}
1e4: 4770 bx lr
1e6: bf00 nop
1e8: 00010003 .word 0x00010003
000001ec <errata_16>:
}
#ifdef NRF52
static bool errata_16(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
1ec: 4b0b ldr r3, [pc, #44] ; (21c <errata_16+0x30>)
1ee: 781b ldrb r3, [r3, #0]
1f0: 2b06 cmp r3, #6
1f2: d001 beq.n 1f8 <errata_16+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
1f4: 2000 movs r0, #0
1f6: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
1f8: 4b09 ldr r3, [pc, #36] ; (220 <errata_16+0x34>)
1fa: 681b ldr r3, [r3, #0]
1fc: f013 0f0f tst.w r3, #15
200: d107 bne.n 212 <errata_16+0x26>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
202: 4b08 ldr r3, [pc, #32] ; (224 <errata_16+0x38>)
204: 681b ldr r3, [r3, #0]
206: f003 03f0 and.w r3, r3, #240 ; 0xf0
20a: 2b30 cmp r3, #48 ; 0x30
20c: d003 beq.n 216 <errata_16+0x2a>
return false;
20e: 2000 movs r0, #0
210: 4770 bx lr
212: 2000 movs r0, #0
214: 4770 bx lr
return true;
216: 2001 movs r0, #1
}
218: 4770 bx lr
21a: bf00 nop
21c: f0000fe0 .word 0xf0000fe0
220: f0000fe4 .word 0xf0000fe4
224: f0000fe8 .word 0xf0000fe8
00000228 <errata_31>:
static bool errata_31(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
228: 4b0f ldr r3, [pc, #60] ; (268 <errata_31+0x40>)
22a: 781b ldrb r3, [r3, #0]
22c: 2b06 cmp r3, #6
22e: d001 beq.n 234 <errata_31+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
230: 2000 movs r0, #0
232: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
234: 4b0d ldr r3, [pc, #52] ; (26c <errata_31+0x44>)
236: 681b ldr r3, [r3, #0]
238: f013 0f0f tst.w r3, #15
23c: d10b bne.n 256 <errata_31+0x2e>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
23e: 4b0c ldr r3, [pc, #48] ; (270 <errata_31+0x48>)
240: 681b ldr r3, [r3, #0]
242: f003 03f0 and.w r3, r3, #240 ; 0xf0
246: 2b30 cmp r3, #48 ; 0x30
248: d007 beq.n 25a <errata_31+0x32>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
24a: 2b40 cmp r3, #64 ; 0x40
24c: d007 beq.n 25e <errata_31+0x36>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
24e: 2b50 cmp r3, #80 ; 0x50
250: d007 beq.n 262 <errata_31+0x3a>
return false;
252: 2000 movs r0, #0
254: 4770 bx lr
256: 2000 movs r0, #0
258: 4770 bx lr
return true;
25a: 2001 movs r0, #1
25c: 4770 bx lr
return true;
25e: 2001 movs r0, #1
260: 4770 bx lr
return true;
262: 2001 movs r0, #1
}
264: 4770 bx lr
266: bf00 nop
268: f0000fe0 .word 0xf0000fe0
26c: f0000fe4 .word 0xf0000fe4
270: f0000fe8 .word 0xf0000fe8
00000274 <errata_32>:
static bool errata_32(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
274: 4b0b ldr r3, [pc, #44] ; (2a4 <errata_32+0x30>)
276: 781b ldrb r3, [r3, #0]
278: 2b06 cmp r3, #6
27a: d001 beq.n 280 <errata_32+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
27c: 2000 movs r0, #0
27e: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
280: 4b09 ldr r3, [pc, #36] ; (2a8 <errata_32+0x34>)
282: 681b ldr r3, [r3, #0]
284: f013 0f0f tst.w r3, #15
288: d107 bne.n 29a <errata_32+0x26>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
28a: 4b08 ldr r3, [pc, #32] ; (2ac <errata_32+0x38>)
28c: 681b ldr r3, [r3, #0]
28e: f003 03f0 and.w r3, r3, #240 ; 0xf0
292: 2b30 cmp r3, #48 ; 0x30
294: d003 beq.n 29e <errata_32+0x2a>
return false;
296: 2000 movs r0, #0
298: 4770 bx lr
29a: 2000 movs r0, #0
29c: 4770 bx lr
return true;
29e: 2001 movs r0, #1
}
2a0: 4770 bx lr
2a2: bf00 nop
2a4: f0000fe0 .word 0xf0000fe0
2a8: f0000fe4 .word 0xf0000fe4
2ac: f0000fe8 .word 0xf0000fe8
000002b0 <errata_36>:
static bool errata_36(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
2b0: 4b0f ldr r3, [pc, #60] ; (2f0 <errata_36+0x40>)
2b2: 781b ldrb r3, [r3, #0]
2b4: 2b06 cmp r3, #6
2b6: d001 beq.n 2bc <errata_36+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
2b8: 2000 movs r0, #0
2ba: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
2bc: 4b0d ldr r3, [pc, #52] ; (2f4 <errata_36+0x44>)
2be: 681b ldr r3, [r3, #0]
2c0: f013 0f0f tst.w r3, #15
2c4: d10b bne.n 2de <errata_36+0x2e>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
2c6: 4b0c ldr r3, [pc, #48] ; (2f8 <errata_36+0x48>)
2c8: 681b ldr r3, [r3, #0]
2ca: f003 03f0 and.w r3, r3, #240 ; 0xf0
2ce: 2b30 cmp r3, #48 ; 0x30
2d0: d007 beq.n 2e2 <errata_36+0x32>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
2d2: 2b40 cmp r3, #64 ; 0x40
2d4: d007 beq.n 2e6 <errata_36+0x36>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
2d6: 2b50 cmp r3, #80 ; 0x50
2d8: d007 beq.n 2ea <errata_36+0x3a>
return false;
2da: 2000 movs r0, #0
2dc: 4770 bx lr
2de: 2000 movs r0, #0
2e0: 4770 bx lr
return true;
2e2: 2001 movs r0, #1
2e4: 4770 bx lr
return true;
2e6: 2001 movs r0, #1
2e8: 4770 bx lr
return true;
2ea: 2001 movs r0, #1
}
2ec: 4770 bx lr
2ee: bf00 nop
2f0: f0000fe0 .word 0xf0000fe0
2f4: f0000fe4 .word 0xf0000fe4
2f8: f0000fe8 .word 0xf0000fe8
000002fc <errata_37>:
static bool errata_37(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
2fc: 4b0b ldr r3, [pc, #44] ; (32c <errata_37+0x30>)
2fe: 781b ldrb r3, [r3, #0]
300: 2b06 cmp r3, #6
302: d001 beq.n 308 <errata_37+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
304: 2000 movs r0, #0
306: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
308: 4b09 ldr r3, [pc, #36] ; (330 <errata_37+0x34>)
30a: 681b ldr r3, [r3, #0]
30c: f013 0f0f tst.w r3, #15
310: d107 bne.n 322 <errata_37+0x26>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
312: 4b08 ldr r3, [pc, #32] ; (334 <errata_37+0x38>)
314: 681b ldr r3, [r3, #0]
316: f003 03f0 and.w r3, r3, #240 ; 0xf0
31a: 2b30 cmp r3, #48 ; 0x30
31c: d003 beq.n 326 <errata_37+0x2a>
return false;
31e: 2000 movs r0, #0
320: 4770 bx lr
322: 2000 movs r0, #0
324: 4770 bx lr
return true;
326: 2001 movs r0, #1
}
328: 4770 bx lr
32a: bf00 nop
32c: f0000fe0 .word 0xf0000fe0
330: f0000fe4 .word 0xf0000fe4
334: f0000fe8 .word 0xf0000fe8
00000338 <errata_57>:
static bool errata_57(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
338: 4b0b ldr r3, [pc, #44] ; (368 <errata_57+0x30>)
33a: 781b ldrb r3, [r3, #0]
33c: 2b06 cmp r3, #6
33e: d001 beq.n 344 <errata_57+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
340: 2000 movs r0, #0
342: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
344: 4b09 ldr r3, [pc, #36] ; (36c <errata_57+0x34>)
346: 681b ldr r3, [r3, #0]
348: f013 0f0f tst.w r3, #15
34c: d107 bne.n 35e <errata_57+0x26>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
34e: 4b08 ldr r3, [pc, #32] ; (370 <errata_57+0x38>)
350: 681b ldr r3, [r3, #0]
352: f003 03f0 and.w r3, r3, #240 ; 0xf0
356: 2b30 cmp r3, #48 ; 0x30
358: d003 beq.n 362 <errata_57+0x2a>
return false;
35a: 2000 movs r0, #0
35c: 4770 bx lr
35e: 2000 movs r0, #0
360: 4770 bx lr
return true;
362: 2001 movs r0, #1
}
364: 4770 bx lr
366: bf00 nop
368: f0000fe0 .word 0xf0000fe0
36c: f0000fe4 .word 0xf0000fe4
370: f0000fe8 .word 0xf0000fe8
00000374 <errata_66>:
static bool errata_66(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
374: 4b0b ldr r3, [pc, #44] ; (3a4 <errata_66+0x30>)
376: 781b ldrb r3, [r3, #0]
378: 2b06 cmp r3, #6
37a: d001 beq.n 380 <errata_66+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
37c: 2000 movs r0, #0
37e: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
380: 4b09 ldr r3, [pc, #36] ; (3a8 <errata_66+0x34>)
382: 681b ldr r3, [r3, #0]
384: f013 0f0f tst.w r3, #15
388: d107 bne.n 39a <errata_66+0x26>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
38a: 4b08 ldr r3, [pc, #32] ; (3ac <errata_66+0x38>)
38c: 681b ldr r3, [r3, #0]
38e: f003 03f0 and.w r3, r3, #240 ; 0xf0
392: 2b50 cmp r3, #80 ; 0x50
394: d003 beq.n 39e <errata_66+0x2a>
return false;
396: 2000 movs r0, #0
398: 4770 bx lr
39a: 2000 movs r0, #0
39c: 4770 bx lr
return true;
39e: 2001 movs r0, #1
}
3a0: 4770 bx lr
3a2: bf00 nop
3a4: f0000fe0 .word 0xf0000fe0
3a8: f0000fe4 .word 0xf0000fe4
3ac: f0000fe8 .word 0xf0000fe8
000003b0 <errata_108>:
static bool errata_108(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
3b0: 4b0f ldr r3, [pc, #60] ; (3f0 <errata_108+0x40>)
3b2: 781b ldrb r3, [r3, #0]
3b4: 2b06 cmp r3, #6
3b6: d001 beq.n 3bc <errata_108+0xc>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
3b8: 2000 movs r0, #0
3ba: 4770 bx lr
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
3bc: 4b0d ldr r3, [pc, #52] ; (3f4 <errata_108+0x44>)
3be: 681b ldr r3, [r3, #0]
3c0: f013 0f0f tst.w r3, #15
3c4: d10b bne.n 3de <errata_108+0x2e>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
3c6: 4b0c ldr r3, [pc, #48] ; (3f8 <errata_108+0x48>)
3c8: 681b ldr r3, [r3, #0]
3ca: f003 03f0 and.w r3, r3, #240 ; 0xf0
3ce: 2b30 cmp r3, #48 ; 0x30
3d0: d007 beq.n 3e2 <errata_108+0x32>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
3d2: 2b40 cmp r3, #64 ; 0x40
3d4: d007 beq.n 3e6 <errata_108+0x36>
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
3d6: 2b50 cmp r3, #80 ; 0x50
3d8: d007 beq.n 3ea <errata_108+0x3a>
return false;
3da: 2000 movs r0, #0
3dc: 4770 bx lr
3de: 2000 movs r0, #0
3e0: 4770 bx lr
return true;
3e2: 2001 movs r0, #1
3e4: 4770 bx lr
return true;
3e6: 2001 movs r0, #1
3e8: 4770 bx lr
return true;
3ea: 2001 movs r0, #1
}
3ec: 4770 bx lr
3ee: bf00 nop
3f0: f0000fe0 .word 0xf0000fe0
3f4: f0000fe4 .word 0xf0000fe4
3f8: f0000fe8 .word 0xf0000fe8
000003fc <SystemCoreClockUpdate>:
SystemCoreClock = __SYSTEM_CLOCK_64M;
3fc: 4b01 ldr r3, [pc, #4] ; (404 <SystemCoreClockUpdate+0x8>)
3fe: 4a02 ldr r2, [pc, #8] ; (408 <SystemCoreClockUpdate+0xc>)
400: 601a str r2, [r3, #0]
}
402: 4770 bx lr
404: 200000e4 .word 0x200000e4
408: 03d09000 .word 0x03d09000
0000040c <SystemInit>:
{
40c: b508 push {r3, lr}
if (errata_16()){
40e: f7ff feed bl 1ec <errata_16>
412: b110 cbz r0, 41a <SystemInit+0xe>
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
414: 4b60 ldr r3, [pc, #384] ; (598 <SystemInit+0x18c>)
416: 4a61 ldr r2, [pc, #388] ; (59c <SystemInit+0x190>)
418: 601a str r2, [r3, #0]
if (errata_31()){
41a: f7ff ff05 bl 228 <errata_31>
41e: b128 cbz r0, 42c <SystemInit+0x20>
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
420: 4b5f ldr r3, [pc, #380] ; (5a0 <SystemInit+0x194>)