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Use ipgen to generate rv_plic #8431

Merged
merged 4 commits into from
Oct 7, 2021
Merged

Use ipgen to generate rv_plic #8431

merged 4 commits into from
Oct 7, 2021

Commits on Oct 6, 2021

  1. [topgen] Add logic to call ipgen 

    Add the ability to produce IP blocks through ipgen instead of having
custom logic within topgen. In this commit this logic isn't use yet.

A difference between topgen-generated IP blocks and ipgen-generated
ones is the slightly different directory structure: ipgen does produce a
full IP block directory, matching a "regular" IP block, and does not
include "autogen" subdirectories.

Signed-off-by: Philipp Wagner <[email protected]>
    @imphil
    imphil committed Oct 6, 2021
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  2. Setup hw/ip_templates directory 

    The hw/ip_templates directory is meant to host IP templates, which can
be used after they have been rendered through ipgen. Since those
templates may contain partial FuseSoC core files, but are not meant to
be used as template, we add a FUSESOC_IGNORE file, excluding the
directory from the core search path.

Signed-off-by: Philipp Wagner <[email protected]>
    @imphil
    imphil committed Oct 6, 2021
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  3. [doc] Add auto-generated top_earlgrey files in doc 

    Signed-off-by: Philipp Wagner <[email protected]>
    @imphil
    imphil committed Oct 6, 2021
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  4. [rv_plic] Produce top_earlgrey instance of rv_plic with ipgen 

    This rather large commit makes rv_plic an IP template, and then uses
ipgen to instantiate the block with the right parametrization for
top_earlgrey.

In contrast to the previous approach, `hw/top_earlgrey/ip_autogen`
now contains a full copy of rv_plic under a unique FuseSoC core
name, `lowrisc:opentitan:top_earlgrey_rv_plic`.

Unfortunately, doing so requires a fair amount of reshuffling, which
cannot be easily split into individual commits while keeping the whole
tree building. Here's what was done:

* Move `ip/rv_plic` to `ip_templates/rv_plic`.
* Remove the `reg_rv_plic.py` tooling, which is now replaced by ipgen.
* Change `topgen.py` to generate the toplevel-specific instance of
  `rv_plic` through ipgen.
* Adjust references in the documentation as necessary.
* Adjust the software build as necessary.
* The FPV testbench is now only run for the Earl Grey-instantiated IP
  block, there is no more "generic" testbench. Update all references
  pointing to the testbench.

Signed-off-by: Philipp Wagner <[email protected]>
    @imphil
    imphil committed Oct 6, 2021
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