From 3d165f88c18b456a28eee373ac3f5381b744aeeb Mon Sep 17 00:00:00 2001 From: Hakim Filali Date: Tue, 12 Mar 2024 13:05:35 +0000 Subject: [PATCH] [csrng/rtl] Change and assign cmd_sts signal This commit changes the sw_cmd_sts and hw_cmd_sts signals to multiple bits. 0 represents a successful acknowledgement, whereas any value other than 0 represents an error status. The sts signal is now also able to anounce to the EDN that the CSRNG main SM is hanging due to an invalid acmd. This commit also aligns the EDN rtl with the new sts response. Furthermore a new csrng interface pkg is created to avoid circular dependencies. This commit also aligns the EDN and CSRNG DV, documentation and SW with the new STS signal. Signed-off-by: Hakim Filali --- hw/dv/sv/csrng_agent/csrng_agent_cfg.sv | 16 +-- hw/dv/sv/csrng_agent/csrng_device_driver.sv | 4 +- hw/dv/sv/csrng_agent/csrng_if.sv | 3 +- hw/ip/csrng/data/csrng.hjson | 39 ++++-- hw/ip/csrng/doc/registers.md | 39 ++++-- hw/ip/csrng/rtl/csrng_cmd_stage.sv | 10 +- hw/ip/csrng/rtl/csrng_core.sv | 130 +++++++++++--------- hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv | 11 +- hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv | 16 +-- hw/ip/csrng/rtl/csrng_pkg.sv | 15 ++- hw/ip/csrng/rtl/csrng_reg_pkg.sv | 8 +- hw/ip/csrng/rtl/csrng_reg_top.sv | 41 +++++- hw/ip/csrng/rtl/csrng_state_db.sv | 12 +- hw/ip/edn/data/edn.hjson | 46 ++++--- hw/ip/edn/doc/registers.md | 60 ++++----- hw/ip/edn/dv/cov/edn_cov_if.sv | 24 ++-- hw/ip/edn/dv/env/edn_env_cfg.sv | 14 ++- hw/ip/edn/dv/env/edn_env_pkg.sv | 14 ++- hw/ip/edn/dv/env/edn_scoreboard.sv | 11 +- hw/ip/edn/dv/env/seq_lib/edn_alert_vseq.sv | 26 ++-- hw/ip/edn/dv/tests/edn_base_test.sv | 3 +- hw/ip/edn/rtl/edn_core.sv | 16 +-- hw/ip/edn/rtl/edn_reg_pkg.sv | 22 ++-- hw/ip/edn/rtl/edn_reg_top.sv | 70 +++++------ sw/device/lib/crypto/drivers/entropy.c | 10 +- sw/device/lib/dif/dif_csrng.c | 86 +------------ sw/device/lib/dif/dif_csrng.h | 33 +++-- sw/device/lib/dif/dif_csrng_unittest.cc | 49 +++----- sw/device/lib/dif/dif_edn.c | 14 +-- sw/device/lib/dif/dif_edn_unittest.cc | 76 +++++++----- sw/device/lib/testing/csrng_testutils.c | 4 +- sw/device/lib/testing/entropy_testutils.c | 6 +- 32 files changed, 491 insertions(+), 437 deletions(-) diff --git a/hw/dv/sv/csrng_agent/csrng_agent_cfg.sv b/hw/dv/sv/csrng_agent/csrng_agent_cfg.sv index a7a7e0bb9f317..3e654c23a8908 100644 --- a/hw/dv/sv/csrng_agent/csrng_agent_cfg.sv +++ b/hw/dv/sv/csrng_agent/csrng_agent_cfg.sv @@ -15,13 +15,13 @@ class csrng_agent_cfg extends dv_base_agent_cfg; `uvm_object_new - uint min_cmd_ack_dly, max_cmd_ack_dly, - min_genbits_dly, max_genbits_dly, - min_genbits_rdy_dly, max_genbits_rdy_dly, - min_cmd_rdy_dly, max_cmd_rdy_dly, - reseed_cnt, generate_cnt, generate_between_reseeds_cnt; - bit cmd_zero_delays; - bit under_reset; - bit rsp_sts_err; + uint min_cmd_ack_dly, max_cmd_ack_dly, + min_genbits_dly, max_genbits_dly, + min_genbits_rdy_dly, max_genbits_rdy_dly, + min_cmd_rdy_dly, max_cmd_rdy_dly, + reseed_cnt, generate_cnt, generate_between_reseeds_cnt; + bit cmd_zero_delays; + bit under_reset; + csrng_cmd_sts_e rsp_sts_err; endclass diff --git a/hw/dv/sv/csrng_agent/csrng_device_driver.sv b/hw/dv/sv/csrng_agent/csrng_device_driver.sv index ee13f0a4a3e57..d2fa2b80c146a 100644 --- a/hw/dv/sv/csrng_agent/csrng_device_driver.sv +++ b/hw/dv/sv/csrng_agent/csrng_device_driver.sv @@ -16,7 +16,7 @@ class csrng_device_driver extends csrng_driver; virtual task reset_signals(); cfg.vif.cmd_rsp_int.csrng_rsp_ack <= 1'b0; - cfg.vif.cmd_rsp_int.csrng_rsp_sts <= 1'b0; + cfg.vif.cmd_rsp_int.csrng_rsp_sts <= CMD_STS_SUCCESS; endtask // drive trans received from sequencer @@ -35,7 +35,7 @@ class csrng_device_driver extends csrng_driver; cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= cfg.rsp_sts_err; @(cfg.vif.device_cb); cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_ack <= 1'b0; - cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= 1'b0;, + cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= CMD_STS_SUCCESS;, wait (cfg.under_reset == 1);) // Write ack bit again in case the race condition with `reset_signals`. diff --git a/hw/dv/sv/csrng_agent/csrng_if.sv b/hw/dv/sv/csrng_agent/csrng_if.sv index 926c289ec1e1a..74e564af6b963 100644 --- a/hw/dv/sv/csrng_agent/csrng_if.sv +++ b/hw/dv/sv/csrng_agent/csrng_if.sv @@ -30,7 +30,8 @@ interface csrng_if (input clk, input rst_n); assign cmd_push_if.valid = (if_mode == dv_utils_pkg::Device) ? cmd_req.csrng_req_valid : 'z; assign cmd_push_if.h_data = (if_mode == dv_utils_pkg::Device) ? cmd_req.csrng_req_bus : 'z; assign cmd_rsp.csrng_rsp_ack = (if_mode == dv_utils_pkg::Device) ? cmd_rsp_int.csrng_rsp_ack : 'z; - assign cmd_rsp.csrng_rsp_sts = (if_mode == dv_utils_pkg::Device) ? cmd_rsp_int.csrng_rsp_sts : 'z; + assign cmd_rsp.csrng_rsp_sts = (if_mode == dv_utils_pkg::Device) ? + cmd_rsp_int.csrng_rsp_sts : CMD_STS_UNDRIVEN; assign genbits_push_if.ready = (if_mode == dv_utils_pkg::Device) ? cmd_req.genbits_ready : 'z; assign cmd_rsp.genbits_valid = (if_mode == dv_utils_pkg::Device) ? genbits_push_if.valid : 'z; diff --git a/hw/ip/csrng/data/csrng.hjson b/hw/ip/csrng/data/csrng.hjson index ee23aca6c3bfe..2b91b1ec9b1e3 100644 --- a/hw/ip/csrng/data/csrng.hjson +++ b/hw/ip/csrng/data/csrng.hjson @@ -325,20 +325,45 @@ tags: [// Internal HW can modify status register "excl:CsrNonInitTests:CsrExclCheck"] fields: [ - { bits: "0", + { bits: "1", name: "CMD_RDY", - desc: '''This bit indicates when the command interface is ready to accept commands. + desc: ''' + This bit indicates when the command interface is ready to accept commands. + Before starting to write a new command to !!SW_CMD_REQ, this field needs to be polled. + 0b0: CSRNG is not ready to accept commands or the last command hasn't been acked yet. + 0b1: CSRNG is ready to accept the next command. ''' - resval: "1" + resval: "0" } - { bits: "1", + { bits: "2", + name: "CMD_ACK", + desc: ''' + This one bit field indicates when a SW command has been acknowledged by the CSRNG. + It is set to low each time a new command is written to !!CMD_REQ. + The field is set to high once a SW command request has been acknowledged by the CSRNG. + 0b0: The last SW command has not been acknowledged yet. + 0b1: The last SW command has been acknowledged. + ''' + resval: "0" + } + { bits: "4:3", name: "CMD_STS", desc: ''' - This one bit field is the status code returned with the application command ack. + This field represents the status code returned with the application command ack. It is updated each time a command ack is asserted on the internal application interface for software use. - 0b0: Request completed successfully - 0b1: Request completed with an error + To check whether a command was succesful, wait for !!INTR_STATE.CS_CMD_REQ_DONE or + !!SW_CMD_STS.CMD_ACK to be high and then check the value of this field. + 0x0: Request completed successfully. + 0x1: Request completed with an invalid application command error. + This error indicates that the issued application command doesn't represent a valid operation. + If this error appears, the main state machine will hang and the entropy complex has to be restarted. + 0x2: Request completed with an invalid state parameter error. + This error indicates that the state wasn't zeroized properly after an uninstantiate command. + In this case the entropy complex should be restarted to properly zeroize the state. + 0x3: Request completed with an invalid counter drbg generation command error. + This error indicates that CSRNG entropy was generated for a command that is not a generate command. + In this case the entropy should not be considered as valid. ''' resval: "0" } diff --git a/hw/ip/csrng/doc/registers.md b/hw/ip/csrng/doc/registers.md index f038827e7c1b2..4d8e7fd907fca 100644 --- a/hw/ip/csrng/doc/registers.md +++ b/hw/ip/csrng/doc/registers.md @@ -157,30 +157,51 @@ Command request register ## SW_CMD_STS Application interface command status register - Offset: `0x1c` -- Reset default: `0x1` -- Reset mask: `0x3` +- Reset default: `0x0` +- Reset mask: `0x1e` ### Fields ```wavejson -{"reg": [{"name": "CMD_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +{"reg": [{"bits": 1}, {"name": "CMD_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_ACK", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} ``` | Bits | Type | Reset | Name | |:------:|:------:|:-------:|:--------------------------------| -| 31:2 | | | Reserved | -| 1 | ro | 0x0 | [CMD_STS](#sw_cmd_sts--cmd_sts) | -| 0 | ro | 0x1 | [CMD_RDY](#sw_cmd_sts--cmd_rdy) | +| 31:5 | | | Reserved | +| 4:3 | ro | 0x0 | [CMD_STS](#sw_cmd_sts--cmd_sts) | +| 2 | ro | 0x0 | [CMD_ACK](#sw_cmd_sts--cmd_ack) | +| 1 | ro | 0x0 | [CMD_RDY](#sw_cmd_sts--cmd_rdy) | ### SW_CMD_STS . CMD_STS -This one bit field is the status code returned with the application command ack. +This field represents the status code returned with the application command ack. It is updated each time a command ack is asserted on the internal application interface for software use. -0b0: Request completed successfully -0b1: Request completed with an error +To check whether a command was succesful, wait for [`INTR_STATE.CS_CMD_REQ_DONE`](#intr_state) or +[`SW_CMD_STS.CMD_ACK`](#sw_cmd_sts) to be high and then check the value of this field. +0x0: Request completed successfully. +0x1: Request completed with an invalid application command error. + This error indicates that the issued application command doesn't represent a valid operation. + If this error appears, the main state machine will hang and the entropy complex has to be restarted. +0x2: Request completed with an invalid state parameter error. + This error indicates that the state wasn't zeroized properly after an uninstantiate command. + In this case the entropy complex should be restarted to properly zeroize the state. +0x3: Request completed with an invalid counter drbg generation command error. + This error indicates that CSRNG entropy was generated for a command that is not a generate command. + In this case the entropy should not be considered as valid. + +### SW_CMD_STS . CMD_ACK +This one bit field indicates when a SW command has been acknowledged by the CSRNG. +It is set to low each time a new command is written to [`CMD_REQ.`](#cmd_req) +The field is set to high once a SW command request has been acknowledged by the CSRNG. +0b0: The last SW command has not been acknowledged yet. +0b1: The last SW command has been acknowledged. ### SW_CMD_STS . CMD_RDY This bit indicates when the command interface is ready to accept commands. +Before starting to write a new command to [`SW_CMD_REQ`](#sw_cmd_req), this field needs to be polled. +0b0: CSRNG is not ready to accept commands or the last command hasn't been acked yet. +0b1: CSRNG is ready to accept the next command. ## GENBITS_VLD Generate bits returned valid register diff --git a/hw/ip/csrng/rtl/csrng_cmd_stage.sv b/hw/ip/csrng/rtl/csrng_cmd_stage.sv index 4af7fd2abeb64..449eca5e1d63a 100644 --- a/hw/ip/csrng/rtl/csrng_cmd_stage.sv +++ b/hw/ip/csrng/rtl/csrng_cmd_stage.sv @@ -27,10 +27,10 @@ module csrng_cmd_stage import csrng_pkg::*; #( output logic [CmdFifoWidth-1:0] cmd_arb_bus_o, // Ack from core. input logic cmd_ack_i, - input logic cmd_ack_sts_i, + input csrng_cmd_sts_e cmd_ack_sts_i, // Ack to app i/f. output logic cmd_stage_ack_o, - output logic cmd_stage_ack_sts_o, + output csrng_cmd_sts_e cmd_stage_ack_sts_o, // Genbits from core. input logic genbits_vld_i, input logic [127:0] genbits_bus_i, @@ -85,7 +85,7 @@ module csrng_cmd_stage import csrng_pkg::*; #( // Flops. logic cmd_ack_q, cmd_ack_d; - logic cmd_ack_sts_q, cmd_ack_sts_d; + csrng_cmd_sts_e cmd_ack_sts_q, cmd_ack_sts_d; logic [3:0] cmd_len_q, cmd_len_d; logic cmd_gen_flag_q, cmd_gen_flag_d; logic [11:0] cmd_gen_cmd_q, cmd_gen_cmd_d; @@ -96,7 +96,7 @@ module csrng_cmd_stage import csrng_pkg::*; #( always_ff @(posedge clk_i or negedge rst_ni) if (!rst_ni) begin cmd_ack_q <= '0; - cmd_ack_sts_q <= '0; + cmd_ack_sts_q <= CMD_STS_SUCCESS; cmd_len_q <= '0; cmd_gen_flag_q <= '0; cmd_gen_cmd_q <= '0; @@ -413,7 +413,7 @@ module csrng_cmd_stage import csrng_pkg::*; #( assign cmd_stage_ack_o = cmd_ack_q; assign cmd_ack_sts_d = - (!cs_enable_i) ? '0 : + (!cs_enable_i) ? CMD_STS_SUCCESS : cmd_final_ack ? cmd_ack_sts_i : cmd_ack_sts_q; diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv index bd39f37b7871d..2c09cfdecf8ae 100644 --- a/hw/ip/csrng/rtl/csrng_core.sv +++ b/hw/ip/csrng/rtl/csrng_core.sv @@ -106,7 +106,7 @@ module csrng_core import csrng_pkg::*; #( logic [KeyLen-1:0] state_db_wr_key; logic [BlkLen-1:0] state_db_wr_v; logic [CtrLen-1:0] state_db_wr_rc; - logic state_db_wr_sts; + csrng_cmd_sts_e state_db_wr_sts; logic state_db_wr_fips; logic [Cmd-1:0] state_db_wr_ccmd; @@ -125,7 +125,7 @@ module csrng_core import csrng_pkg::*; #( logic cmd_result_wr_req; logic cmd_result_ack; - logic cmd_result_ack_sts; + csrng_cmd_sts_e cmd_result_ack_sts; logic [Cmd-1:0] cmd_result_ccmd; logic cmd_result_ack_rdy; logic [StateId-1:0] cmd_result_inst_id; @@ -137,11 +137,11 @@ module csrng_core import csrng_pkg::*; #( logic [CtrLen-1:0] cmd_result_rc; logic state_db_sts_ack; - logic state_db_sts_sts; + csrng_cmd_sts_e state_db_sts_sts; logic [StateId-1:0] state_db_sts_id; logic gen_result_wr_req; - logic gen_result_ack_sts; + csrng_cmd_sts_e gen_result_ack_sts; logic gen_result_ack_rdy; logic [Cmd-1:0] gen_result_ccmd; logic [StateId-1:0] gen_result_inst_id; @@ -303,54 +303,54 @@ module csrng_core import csrng_pkg::*; #( logic ctr_drbg_upd_v_ctr_err; logic ctr_drbg_gen_v_ctr_err; - logic [NApps-1:0] cmd_stage_vld; - logic [StateId-1:0] cmd_stage_shid[NApps]; - logic [AppCmdWidth-1:0] cmd_stage_bus[NApps]; - logic [NApps-1:0] cmd_stage_rdy; - logic [NApps-1:0] cmd_arb_req; - logic [NApps-1:0] cmd_arb_gnt; - logic [$clog2(NApps)-1:0] cmd_arb_idx; - logic [NApps-1:0] cmd_arb_sop; - logic [NApps-1:0] cmd_arb_mop; - logic [NApps-1:0] cmd_arb_eop; - logic [AppCmdWidth-1:0] cmd_arb_bus[NApps]; - logic [NApps-1:0] cmd_core_ack; - logic [NApps-1:0] cmd_core_ack_sts; - logic [NApps-1:0] cmd_stage_ack; - logic [NApps-1:0] cmd_stage_ack_sts; - logic [NApps-1:0] genbits_core_vld; - logic [GenBitsWidth-1:0] genbits_core_bus[NApps]; - logic [NApps-1:0] genbits_core_fips; - logic [NApps-1:0] genbits_stage_vld; - logic [NApps-1:0] genbits_stage_fips; - logic [GenBitsWidth-1:0] genbits_stage_bus[NApps]; - logic [NApps-1:0] genbits_stage_rdy; - logic genbits_stage_vldo_sw; - logic genbits_stage_bus_rd_sw; - logic [31:0] genbits_stage_bus_sw; - logic genbits_stage_fips_sw; - - logic [15:0] hw_exception_sts; - logic [LcHwDebugCopies-1:0]lc_hw_debug_on_fo; - logic state_db_is_dump_en; - logic state_db_reg_rd_sel; - logic state_db_reg_rd_id_pulse; - logic [StateId-1:0] state_db_reg_rd_id; - logic [31:0] state_db_reg_rd_val; - - logic [30:0] err_code_test_bit; - logic ctr_drbg_upd_es_ack; - logic ctr_drbg_gen_es_ack; - logic block_encrypt_quiet; - - logic cs_rdata_capt_vld; - logic cs_bus_cmp_alert; - logic cmd_rdy; - logic [1:0] efuse_sw_app_enable; - - logic unused_err_code_test_bit; - logic unused_reg2hw_genbits; - logic unused_int_state_val; + logic [NApps-1:0] cmd_stage_vld; + logic [StateId-1:0] cmd_stage_shid[NApps]; + logic [AppCmdWidth-1:0] cmd_stage_bus[NApps]; + logic [NApps-1:0] cmd_stage_rdy; + logic [NApps-1:0] cmd_arb_req; + logic [NApps-1:0] cmd_arb_gnt; + logic [$clog2(NApps)-1:0] cmd_arb_idx; + logic [NApps-1:0] cmd_arb_sop; + logic [NApps-1:0] cmd_arb_mop; + logic [NApps-1:0] cmd_arb_eop; + logic [AppCmdWidth-1:0] cmd_arb_bus[NApps]; + logic [NApps-1:0] cmd_core_ack; + csrng_cmd_sts_e [NApps-1:0] cmd_core_ack_sts; + logic [NApps-1:0] cmd_stage_ack; + csrng_cmd_sts_e [NApps-1:0] cmd_stage_ack_sts; + logic [NApps-1:0] genbits_core_vld; + logic [GenBitsWidth-1:0] genbits_core_bus[NApps]; + logic [NApps-1:0] genbits_core_fips; + logic [NApps-1:0] genbits_stage_vld; + logic [NApps-1:0] genbits_stage_fips; + logic [GenBitsWidth-1:0] genbits_stage_bus[NApps]; + logic [NApps-1:0] genbits_stage_rdy; + logic genbits_stage_vldo_sw; + logic genbits_stage_bus_rd_sw; + logic [31:0] genbits_stage_bus_sw; + logic genbits_stage_fips_sw; + + logic [15:0] hw_exception_sts; + logic [LcHwDebugCopies-1:0] lc_hw_debug_on_fo; + logic state_db_is_dump_en; + logic state_db_reg_rd_sel; + logic state_db_reg_rd_id_pulse; + logic [StateId-1:0] state_db_reg_rd_id; + logic [31:0] state_db_reg_rd_val; + + logic [30:0] err_code_test_bit; + logic ctr_drbg_upd_es_ack; + logic ctr_drbg_gen_es_ack; + logic block_encrypt_quiet; + + logic cs_rdata_capt_vld; + logic cs_bus_cmp_alert; + logic cmd_rdy; + logic [1:0] efuse_sw_app_enable; + + logic unused_err_code_test_bit; + logic unused_reg2hw_genbits; + logic unused_int_state_val; prim_mubi_pkg::mubi8_t [1:0] en_csrng_sw_app_read; prim_mubi_pkg::mubi4_t [CsEnableCopies-1:0] mubi_cs_enable_fanout; @@ -372,6 +372,7 @@ module csrng_core import csrng_pkg::*; #( logic [63:0] cs_rdata_capt_q, cs_rdata_capt_d; logic cs_rdata_capt_vld_q, cs_rdata_capt_vld_d; logic sw_rdy_sts_q, sw_rdy_sts_d; + logic sw_sts_ack_q, sw_sts_ack_d; always_ff @(posedge clk_i or negedge rst_ni) if (!rst_ni) begin @@ -390,6 +391,7 @@ module csrng_core import csrng_pkg::*; #( cs_rdata_capt_q <= '0; cs_rdata_capt_vld_q <= '0; sw_rdy_sts_q <= '0; + sw_sts_ack_q <= '0; end else begin acmd_q <= acmd_d; shid_q <= shid_d; @@ -406,6 +408,7 @@ module csrng_core import csrng_pkg::*; #( cs_rdata_capt_q <= cs_rdata_capt_d; cs_rdata_capt_vld_q <= cs_rdata_capt_vld_d; sw_rdy_sts_q <= sw_rdy_sts_d; + sw_sts_ack_q <= sw_sts_ack_d; end //-------------------------------------------- @@ -870,14 +873,23 @@ module csrng_core import csrng_pkg::*; #( assign hw2reg.sw_cmd_sts.cmd_rdy.d = cmd_rdy; assign cmd_rdy = !cmd_stage_vld[NApps-1] && sw_rdy_sts_q; assign sw_rdy_sts_d = - !cs_enable_fo[28] ? 1'b1 : + !cs_enable_fo[28] ? 1'b0 : cmd_stage_vld[NApps-1] ? 1'b0 : cmd_stage_rdy[NApps-1] ? 1'b1 : sw_rdy_sts_q; - + // cmd sts ack + assign hw2reg.sw_cmd_sts.cmd_ack.de = 1'b1; + assign hw2reg.sw_cmd_sts.cmd_ack.d = sw_sts_ack_d; + assign sw_sts_ack_d = + !cs_enable_fo[28] ? 1'b0 : + cmd_stage_vld[NApps-1] ? 1'b0 : + cmd_stage_ack[NApps-1] ? 1'b1 : + sw_sts_ack_q; // cmd ack sts - assign hw2reg.sw_cmd_sts.cmd_sts.de = cmd_stage_ack[NApps-1]; - assign hw2reg.sw_cmd_sts.cmd_sts.d = cmd_stage_ack_sts[NApps-1]; + assign hw2reg.sw_cmd_sts.cmd_sts.de = (cs_main_sm_alert && (shid_q == StateId'(NApps-1))) || + cmd_stage_ack[NApps-1]; + assign hw2reg.sw_cmd_sts.cmd_sts.d = (cs_main_sm_alert && (shid_q == StateId'(NApps-1))) ? + CMD_STS_INVALID_ACMD : cmd_stage_ack_sts[NApps-1]; // genbits assign hw2reg.genbits_vld.genbits_vld.d = genbits_stage_vldo_sw; assign hw2reg.genbits_vld.genbits_fips.d = genbits_stage_fips_sw; @@ -963,8 +975,10 @@ module csrng_core import csrng_pkg::*; #( assign cmd_stage_bus[hai] = csrng_cmd_i[hai].csrng_req_bus; assign csrng_cmd_o[hai].csrng_req_ready = cmd_stage_rdy[hai]; // cmd ack - assign csrng_cmd_o[hai].csrng_rsp_ack = cmd_stage_ack[hai]; - assign csrng_cmd_o[hai].csrng_rsp_sts = cmd_stage_ack_sts[hai]; + assign csrng_cmd_o[hai].csrng_rsp_ack = (cs_main_sm_alert && (shid_q == StateId'(hai))) || + cmd_stage_ack[hai]; + assign csrng_cmd_o[hai].csrng_rsp_sts = (cs_main_sm_alert && (shid_q == StateId'(hai))) ? + CMD_STS_INVALID_ACMD : cmd_stage_ack_sts[hai]; // genbits assign csrng_cmd_o[hai].genbits_valid = genbits_stage_vld[hai]; assign csrng_cmd_o[hai].genbits_fips = genbits_stage_fips[hai]; diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv index d4df09ade5b18..5e2231f59ab27 100644 --- a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv +++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv @@ -33,7 +33,7 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #( input logic ctr_drbg_cmd_fips_i, output logic ctr_drbg_cmd_ack_o, // final ack when update process has been completed - output logic ctr_drbg_cmd_sts_o, // final ack status + output csrng_cmd_sts_e ctr_drbg_cmd_sts_o, // final ack status input logic ctr_drbg_cmd_rdy_i, // ready to process the ack above output logic [Cmd-1:0] ctr_drbg_cmd_ccmd_o, output logic [StateId-1:0] ctr_drbg_cmd_inst_id_o, @@ -71,6 +71,7 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #( localparam int RCStageFifoWidth = KeyLen+BlkLen+StateId+CtrLen+1+SeedLen+1+Cmd; localparam int KeyVRCFifoDepth = 1; localparam int KeyVRCFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd; + localparam int UniZeroizeWidth = KeyLen+BlkLen+CtrLen+1+SeedLen; // signals @@ -98,6 +99,7 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #( logic [SeedLen-1:0] rcstage_adata; logic rcstage_fips; logic fips_modified; + logic ctr_drbg_cmd_sts_err; // cmdreq fifo logic [CmdreqFifoWidth-1:0] sfifo_cmdreq_rdata; @@ -318,8 +320,11 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #( // block ack assign ctr_drbg_cmd_ack_o = sfifo_keyvrc_pop; - assign ctr_drbg_cmd_sts_o = sfifo_keyvrc_pop && (ctr_drbg_cmd_ccmd_o == UNI) && - ((KeyLen == '0) && (BlkLen == '0) && (CtrLen == '0)); + // Return a status error when the state is not zeroized properly during a UNI command. + assign ctr_drbg_cmd_sts_err = sfifo_keyvrc_pop && (ctr_drbg_cmd_ccmd_o == UNI) && + (sfifo_keyvrc_wdata >> (KeyVRCFifoWidth-UniZeroizeWidth)) == '0; + + assign ctr_drbg_cmd_sts_o = ctr_drbg_cmd_sts_err ? CMD_STS_INVALID_STATE_PARAM : CMD_STS_SUCCESS; endmodule diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv index c02272a39748a..69b201a0c47ad 100644 --- a/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv +++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv @@ -34,7 +34,7 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #( input logic [CtrLen-1:0] ctr_drbg_gen_rc_i, output logic ctr_drbg_gen_ack_o, // final ack when update process has been completed - output logic ctr_drbg_gen_sts_o, // final ack status + output csrng_cmd_sts_e ctr_drbg_gen_sts_o, // final ack status input logic ctr_drbg_gen_rdy_i, // ready to process the ack above output logic [Cmd-1:0] ctr_drbg_gen_ccmd_o, output logic [StateId-1:0] ctr_drbg_gen_inst_id_o, @@ -181,6 +181,9 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #( logic [SeedLen-1:0] update_adata[NApps]; logic [CtrLen-1:0] v_ctr; + // status error signals + logic ctr_drbg_gen_sts_err; + // flops logic [1:0] interate_ctr_q, interate_ctr_d; logic [SeedLen-1:0] update_adata_q[NApps], update_adata_d[NApps]; @@ -588,12 +591,11 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #( // block ack assign ctr_drbg_gen_ack_o = sfifo_genbits_pop; - assign ctr_drbg_gen_sts_o = sfifo_genbits_pop && ( - (ctr_drbg_gen_ccmd_o == INV) || - (ctr_drbg_gen_ccmd_o == INS) || - (ctr_drbg_gen_ccmd_o == RES) || - (ctr_drbg_gen_ccmd_o == UPD) || - (ctr_drbg_gen_ccmd_o == UNI)); + // Return a status error when the genbits FIFO is popped while ctr_drbg_gen_ccmd_o is not + // equal to GEN. + assign ctr_drbg_gen_sts_err = sfifo_genbits_pop && (ctr_drbg_gen_ccmd_o != GEN); + + assign ctr_drbg_gen_sts_o = ctr_drbg_gen_sts_err ? CMD_STS_INVALID_GEN_CMD : CMD_STS_SUCCESS; // Make sure that the state machine has a stable error state. This means that after the error // state is entered it will not exit it unless a reset signal is received. diff --git a/hw/ip/csrng/rtl/csrng_pkg.sv b/hw/ip/csrng/rtl/csrng_pkg.sv index 86db5855c351c..0aa5e12cd6c1c 100644 --- a/hw/ip/csrng/rtl/csrng_pkg.sv +++ b/hw/ip/csrng/rtl/csrng_pkg.sv @@ -14,6 +14,7 @@ package csrng_pkg; parameter int unsigned FIPS_GENBITS_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH + GENBITS_BUS_WIDTH; parameter int unsigned MainSmStateWidth = 8; + parameter int unsigned CSRNG_CMD_STS_WIDTH = 2; // instantiation interface typedef struct packed { @@ -22,17 +23,25 @@ package csrng_pkg; logic genbits_ready; } csrng_req_t; + typedef enum logic [CSRNG_CMD_STS_WIDTH-1:0] { + CMD_STS_SUCCESS = 2'h0, + CMD_STS_INVALID_ACMD = 2'h1, + CMD_STS_INVALID_STATE_PARAM = 2'h2, + CMD_STS_INVALID_GEN_CMD = 2'h3, + CMD_STS_UNDRIVEN = 'z + } csrng_cmd_sts_e; + typedef struct packed { logic csrng_req_ready; logic csrng_rsp_ack; - logic csrng_rsp_sts; + csrng_cmd_sts_e csrng_rsp_sts; logic genbits_valid; logic genbits_fips; logic [GENBITS_BUS_WIDTH-1:0] genbits_bus; } csrng_rsp_t; parameter csrng_req_t CSRNG_REQ_DEFAULT = '{default: '0}; - parameter csrng_rsp_t CSRNG_RSP_DEFAULT = '{default: '0}; + parameter csrng_rsp_t CSRNG_RSP_DEFAULT = '0; typedef enum logic [2:0] { INV = 3'h0, @@ -76,7 +85,7 @@ package csrng_pkg; // Minimum Hamming weight: 1 // Maximum Hamming weight: 7 // - typedef enum logic [MainSmStateWidth-1:0] { + typedef enum logic [MainSmStateWidth-1:0] { MainSmIdle = 8'b01001110, // idle MainSmParseCmd = 8'b10111011, // parse the cmd MainSmInstantPrep = 8'b11000001, // instantiate prep diff --git a/hw/ip/csrng/rtl/csrng_reg_pkg.sv b/hw/ip/csrng/rtl/csrng_reg_pkg.sv index e2f4d9e212080..13d86f732d3c5 100644 --- a/hw/ip/csrng/rtl/csrng_reg_pkg.sv +++ b/hw/ip/csrng/rtl/csrng_reg_pkg.sv @@ -140,6 +140,10 @@ package csrng_reg_pkg; struct packed { logic d; logic de; + } cmd_ack; + struct packed { + logic [1:0] d; + logic de; } cmd_sts; } csrng_hw2reg_sw_cmd_sts_reg_t; @@ -320,8 +324,8 @@ package csrng_reg_pkg; // HW -> register type typedef struct packed { - csrng_hw2reg_intr_state_reg_t intr_state; // [167:160] - csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [159:156] + csrng_hw2reg_intr_state_reg_t intr_state; // [170:163] + csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [162:156] csrng_hw2reg_genbits_vld_reg_t genbits_vld; // [155:154] csrng_hw2reg_genbits_reg_t genbits; // [153:122] csrng_hw2reg_int_state_val_reg_t int_state_val; // [121:90] diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv index 18705f67b7259..68284be8d2862 100644 --- a/hw/ip/csrng/rtl/csrng_reg_top.sv +++ b/hw/ip/csrng/rtl/csrng_reg_top.sv @@ -160,7 +160,8 @@ module csrng_reg_top ( logic cmd_req_we; logic [31:0] cmd_req_wd; logic sw_cmd_sts_cmd_rdy_qs; - logic sw_cmd_sts_cmd_sts_qs; + logic sw_cmd_sts_cmd_ack_qs; + logic [1:0] sw_cmd_sts_cmd_sts_qs; logic genbits_vld_re; logic genbits_vld_genbits_vld_qs; logic genbits_vld_genbits_fips_qs; @@ -700,11 +701,11 @@ module csrng_reg_top ( // R[sw_cmd_sts]: V(False) - // F[cmd_rdy]: 0:0 + // F[cmd_rdy]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h1), + .RESVAL (1'h0), .Mubi (1'b0) ) u_sw_cmd_sts_cmd_rdy ( .clk_i (clk_i), @@ -727,12 +728,39 @@ module csrng_reg_top ( .qs (sw_cmd_sts_cmd_rdy_qs) ); - // F[cmd_sts]: 1:1 + // F[cmd_ack]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) + ) u_sw_cmd_sts_cmd_ack ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.sw_cmd_sts.cmd_ack.de), + .d (hw2reg.sw_cmd_sts.cmd_ack.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_cmd_sts_cmd_ack_qs) + ); + + // F[cmd_sts]: 4:3 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (2'h0), + .Mubi (1'b0) ) u_sw_cmd_sts_cmd_sts ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -2012,8 +2040,9 @@ module csrng_reg_top ( end addr_hit[7]: begin - reg_rdata_next[0] = sw_cmd_sts_cmd_rdy_qs; - reg_rdata_next[1] = sw_cmd_sts_cmd_sts_qs; + reg_rdata_next[1] = sw_cmd_sts_cmd_rdy_qs; + reg_rdata_next[2] = sw_cmd_sts_cmd_ack_qs; + reg_rdata_next[4:3] = sw_cmd_sts_cmd_sts_qs; end addr_hit[8]: begin diff --git a/hw/ip/csrng/rtl/csrng_state_db.sv b/hw/ip/csrng/rtl/csrng_state_db.sv index 7d2d1d2edad7e..df29c64e9a788 100644 --- a/hw/ip/csrng/rtl/csrng_state_db.sv +++ b/hw/ip/csrng/rtl/csrng_state_db.sv @@ -37,7 +37,7 @@ module csrng_state_db import csrng_pkg::*; #( input logic [KeyLen-1:0] state_db_wr_key_i, input logic [BlkLen-1:0] state_db_wr_v_i, input logic [CtrLen-1:0] state_db_wr_res_ctr_i, - input logic state_db_wr_sts_i, + input csrng_cmd_sts_e state_db_wr_sts_i, // status interface input logic state_db_is_dump_en_i, input logic state_db_reg_rd_sel_i, @@ -45,14 +45,14 @@ module csrng_state_db import csrng_pkg::*; #( input logic [StateId-1:0] state_db_reg_rd_id_i, output logic [31:0] state_db_reg_rd_val_o, output logic state_db_sts_ack_o, - output logic state_db_sts_sts_o, + output csrng_cmd_sts_e state_db_sts_sts_o, output logic [StateId-1:0] state_db_sts_id_o ); localparam int InternalStateWidth = 2+KeyLen+BlkLen+CtrLen; localparam int RegInternalStateWidth = 30+InternalStateWidth; localparam int RegW = 32; - localparam int StateWidth = 1+1+KeyLen+BlkLen+CtrLen+StateId+1; + localparam int StateWidth = 1+1+KeyLen+BlkLen+CtrLen+StateId+CSRNG_CMD_STS_WIDTH; logic [StateId-1:0] state_db_id; logic [KeyLen-1:0] state_db_key; @@ -60,7 +60,7 @@ module csrng_state_db import csrng_pkg::*; #( logic [CtrLen-1:0] state_db_rc; logic state_db_fips; logic state_db_inst_st; - logic state_db_sts; + csrng_cmd_sts_e state_db_sts; logic state_db_write; logic instance_status; logic [NApps-1:0] int_st_out_sel; @@ -74,7 +74,7 @@ module csrng_state_db import csrng_pkg::*; #( // flops logic state_db_sts_ack_q, state_db_sts_ack_d; - logic state_db_sts_sts_q, state_db_sts_sts_d; + csrng_cmd_sts_e state_db_sts_sts_q, state_db_sts_sts_d; logic [StateId-1:0] state_db_sts_id_q, state_db_sts_id_d; logic [StateId-1:0] reg_rd_ptr_q, reg_rd_ptr_d; logic [StateId-1:0] int_st_dump_id_q, int_st_dump_id_d; @@ -82,7 +82,7 @@ module csrng_state_db import csrng_pkg::*; #( always_ff @(posedge clk_i or negedge rst_ni) if (!rst_ni) begin state_db_sts_ack_q <= '0; - state_db_sts_sts_q <= '0; + state_db_sts_sts_q <= CMD_STS_SUCCESS; state_db_sts_id_q <= '0; reg_rd_ptr_q <= '0; int_st_dump_id_q <= '0; diff --git a/hw/ip/edn/data/edn.hjson b/hw/ip/edn/data/edn.hjson index 46d162a6ca2da..34b8d632357a5 100644 --- a/hw/ip/edn/data/edn.hjson +++ b/hw/ip/edn/data/edn.hjson @@ -329,18 +329,6 @@ resval: "0" } { bits: "2", - name: "CMD_STS", - desc: ''' - This one bit field represents the status code returned with the CSRNG application command ack. - It is updated each time a SW command is acknowledged by CSRNG. - To check whether a command was succesful, wait for !!INTR_STATE.EDN_CMD_REQ_DONE or - !!SW_CMD_STS.CMD_ACK to be high and then check the value of this field. - 0b0: Request completed successfully. - 0b1: Request completed with an error. - ''' - resval: "0" - } - { bits: "3", name: "CMD_ACK", desc: ''' This one bit field indicates when a SW command has been acknowledged by the CSRNG. @@ -351,6 +339,17 @@ ''' resval: "0" } + { bits: "4:3", + name: "CMD_STS", + desc: ''' + This field represents the status code returned with the CSRNG application command ack. + It is updated each time a SW command is acknowledged by CSRNG. + To check whether a command was successful, wait for !!INTR_STATE.EDN_CMD_REQ_DONE or + !!SW_CMD_STS.CMD_ACK to be high and then check the value of this field. + A description of the command status types can be found [here](../../csrng/doc/registers.md#sw_cmd_sts--cmd_sts). + ''' + resval: "0" + } ] }, { name: "HW_CMD_STS", @@ -379,17 +378,16 @@ ''' resval: "0" } - { bits: "2", - name: "CMD_STS", + { bits: "5:2", + name: "CMD_TYPE", desc: ''' - This one bit field represents the status code returned with the CSRNG application command ack. - It is updated each time a HW command is acknowledged by CSRNG. - 0b0: Request completed successfully. - 0b1: Request completed with an error. + This field contains the application command type of the hardware controlled command issued last. + The application command selects one of five operations to perform. + A description of the application command types can be found [here](../../csrng/doc/theory_of_operation.md#command-description). ''' resval: "0" } - { bits: "3", + { bits: "6", name: "CMD_ACK", desc: ''' This one bit field indicates when a HW command has been acknowledged by the CSRNG. @@ -400,12 +398,12 @@ ''' resval: "0" } - { bits: "7:4", - name: "CMD_TYPE", + { bits: "8:7", + name: "CMD_STS", desc: ''' - This field contains the application command type of the hardware controlled command issued last. - The application command selects one of five operations to perform. - A description of the application command types can be found [here](https://opentitan.org/book/hw/ip/csrng/doc/theory_of_operation.html#command-description). + This field represents the status code returned with the CSRNG application command ack. + It is updated each time a HW command is acknowledged by CSRNG. + A description of the command status types can be found [here](../../csrng/doc/registers.md#sw_cmd_sts--cmd_sts). ''' resval: "0" } diff --git a/hw/ip/edn/doc/registers.md b/hw/ip/edn/doc/registers.md index e237332275bb1..2464c836f5888 100644 --- a/hw/ip/edn/doc/registers.md +++ b/hw/ip/edn/doc/registers.md @@ -1,3 +1,6 @@ +# Registers + + ## Summary | Name | Offset | Length | Description | @@ -224,22 +227,29 @@ in the CSRNG documentation. EDN software command status register - Offset: `0x24` - Reset default: `0x0` -- Reset mask: `0xf` +- Reset mask: `0x1f` ### Fields ```wavejson -{"reg": [{"name": "CMD_REG_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_ACK", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +{"reg": [{"name": "CMD_REG_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_ACK", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} ``` | Bits | Type | Reset | Name | |:------:|:------:|:-------:|:----------------------------------------| -| 31:4 | | | Reserved | -| 3 | ro | 0x0 | [CMD_ACK](#sw_cmd_sts--cmd_ack) | -| 2 | ro | 0x0 | [CMD_STS](#sw_cmd_sts--cmd_sts) | +| 31:5 | | | Reserved | +| 4:3 | ro | 0x0 | [CMD_STS](#sw_cmd_sts--cmd_sts) | +| 2 | ro | 0x0 | [CMD_ACK](#sw_cmd_sts--cmd_ack) | | 1 | ro | 0x0 | [CMD_RDY](#sw_cmd_sts--cmd_rdy) | | 0 | ro | 0x0 | [CMD_REG_RDY](#sw_cmd_sts--cmd_reg_rdy) | +### SW_CMD_STS . CMD_STS +This field represents the status code returned with the CSRNG application command ack. +It is updated each time a SW command is acknowledged by CSRNG. +To check whether a command was successful, wait for [`INTR_STATE.EDN_CMD_REQ_DONE`](#intr_state) or +[`SW_CMD_STS.CMD_ACK`](#sw_cmd_sts) to be high and then check the value of this field. +A description of the command status types can be found [here](../../csrng/doc/registers.md#sw_cmd_sts--cmd_sts). + ### SW_CMD_STS . CMD_ACK This one bit field indicates when a SW command has been acknowledged by the CSRNG. It is set to low each time a new command is written to [`SW_CMD_REQ.`](#sw_cmd_req) @@ -247,14 +257,6 @@ The field is set to high once a SW command request has been acknowledged by the 0b0: The last SW command has not been acknowledged yet. 0b1: The last SW command has been acknowledged. -### SW_CMD_STS . CMD_STS -This one bit field represents the status code returned with the CSRNG application command ack. -It is updated each time a SW command is acknowledged by CSRNG. -To check whether a command was succesful, wait for [`INTR_STATE.EDN_CMD_REQ_DONE`](#intr_state) or -[`SW_CMD_STS.CMD_ACK`](#sw_cmd_sts) to be high and then check the value of this field. -0b0: Request completed successfully. -0b1: Request completed with an error. - ### SW_CMD_STS . CMD_RDY This bit indicates when the EDN is ready to accept the next command. Before starting to write a new command to [`SW_CMD_REQ`](#sw_cmd_req), this field needs to be polled. @@ -271,27 +273,27 @@ This bit has to be polled before each word of a command is written to [`SW_CMD_R EDN hardware command status register - Offset: `0x28` - Reset default: `0x0` -- Reset mask: `0xff` +- Reset mask: `0x1ff` ### Fields ```wavejson -{"reg": [{"name": "BOOT_MODE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AUTO_MODE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_ACK", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_TYPE", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +{"reg": [{"name": "BOOT_MODE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AUTO_MODE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_TYPE", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "CMD_ACK", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} ``` | Bits | Type | Reset | Name | |:------:|:------:|:-------:|:------------------------------------| -| 31:8 | | | Reserved | -| 7:4 | ro | 0x0 | [CMD_TYPE](#hw_cmd_sts--cmd_type) | -| 3 | ro | 0x0 | [CMD_ACK](#hw_cmd_sts--cmd_ack) | -| 2 | ro | 0x0 | [CMD_STS](#hw_cmd_sts--cmd_sts) | +| 31:9 | | | Reserved | +| 8:7 | ro | 0x0 | [CMD_STS](#hw_cmd_sts--cmd_sts) | +| 6 | ro | 0x0 | [CMD_ACK](#hw_cmd_sts--cmd_ack) | +| 5:2 | ro | 0x0 | [CMD_TYPE](#hw_cmd_sts--cmd_type) | | 1 | ro | 0x0 | [AUTO_MODE](#hw_cmd_sts--auto_mode) | | 0 | ro | 0x0 | [BOOT_MODE](#hw_cmd_sts--boot_mode) | -### HW_CMD_STS . CMD_TYPE -This field contains the application command type of the hardware controlled command issued last. -The application command selects one of five operations to perform. -A description of the application command types can be found [here](https://opentitan.org/book/hw/ip/csrng/doc/theory_of_operation.html#command-description). +### HW_CMD_STS . CMD_STS +This field represents the status code returned with the CSRNG application command ack. +It is updated each time a HW command is acknowledged by CSRNG. +A description of the command status types can be found [here](../../csrng/doc/registers.md#sw_cmd_sts--cmd_sts). ### HW_CMD_STS . CMD_ACK This one bit field indicates when a HW command has been acknowledged by the CSRNG. @@ -300,11 +302,10 @@ The field is set to high once a HW command request has been acknowledged by the 0b0: The last HW command has not been acknowledged yet. 0b1: The last HW command has been acknowledged. -### HW_CMD_STS . CMD_STS -This one bit field represents the status code returned with the CSRNG application command ack. -It is updated each time a HW command is acknowledged by CSRNG. -0b0: Request completed successfully. -0b1: Request completed with an error. +### HW_CMD_STS . CMD_TYPE +This field contains the application command type of the hardware controlled command issued last. +The application command selects one of five operations to perform. +A description of the application command types can be found [here](../../csrng/doc/theory_of_operation.md#command-description). ### HW_CMD_STS . AUTO_MODE This one bit field indicates whether the EDN is in the hardware controlled part of auto mode. @@ -532,3 +533,6 @@ Main state machine state observation register |:------:|:------:|:-------:|:--------------|:---------------------------------------------------------------------------------------------------------------| | 31:9 | | | | Reserved | | 8:0 | ro | 0xc1 | MAIN_SM_STATE | This is the state of the EDN main state machine. See the RTL file `edn_main_sm` for the meaning of the values. | + + + diff --git a/hw/ip/edn/dv/cov/edn_cov_if.sv b/hw/ip/edn/dv/cov/edn_cov_if.sv index e2069e49a0d48..2450198860ecc 100644 --- a/hw/ip/edn/dv/cov/edn_cov_if.sv +++ b/hw/ip/edn/dv/cov/edn_cov_if.sv @@ -238,7 +238,8 @@ interface edn_cov_if ( endgroup : edn_cs_cmd_response_cg covergroup edn_sw_cmd_sts_cg with function sample(bit cmd_rdy, bit cmd_reg_rdy, - bit cmd_sts, bit cmd_ack); + csrng_pkg::csrng_cmd_sts_e cmd_sts, + bit cmd_ack); option.name = "edn_sw_cmd_sts_cg"; option.per_instance = 1; @@ -252,10 +253,7 @@ interface edn_cov_if ( bins not_ready = { 1'b0 }; } - cp_cmd_sts_cg: coverpoint cmd_sts { - bins error = { 1'b1 }; - bins success = { 1'b0 }; - } + cp_cmd_sts_cg: coverpoint cmd_sts; cp_cmd_ack_cg: coverpoint cmd_ack { bins ack = { 1'b1 }; @@ -264,8 +262,8 @@ interface edn_cov_if ( endgroup : edn_sw_cmd_sts_cg covergroup edn_hw_cmd_sts_cg with function sample(bit boot_mode, bit auto_mode, - bit cmd_sts, bit cmd_ack, - csrng_pkg::acmd_e acmd); + csrng_pkg::csrng_cmd_sts_e cmd_sts, + bit cmd_ack, csrng_pkg::acmd_e acmd); option.name = "edn_hw_cmd_sts_cg"; option.per_instance = 1; @@ -279,10 +277,7 @@ interface edn_cov_if ( bins not_auto_mode = { 1'b0 }; } - cp_cmd_sts: coverpoint cmd_sts { - bins error = { 1'b1 }; - bins success = { 1'b0 }; - } + cp_cmd_sts: coverpoint cmd_sts; cp_cmd_ack: coverpoint cmd_ack { bins ack = { 1'b1 }; @@ -368,13 +363,14 @@ interface edn_cov_if ( endfunction : cg_cs_cmd_response_sample function automatic void cg_edn_sw_cmd_sts_sample(bit cmd_rdy, bit cmd_reg_rdy, - bit cmd_sts, bit cmd_ack); + csrng_pkg::csrng_cmd_sts_e cmd_sts, + bit cmd_ack); edn_sw_cmd_sts_cg_inst.sample(cmd_rdy, cmd_reg_rdy, cmd_sts, cmd_ack); endfunction : cg_edn_sw_cmd_sts_sample function automatic void cg_edn_hw_cmd_sts_sample(bit boot_mode, bit auto_mode, - bit cmd_sts, bit cmd_ack, - csrng_pkg::acmd_e acmd); + csrng_pkg::csrng_cmd_sts_e cmd_sts, + bit cmd_ack, csrng_pkg::acmd_e acmd); edn_hw_cmd_sts_cg_inst.sample(boot_mode, auto_mode, cmd_sts, cmd_ack, acmd); endfunction : cg_edn_hw_cmd_sts_sample diff --git a/hw/ip/edn/dv/env/edn_env_cfg.sv b/hw/ip/edn/dv/env/edn_env_cfg.sv index ef53fd96a3e5e..86ba57650c56f 100644 --- a/hw/ip/edn/dv/env/edn_env_cfg.sv +++ b/hw/ip/edn/dv/env/edn_env_cfg.sv @@ -46,11 +46,12 @@ class edn_env_cfg extends cip_base_env_cfg #(.RAL_T(edn_reg_block)); rand bit force_disable; rand bit [csrng_pkg::CSRNG_CMD_WIDTH - 1:0] boot_ins_cmd, boot_gen_cmd; - rand fatal_err_e which_fatal_err; - rand err_code_e which_err_code; - rand which_fifo_e which_fifo; - rand which_fifo_err_e which_fifo_err; - rand invalid_mubi_e which_invalid_mubi; + rand fatal_err_e which_fatal_err; + rand err_code_e which_err_code; + rand which_fifo_e which_fifo; + rand which_fifo_err_e which_fifo_err; + rand invalid_mubi_e which_invalid_mubi; + rand csrng_pkg::csrng_cmd_sts_e which_cmd_sts_err; // Constraints constraint glen_auto_mode_c {glen_auto_mode dist { @@ -85,6 +86,9 @@ class edn_env_cfg extends cip_base_env_cfg #(.RAL_T(edn_reg_block)); // All other error codes will implicitly get a weight of 1. };} + // CMD_STS_SUCCESS is not an error so ignore it. + constraint which_cmd_sts_err_c {{which_cmd_sts_err != csrng_pkg::CMD_STS_SUCCESS};} + // Functions function void post_randomize(); if (use_invalid_mubi) begin diff --git a/hw/ip/edn/dv/env/edn_env_pkg.sv b/hw/ip/edn/dv/env/edn_env_pkg.sv index 867c22e109593..7ef4feff4779d 100644 --- a/hw/ip/edn/dv/env/edn_env_pkg.sv +++ b/hw/ip/edn/dv/env/edn_env_pkg.sv @@ -26,6 +26,8 @@ package edn_env_pkg; parameter uint MAX_NUM_ENDPOINTS = 7; parameter string LIST_OF_ALERTS[] = {"recov_alert","fatal_alert"}; parameter uint NUM_ALERTS = 2; + parameter uint CMD_STS_SIZE = 2; + parameter uint CMD_TYPE_SIZE = 4; // types typedef enum int { @@ -127,17 +129,17 @@ package edn_env_pkg; typedef enum int { sw_cmd_reg_rdy = 0, - sw_cmd_rdy = 1, - sw_cmd_sts = 2, - sw_cmd_ack = 3 + sw_cmd_rdy = 1, + sw_cmd_ack = 2, + sw_cmd_sts = 3 } sw_cmd_sts_e; typedef enum int { hw_cmd_boot_mode = 0, hw_cmd_auto_mode = 1, - hw_cmd_sts = 2, - hw_cmd_ack = 3, - hw_cmd_type = 4 + hw_cmd_type = 2, + hw_cmd_ack = 6, + hw_cmd_sts = 7 } hw_cmd_sts_e; // package sources diff --git a/hw/ip/edn/dv/env/edn_scoreboard.sv b/hw/ip/edn/dv/env/edn_scoreboard.sv index 8b13bd2cee557..25a88424a8a1a 100644 --- a/hw/ip/edn/dv/env/edn_scoreboard.sv +++ b/hw/ip/edn/dv/env/edn_scoreboard.sv @@ -239,7 +239,7 @@ class edn_scoreboard extends cip_base_scoreboard #( backdoor_disable_fifo_clr = 1'b0; reset_happened = 1'b0; sw_cmd_sts[sw_cmd_ack] = 1'b0; - sw_cmd_sts[sw_cmd_sts] = 1'b0; + sw_cmd_sts[sw_cmd_sts+:CMD_STS_SIZE-1] = csrng_pkg::CMD_STS_SUCCESS; sw_cmd_sts[sw_cmd_rdy] = !boot_mode; sw_cmd_sts[sw_cmd_reg_rdy] = !boot_mode; @@ -314,7 +314,8 @@ class edn_scoreboard extends cip_base_scoreboard #( $sformatf("reg name: %0s", csr.get_full_name())) if (cfg.en_cov) begin cov_vif.cg_edn_sw_cmd_sts_sample(item.d_data[sw_cmd_rdy], item.d_data[sw_cmd_reg_rdy], - item.d_data[sw_cmd_sts], item.d_data[sw_cmd_ack]); + csrng_pkg::csrng_cmd_sts_e'(item.d_data[sw_cmd_sts+:CMD_STS_SIZE]), + item.d_data[sw_cmd_ack]); end end end @@ -656,7 +657,7 @@ class edn_scoreboard extends cip_base_scoreboard #( if ((auto_mode && instantiated) || boot_mode) begin hw_cmd_sts = `gmv(ral.hw_cmd_sts); hw_cmd_sts[hw_cmd_ack] = 1'b0; - hw_cmd_sts[hw_cmd_type:+4] = acmd_cur; + hw_cmd_sts[hw_cmd_type+:CMD_TYPE_SIZE-1] = acmd_cur; void'(ral.hw_cmd_sts.predict(.value(hw_cmd_sts))); end end @@ -703,7 +704,7 @@ class edn_scoreboard extends cip_base_scoreboard #( csr_spinwait(.ptr(ral.sw_cmd_sts.cmd_ack), .exp_data(rsp_sts.csrng_rsp_ack), .backdoor(1'b1)); sw_cmd_sts[sw_cmd_ack] = rsp_sts.csrng_rsp_ack; - sw_cmd_sts[sw_cmd_sts] = rsp_sts.csrng_rsp_sts; + sw_cmd_sts[sw_cmd_sts+:CMD_STS_SIZE-1] = rsp_sts.csrng_rsp_sts; sw_cmd_sts[sw_cmd_rdy] = !auto_mode; sw_cmd_sts[sw_cmd_reg_rdy] = !auto_mode;, wait (cfg.backdoor_disable || reset_happened); @@ -713,7 +714,7 @@ class edn_scoreboard extends cip_base_scoreboard #( end else begin hw_cmd_sts = `gmv(ral.hw_cmd_sts); hw_cmd_sts[hw_cmd_ack] = rsp_sts.csrng_rsp_ack; - hw_cmd_sts[hw_cmd_sts] = rsp_sts.csrng_rsp_sts; + hw_cmd_sts[hw_cmd_sts+:CMD_STS_SIZE-1] = rsp_sts.csrng_rsp_sts; void'(ral.hw_cmd_sts.predict(.value(hw_cmd_sts))); end end diff --git a/hw/ip/edn/dv/env/seq_lib/edn_alert_vseq.sv b/hw/ip/edn/dv/env/seq_lib/edn_alert_vseq.sv index ce24e19f8f014..ec4308545ceea 100644 --- a/hw/ip/edn/dv/env/seq_lib/edn_alert_vseq.sv +++ b/hw/ip/edn/dv/env/seq_lib/edn_alert_vseq.sv @@ -89,7 +89,7 @@ class edn_alert_vseq extends edn_base_vseq; end `uvm_info(`gfn, $sformatf("State reached"), UVM_HIGH) // The next acknowledgement should return an error status. - cfg.m_csrng_agent_cfg.rsp_sts_err = 1; + cfg.m_csrng_agent_cfg.rsp_sts_err = cfg.which_cmd_sts_err; ) join_none @@ -104,10 +104,10 @@ class edn_alert_vseq extends edn_base_vseq; // If coverage is enabled, record the values of the hw_cmd_sts register. if (cfg.en_cov) begin cov_vif.cg_edn_hw_cmd_sts_sample(.boot_mode(value[hw_cmd_boot_mode]), - .auto_mode(value[hw_cmd_auto_mode]), - .cmd_sts(value[hw_cmd_sts]), - .cmd_ack(value[hw_cmd_ack]), - .acmd(csrng_pkg::acmd_e'(value[hw_cmd_type+:4]))); + .auto_mode(value[hw_cmd_auto_mode]), + .cmd_sts(csrng_pkg::csrng_cmd_sts_e'(value[hw_cmd_sts+:CMD_STS_SIZE])), + .cmd_ack(value[hw_cmd_ack]), + .acmd(csrng_pkg::acmd_e'(value[hw_cmd_type+:CMD_TYPE_SIZE]))); end // Issue the commands that are needed to get to exp_state in a fork. start_transition_to_main_sm_state(exp_state); @@ -128,7 +128,7 @@ class edn_alert_vseq extends edn_base_vseq; // Wait for the CSRNG error status response to propagate through the EDN // to the hw_cmd_sts register. - csr_spinwait(.ptr(ral.hw_cmd_sts.cmd_sts), .exp_data(1'b1), .backdoor(1'b1)); + csr_spinwait(.ptr(ral.hw_cmd_sts.cmd_sts), .exp_data(cfg.which_cmd_sts_err), .backdoor(1'b1)); cfg.clk_rst_vif.wait_clks(10); // Expect the csrng_ack_err bit to be set in the recov_alert_sts register. exp_recov_alert_sts = 32'b0; @@ -137,9 +137,9 @@ class edn_alert_vseq extends edn_base_vseq; // Check hw_cmd_sts in scoreboard. exp_hw_cmd_sts[hw_cmd_boot_mode] = (cfg.boot_req_mode == MuBi4True) ? 1'b1 : 1'b0; exp_hw_cmd_sts[hw_cmd_auto_mode] = (cfg.auto_req_mode == MuBi4True) ? 1'b1 : 1'b0; - exp_hw_cmd_sts[hw_cmd_sts] = 1'b1; + exp_hw_cmd_sts[hw_cmd_sts+:CMD_STS_SIZE] = cfg.which_cmd_sts_err; exp_hw_cmd_sts[hw_cmd_ack] = 1'b1; - exp_hw_cmd_sts[hw_cmd_type+:4] = + exp_hw_cmd_sts[hw_cmd_type+:CMD_TYPE_SIZE] = (exp_state inside {BootLoadIns, BootInsAckWait}) ? csrng_pkg::INS : (exp_state inside {BootPulse, BootDone, BootLoadUni}) ? csrng_pkg::UNI : (exp_state inside {AutoCaptReseedCnt, AutoSendReseedCmd}) ? csrng_pkg::RES : @@ -148,10 +148,10 @@ class edn_alert_vseq extends edn_base_vseq; // If coverage is enabled, record the values of the hw_cmd_sts register. if (cfg.en_cov) begin cov_vif.cg_edn_hw_cmd_sts_sample(.boot_mode(exp_hw_cmd_sts[hw_cmd_boot_mode]), - .auto_mode(exp_hw_cmd_sts[hw_cmd_auto_mode]), - .cmd_sts(exp_hw_cmd_sts[hw_cmd_sts]), - .cmd_ack(exp_hw_cmd_sts[hw_cmd_ack]), - .acmd(csrng_pkg::acmd_e'(exp_hw_cmd_sts[hw_cmd_type+:4]))); + .auto_mode(exp_hw_cmd_sts[hw_cmd_auto_mode]), + .cmd_sts(csrng_pkg::csrng_cmd_sts_e'(exp_hw_cmd_sts[hw_cmd_sts+:CMD_STS_SIZE])), + .cmd_ack(exp_hw_cmd_sts[hw_cmd_ack]), + .acmd(csrng_pkg::acmd_e'(exp_hw_cmd_sts[hw_cmd_type+:CMD_TYPE_SIZE]))); end csr_rd_check(.ptr(ral.main_sm_state), .compare_value(edn_pkg::RejectCsrngEntropy)); // See if we can request some data if the generate has been issued. @@ -161,7 +161,7 @@ class edn_alert_vseq extends edn_base_vseq; m_endpoint_pull_seq.start(p_sequencer.endpoint_sequencer_h[endpoint_port]); end // From now on we want the CSRNG status responses to be valid again. - cfg.m_csrng_agent_cfg.rsp_sts_err = 0; + cfg.m_csrng_agent_cfg.rsp_sts_err = csrng_pkg::CMD_STS_SUCCESS; // Force the genbits valid signal to high and verify that the EDN does not accept // any further genbits. `DV_SPINWAIT_EXIT(`DV_CHECK(uvm_hdl_force(cfg.edn_vif.genbits_valid_path(), 1'b1)); diff --git a/hw/ip/edn/dv/tests/edn_base_test.sv b/hw/ip/edn/dv/tests/edn_base_test.sv index 6cca685481742..bbf67d6edfd34 100644 --- a/hw/ip/edn/dv/tests/edn_base_test.sv +++ b/hw/ip/edn/dv/tests/edn_base_test.sv @@ -33,7 +33,8 @@ class edn_base_test extends cip_base_test #( cfg.m_csrng_agent_cfg.max_genbits_dly = 32; cfg.m_csrng_agent_cfg.min_cmd_rdy_dly = 0; cfg.m_csrng_agent_cfg.max_cmd_rdy_dly = 1; - cfg.m_csrng_agent_cfg.rsp_sts_err = 0; // CSRNG should not return errors + // CSRNG should not return errors + cfg.m_csrng_agent_cfg.rsp_sts_err = csrng_pkg::CMD_STS_SUCCESS; endfunction endclass : edn_base_test diff --git a/hw/ip/edn/rtl/edn_core.sv b/hw/ip/edn/rtl/edn_core.sv index 009e5cc031be2..74d33192cbffe 100644 --- a/hw/ip/edn/rtl/edn_core.sv +++ b/hw/ip/edn/rtl/edn_core.sv @@ -202,10 +202,10 @@ module edn_core import edn_pkg::*; logic [63:0] cs_rdata_capt_q, cs_rdata_capt_d; logic cs_rdata_capt_vld_q, cs_rdata_capt_vld_d; logic cmd_rdy_q, cmd_rdy_d; - logic csrng_cmd_sts_q, csrng_cmd_sts_d; + csrng_pkg::csrng_cmd_sts_e csrng_cmd_sts_q, csrng_cmd_sts_d; logic csrng_sw_cmd_ack_q, csrng_sw_cmd_ack_d; logic csrng_hw_cmd_ack_q, csrng_hw_cmd_ack_d; - logic csrng_hw_cmd_sts_q, csrng_hw_cmd_sts_d; + csrng_pkg::csrng_cmd_sts_e csrng_hw_cmd_sts_q, csrng_hw_cmd_sts_d; logic boot_mode_q, boot_mode_d, auto_mode_q, auto_mode_d; logic [3:0] cmd_type_q, cmd_type_d; @@ -223,9 +223,9 @@ module edn_core import edn_pkg::*; cs_rdata_capt_q <= '0; cs_rdata_capt_vld_q <= '0; cmd_rdy_q <= '0; - csrng_cmd_sts_q <= '0; + csrng_cmd_sts_q <= csrng_pkg::CMD_STS_SUCCESS; csrng_sw_cmd_ack_q <= '0; - csrng_hw_cmd_sts_q <= '0; + csrng_hw_cmd_sts_q <= csrng_pkg::CMD_STS_SUCCESS; boot_mode_q <= '0; auto_mode_q <= '0; cmd_type_q <= '0; @@ -568,7 +568,7 @@ module edn_core import edn_pkg::*; assign hw2reg.sw_cmd_sts.cmd_sts.de = 1'b1; assign hw2reg.sw_cmd_sts.cmd_sts.d = csrng_cmd_sts_d; assign csrng_cmd_sts_d = - !edn_enable_fo[SwCmdSts] ? 1'b0 : + !edn_enable_fo[SwCmdSts] ? csrng_pkg::CMD_STS_SUCCESS : (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q; @@ -601,10 +601,10 @@ module edn_core import edn_pkg::*; assign hw2reg.hw_cmd_sts.cmd_sts.de = 1'b1; assign hw2reg.hw_cmd_sts.cmd_sts.d = csrng_hw_cmd_sts_d; assign csrng_hw_cmd_sts_d = - !edn_enable_fo[HwCmdSts] ? 1'b0 : + !edn_enable_fo[HwCmdSts] ? csrng_pkg::CMD_STS_SUCCESS : sw_cmd_valid ? csrng_hw_cmd_sts_q : - (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? 1'b0 : - csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts ? 1'b1 : + (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? csrng_pkg::CMD_STS_SUCCESS : + csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q; // Set the cmd_ack signal to high whenever a hardware command is acknowledged and set it // to low whenever a new hardware command is issued to the CSRNG. diff --git a/hw/ip/edn/rtl/edn_reg_pkg.sv b/hw/ip/edn/rtl/edn_reg_pkg.sv index d47f729bd82ba..fe14870719fc1 100644 --- a/hw/ip/edn/rtl/edn_reg_pkg.sv +++ b/hw/ip/edn/rtl/edn_reg_pkg.sv @@ -131,11 +131,11 @@ package edn_reg_pkg; struct packed { logic d; logic de; - } cmd_sts; + } cmd_ack; struct packed { - logic d; + logic [1:0] d; logic de; - } cmd_ack; + } cmd_sts; } edn_hw2reg_sw_cmd_sts_reg_t; typedef struct packed { @@ -148,17 +148,17 @@ package edn_reg_pkg; logic de; } auto_mode; struct packed { - logic d; + logic [3:0] d; logic de; - } cmd_sts; + } cmd_type; struct packed { logic d; logic de; } cmd_ack; struct packed { - logic [3:0] d; + logic [1:0] d; logic de; - } cmd_type; + } cmd_sts; } edn_hw2reg_hw_cmd_sts_reg_t; typedef struct packed { @@ -246,9 +246,9 @@ package edn_reg_pkg; // HW -> register type typedef struct packed { - edn_hw2reg_intr_state_reg_t intr_state; // [62:59] - edn_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [58:51] - edn_hw2reg_hw_cmd_sts_reg_t hw_cmd_sts; // [50:38] + edn_hw2reg_intr_state_reg_t intr_state; // [64:61] + edn_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [60:52] + edn_hw2reg_hw_cmd_sts_reg_t hw_cmd_sts; // [51:38] edn_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [37:26] edn_hw2reg_err_code_reg_t err_code; // [25:10] edn_hw2reg_main_sm_state_reg_t main_sm_state; // [9:0] @@ -319,7 +319,7 @@ package edn_reg_pkg; 4'b 1111, // index[ 7] EDN_BOOT_GEN_CMD 4'b 1111, // index[ 8] EDN_SW_CMD_REQ 4'b 0001, // index[ 9] EDN_SW_CMD_STS - 4'b 0001, // index[10] EDN_HW_CMD_STS + 4'b 0011, // index[10] EDN_HW_CMD_STS 4'b 1111, // index[11] EDN_RESEED_CMD 4'b 1111, // index[12] EDN_GENERATE_CMD 4'b 1111, // index[13] EDN_MAX_NUM_REQS_BETWEEN_RESEEDS diff --git a/hw/ip/edn/rtl/edn_reg_top.sv b/hw/ip/edn/rtl/edn_reg_top.sv index 956d0016f7c1c..efa9291252d54 100644 --- a/hw/ip/edn/rtl/edn_reg_top.sv +++ b/hw/ip/edn/rtl/edn_reg_top.sv @@ -159,13 +159,13 @@ module edn_reg_top ( logic [31:0] sw_cmd_req_wd; logic sw_cmd_sts_cmd_reg_rdy_qs; logic sw_cmd_sts_cmd_rdy_qs; - logic sw_cmd_sts_cmd_sts_qs; logic sw_cmd_sts_cmd_ack_qs; + logic [1:0] sw_cmd_sts_cmd_sts_qs; logic hw_cmd_sts_boot_mode_qs; logic hw_cmd_sts_auto_mode_qs; - logic hw_cmd_sts_cmd_sts_qs; - logic hw_cmd_sts_cmd_ack_qs; logic [3:0] hw_cmd_sts_cmd_type_qs; + logic hw_cmd_sts_cmd_ack_qs; + logic [1:0] hw_cmd_sts_cmd_sts_qs; logic reseed_cmd_we; logic [31:0] reseed_cmd_wd; logic generate_cmd_we; @@ -658,13 +658,13 @@ module edn_reg_top ( .qs (sw_cmd_sts_cmd_rdy_qs) ); - // F[cmd_sts]: 2:2 + // F[cmd_ack]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_sw_cmd_sts_cmd_sts ( + ) u_sw_cmd_sts_cmd_ack ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -673,8 +673,8 @@ module edn_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.sw_cmd_sts.cmd_sts.de), - .d (hw2reg.sw_cmd_sts.cmd_sts.d), + .de (hw2reg.sw_cmd_sts.cmd_ack.de), + .d (hw2reg.sw_cmd_sts.cmd_ack.d), // to internal hardware .qe (), @@ -682,16 +682,16 @@ module edn_reg_top ( .ds (), // to register interface (read) - .qs (sw_cmd_sts_cmd_sts_qs) + .qs (sw_cmd_sts_cmd_ack_qs) ); - // F[cmd_ack]: 3:3 + // F[cmd_sts]: 4:3 prim_subreg #( - .DW (1), + .DW (2), .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), + .RESVAL (2'h0), .Mubi (1'b0) - ) u_sw_cmd_sts_cmd_ack ( + ) u_sw_cmd_sts_cmd_sts ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -700,8 +700,8 @@ module edn_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.sw_cmd_sts.cmd_ack.de), - .d (hw2reg.sw_cmd_sts.cmd_ack.d), + .de (hw2reg.sw_cmd_sts.cmd_sts.de), + .d (hw2reg.sw_cmd_sts.cmd_sts.d), // to internal hardware .qe (), @@ -709,7 +709,7 @@ module edn_reg_top ( .ds (), // to register interface (read) - .qs (sw_cmd_sts_cmd_ack_qs) + .qs (sw_cmd_sts_cmd_sts_qs) ); @@ -768,13 +768,13 @@ module edn_reg_top ( .qs (hw_cmd_sts_auto_mode_qs) ); - // F[cmd_sts]: 2:2 + // F[cmd_type]: 5:2 prim_subreg #( - .DW (1), + .DW (4), .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), + .RESVAL (4'h0), .Mubi (1'b0) - ) u_hw_cmd_sts_cmd_sts ( + ) u_hw_cmd_sts_cmd_type ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -783,8 +783,8 @@ module edn_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.hw_cmd_sts.cmd_sts.de), - .d (hw2reg.hw_cmd_sts.cmd_sts.d), + .de (hw2reg.hw_cmd_sts.cmd_type.de), + .d (hw2reg.hw_cmd_sts.cmd_type.d), // to internal hardware .qe (), @@ -792,10 +792,10 @@ module edn_reg_top ( .ds (), // to register interface (read) - .qs (hw_cmd_sts_cmd_sts_qs) + .qs (hw_cmd_sts_cmd_type_qs) ); - // F[cmd_ack]: 3:3 + // F[cmd_ack]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), @@ -822,13 +822,13 @@ module edn_reg_top ( .qs (hw_cmd_sts_cmd_ack_qs) ); - // F[cmd_type]: 7:4 + // F[cmd_sts]: 8:7 prim_subreg #( - .DW (4), + .DW (2), .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (4'h0), + .RESVAL (2'h0), .Mubi (1'b0) - ) u_hw_cmd_sts_cmd_type ( + ) u_hw_cmd_sts_cmd_sts ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -837,8 +837,8 @@ module edn_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.hw_cmd_sts.cmd_type.de), - .d (hw2reg.hw_cmd_sts.cmd_type.d), + .de (hw2reg.hw_cmd_sts.cmd_sts.de), + .d (hw2reg.hw_cmd_sts.cmd_sts.d), // to internal hardware .qe (), @@ -846,7 +846,7 @@ module edn_reg_top ( .ds (), // to register interface (read) - .qs (hw_cmd_sts_cmd_type_qs) + .qs (hw_cmd_sts_cmd_sts_qs) ); @@ -1570,16 +1570,16 @@ module edn_reg_top ( addr_hit[9]: begin reg_rdata_next[0] = sw_cmd_sts_cmd_reg_rdy_qs; reg_rdata_next[1] = sw_cmd_sts_cmd_rdy_qs; - reg_rdata_next[2] = sw_cmd_sts_cmd_sts_qs; - reg_rdata_next[3] = sw_cmd_sts_cmd_ack_qs; + reg_rdata_next[2] = sw_cmd_sts_cmd_ack_qs; + reg_rdata_next[4:3] = sw_cmd_sts_cmd_sts_qs; end addr_hit[10]: begin reg_rdata_next[0] = hw_cmd_sts_boot_mode_qs; reg_rdata_next[1] = hw_cmd_sts_auto_mode_qs; - reg_rdata_next[2] = hw_cmd_sts_cmd_sts_qs; - reg_rdata_next[3] = hw_cmd_sts_cmd_ack_qs; - reg_rdata_next[7:4] = hw_cmd_sts_cmd_type_qs; + reg_rdata_next[5:2] = hw_cmd_sts_cmd_type_qs; + reg_rdata_next[6] = hw_cmd_sts_cmd_ack_qs; + reg_rdata_next[8:7] = hw_cmd_sts_cmd_sts_qs; end addr_hit[11]: begin diff --git a/sw/device/lib/crypto/drivers/entropy.c b/sw/device/lib/crypto/drivers/entropy.c index 1063bb5d62ad5..295c6a1ce9c0f 100644 --- a/sw/device/lib/crypto/drivers/entropy.c +++ b/sw/device/lib/crypto/drivers/entropy.c @@ -450,9 +450,9 @@ static status_t csrng_send_app_cmd(uint32_t base_address, reg = abs_mmio_read32(kBaseCsrng + CSRNG_INTR_STATE_REG_OFFSET); } while (!bitfield_bit32_read(reg, CSRNG_INTR_STATE_CS_CMD_REQ_DONE_BIT)); - // Check the "status" bit, which will be 1 only if there was an error. + // Check the "status" bit, which will be 0 unless there was an error. reg = abs_mmio_read32(kBaseCsrng + CSRNG_SW_CMD_STS_REG_OFFSET); - if (bitfield_bit32_read(reg, CSRNG_SW_CMD_STS_CMD_STS_BIT)) { + if (bitfield_field32_read(reg, CSRNG_SW_CMD_STS_CMD_STS_FIELD)) { return OTCRYPTO_RECOV_ERR; } } @@ -467,8 +467,8 @@ static status_t csrng_send_app_cmd(uint32_t base_address, reg = abs_mmio_read32(sts_reg_addr); } while (!bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_ACK_BIT)); - // Check the "status" bit, which will be 1 only if there was an error. - if (bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_STS_BIT)) { + // Check the "status" bit, which will be 0 unless there was an error. + if (bitfield_field32_read(reg, CSRNG_SW_CMD_STS_CMD_STS_FIELD)) { return OTCRYPTO_RECOV_ERR; } } @@ -525,7 +525,7 @@ static status_t edn_ready_block(uint32_t edn_address) { reg = abs_mmio_read32(edn_address + EDN_SW_CMD_STS_REG_OFFSET); } while (!bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_RDY_BIT)); - if (bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_STS_BIT)) { + if (bitfield_field32_read(reg, CSRNG_SW_CMD_STS_CMD_STS_FIELD)) { return OTCRYPTO_RECOV_ERR; } return OTCRYPTO_OK; diff --git a/sw/device/lib/dif/dif_csrng.c b/sw/device/lib/dif/dif_csrng.c index e7b15e6d1e926..77c74e4acfe8d 100644 --- a/sw/device/lib/dif/dif_csrng.c +++ b/sw/device/lib/dif/dif_csrng.c @@ -147,90 +147,12 @@ dif_result_t dif_csrng_get_cmd_interface_status( uint32_t reg = mmio_region_read32(csrng->base_addr, CSRNG_SW_CMD_STS_REG_OFFSET); bool cmd_ready = bitfield_bit32_read(reg, CSRNG_SW_CMD_STS_CMD_RDY_BIT); - bool cmd_error = bitfield_bit32_read(reg, CSRNG_SW_CMD_STS_CMD_STS_BIT); + uint32_t cmd_sts = bitfield_field32_read(reg, CSRNG_SW_CMD_STS_CMD_STS_FIELD); - // The function prioritizes error detection to avoid masking errors - // when `cmd_ready` is set to true. - if (cmd_error) { + status->cmd_sts = cmd_sts; + // If the command did not execute successfully, return the error status. + if (cmd_sts != 0) { status->kind = kDifCsrngCmdStatusError; - uint32_t reg = - mmio_region_read32(csrng->base_addr, CSRNG_ERR_CODE_REG_OFFSET); - - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoCmd, reg, - CSRNG_ERR_CODE_SFIFO_CMD_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoGenBits, reg, - CSRNG_ERR_CODE_SFIFO_GENBITS_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoCmdReq, reg, - CSRNG_ERR_CODE_SFIFO_CMDREQ_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoRcStage, reg, - CSRNG_ERR_CODE_SFIFO_RCSTAGE_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoKeyVrc, reg, - CSRNG_ERR_CODE_SFIFO_KEYVRC_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoUpdateReq, - reg, CSRNG_ERR_CODE_SFIFO_UPDREQ_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoBencRec, reg, - CSRNG_ERR_CODE_SFIFO_BENCREQ_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoBencAck, reg, - CSRNG_ERR_CODE_SFIFO_BENCACK_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoPData, reg, - CSRNG_ERR_CODE_SFIFO_PDATA_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoFinal, reg, - CSRNG_ERR_CODE_SFIFO_FINAL_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoGBencAck, reg, - CSRNG_ERR_CODE_SFIFO_GBENCACK_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoGrcStage, reg, - CSRNG_ERR_CODE_SFIFO_GRCSTAGE_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoGGenReq, reg, - CSRNG_ERR_CODE_SFIFO_GGENREQ_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoGadStage, reg, - CSRNG_ERR_CODE_SFIFO_GADSTAGE_ERR_BIT); - status->unhealthy_fifos = - bitfield_bit32_copy(status->unhealthy_fifos, kDifCsrngFifoBlockEnc, reg, - CSRNG_ERR_CODE_SFIFO_BLKENC_ERR_BIT); - - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorCmdStageSm, reg, - CSRNG_ERR_CODE_CMD_STAGE_SM_ERR_BIT); - status->errors = bitfield_bit32_copy(status->errors, kDifCsrngErrorMainSm, - reg, CSRNG_ERR_CODE_MAIN_SM_ERR_BIT); - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorDrbgGenSm, reg, - CSRNG_ERR_CODE_DRBG_GEN_SM_ERR_BIT); - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorDrbgUpdateBlockEncSm, - reg, CSRNG_ERR_CODE_DRBG_UPDBE_SM_ERR_BIT); - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorDrbgUpdateOutBlockSm, - reg, CSRNG_ERR_CODE_DRBG_UPDOB_SM_ERR_BIT); - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorAesSm, reg, - CSRNG_ERR_CODE_AES_CIPHER_SM_ERR_BIT); - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorGenerateCmdCounter, - reg, CSRNG_ERR_CODE_CMD_GEN_CNT_ERR_BIT); - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorFifoWrite, reg, - CSRNG_ERR_CODE_FIFO_WRITE_ERR_BIT); - status->errors = bitfield_bit32_copy(status->errors, kDifCsrngErrorFifoRead, - reg, CSRNG_ERR_CODE_FIFO_READ_ERR_BIT); - status->errors = - bitfield_bit32_copy(status->errors, kDifCsrngErrorFifoFullAndEmpty, reg, - CSRNG_ERR_CODE_FIFO_STATE_ERR_BIT); - return kDifOk; } diff --git a/sw/device/lib/dif/dif_csrng.h b/sw/device/lib/dif/dif_csrng.h index 3549f6da12e35..ba24ffbd7fbd9 100644 --- a/sw/device/lib/dif/dif_csrng.h +++ b/sw/device/lib/dif/dif_csrng.h @@ -154,6 +154,30 @@ typedef enum dif_csrng_error { kDifCsrngErrorFifoFullAndEmpty, } dif_csrng_error_t; +/** + * Enumeration of CSRNG command status errors. + */ +typedef enum dif_csrng_cmd_sts_error { + /** + * Indicates that the command completed successfully. + */ + kDifCsrngCmdStsSuccess = 0, + /** + * Indicates that an invalid apllication command has been issued. + */ + kDifCsrngCmdStsInvalidAcmd = 1, + /** + * Indicates that the state wasn't zeroized properly after an uninstantiate + * command due to invalid state parameters in the cmd drbg. + */ + kDifCsrngCmdStsInvalidStateParams = 2, + /** + * Indicates that CSRNG entropy was generated for a command that is not a + * generate command. + */ + kDifCsrngCmdStsInvalidCtrDrbgCmd = 3, +} dif_csrng_cmd_sts_t; + /** * The status of the CSRNG block at a particular moment in time. */ @@ -163,14 +187,9 @@ typedef struct dif_csrng_cmd_status { */ dif_csrng_cmd_status_kind_t kind; /** - * A bitset of FIFOs in an unhealthy state, with bit indices given by - * `dif_csrng_fifo_t`. - */ - uint32_t unhealthy_fifos; - /** - * A bitset of errors, with bit indices given by `dif_csrng_error_t`. + * The status value CSRNG returns. */ - uint32_t errors; + dif_csrng_cmd_sts_t cmd_sts; } dif_csrng_cmd_status_t; /** diff --git a/sw/device/lib/dif/dif_csrng_unittest.cc b/sw/device/lib/dif/dif_csrng_unittest.cc index db6cf11464aa4..f9019f97687da 100644 --- a/sw/device/lib/dif/dif_csrng_unittest.cc +++ b/sw/device/lib/dif/dif_csrng_unittest.cc @@ -54,19 +54,11 @@ TEST_F(GetCmdInterfaceStatusTest, NullArgs) { struct StatusTestCase { bool cmd_ready; - bool cmd_status; - uint32_t err_codes; + bool cmd_ack; + uint32_t cmd_status; dif_csrng_cmd_status_t expected_status; }; -template -uint32_t BitSet(Ints... bits) { - uint32_t x = 0; - auto ignored = {x |= 1 << static_cast(bits)...}; - (void)ignored; - return x; -} - class GetCmdInterfaceStatusTestAllParams : public GetCmdInterfaceStatusTest, public testing::WithParamInterface {}; @@ -74,38 +66,31 @@ class GetCmdInterfaceStatusTestAllParams TEST_P(GetCmdInterfaceStatusTestAllParams, ValidConfigurationMode) { const auto &test_param = GetParam(); dif_csrng_cmd_status_t status{}; - EXPECT_READ32(CSRNG_SW_CMD_STS_REG_OFFSET, - { - {CSRNG_SW_CMD_STS_CMD_RDY_BIT, test_param.cmd_ready}, - {CSRNG_SW_CMD_STS_CMD_STS_BIT, test_param.cmd_status}, - }); - if (test_param.expected_status.kind == kDifCsrngCmdStatusError) { - EXPECT_READ32(CSRNG_ERR_CODE_REG_OFFSET, test_param.err_codes); - } + uint32_t ctrl_reg = 0; + ctrl_reg = bitfield_bit32_write(ctrl_reg, CSRNG_SW_CMD_STS_CMD_RDY_BIT, + test_param.cmd_ready); + ctrl_reg = bitfield_bit32_write(ctrl_reg, CSRNG_SW_CMD_STS_CMD_ACK_BIT, + test_param.cmd_ack); + ctrl_reg = bitfield_field32_write(ctrl_reg, CSRNG_SW_CMD_STS_CMD_STS_FIELD, + test_param.cmd_status); + EXPECT_READ32(CSRNG_SW_CMD_STS_REG_OFFSET, ctrl_reg); EXPECT_DIF_OK(dif_csrng_get_cmd_interface_status(&csrng_, &status)); EXPECT_EQ(status.kind, test_param.expected_status.kind); - EXPECT_EQ(status.unhealthy_fifos, test_param.expected_status.unhealthy_fifos); - EXPECT_EQ(status.errors, test_param.expected_status.errors); + EXPECT_EQ(status.cmd_sts, test_param.expected_status.cmd_sts); } INSTANTIATE_TEST_SUITE_P( GetCmdInterfaceStatusTestAllParams, GetCmdInterfaceStatusTestAllParams, - testing::Values(StatusTestCase{true, false, 0, {kDifCsrngCmdStatusReady}}, - StatusTestCase{false, false, 0, {kDifCsrngCmdStatusBusy}}, - StatusTestCase{true, true, 0, {kDifCsrngCmdStatusError}}, + testing::Values(StatusTestCase{true, 0, 0x0, {kDifCsrngCmdStatusReady}}, + StatusTestCase{false, 0, 0x0, {kDifCsrngCmdStatusBusy}}, + StatusTestCase{true, 1, 0x0, {kDifCsrngCmdStatusReady}}, StatusTestCase{ false, - true, - BitSet(CSRNG_ERR_CODE_SFIFO_GENBITS_ERR_BIT, - CSRNG_ERR_CODE_SFIFO_PDATA_ERR_BIT, - CSRNG_ERR_CODE_AES_CIPHER_SM_ERR_BIT, - CSRNG_ERR_CODE_FIFO_STATE_ERR_BIT), + 1, + kDifCsrngCmdStsInvalidAcmd, { .kind = kDifCsrngCmdStatusError, - .unhealthy_fifos = BitSet(kDifCsrngFifoGenBits, - kDifCsrngFifoPData), - .errors = BitSet(kDifCsrngErrorAesSm, - kDifCsrngErrorFifoFullAndEmpty), + .cmd_sts = kDifCsrngCmdStsInvalidAcmd, }, })); diff --git a/sw/device/lib/dif/dif_edn.c b/sw/device/lib/dif/dif_edn.c index e3501eb975cf9..e0c87ff07bf4d 100644 --- a/sw/device/lib/dif/dif_edn.c +++ b/sw/device/lib/dif/dif_edn.c @@ -157,26 +157,26 @@ dif_result_t dif_edn_get_status(const dif_edn_t *edn, dif_edn_status_t flag, return kDifBadArg; } - uint32_t bit; + uint32_t reg = mmio_region_read32(edn->base_addr, EDN_SW_CMD_STS_REG_OFFSET); + uint32_t field_val; switch (flag) { case kDifEdnStatusRegReady: - bit = EDN_SW_CMD_STS_CMD_REG_RDY_BIT; + *set = bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT); break; case kDifEdnStatusReady: - bit = EDN_SW_CMD_STS_CMD_RDY_BIT; + *set = bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_RDY_BIT); break; case kDifEdnStatusCsrngStatus: - bit = EDN_SW_CMD_STS_CMD_STS_BIT; + field_val = bitfield_field32_read(reg, EDN_SW_CMD_STS_CMD_STS_FIELD); + *set = field_val ? true : false; break; case kDifEdnStatusCsrngAck: - bit = EDN_SW_CMD_STS_CMD_ACK_BIT; + *set = bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_ACK_BIT); break; default: return kDifBadArg; } - uint32_t reg = mmio_region_read32(edn->base_addr, EDN_SW_CMD_STS_REG_OFFSET); - *set = bitfield_bit32_read(reg, bit); return kDifOk; } diff --git a/sw/device/lib/dif/dif_edn_unittest.cc b/sw/device/lib/dif/dif_edn_unittest.cc index abe50b3b3c6ab..862214eff8052 100644 --- a/sw/device/lib/dif/dif_edn_unittest.cc +++ b/sw/device/lib/dif/dif_edn_unittest.cc @@ -171,8 +171,13 @@ TEST_F(SetModeTest, Auto) { EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, {{EDN_SW_CMD_STS_CMD_ACK_BIT, true}}); - EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, - {{EDN_SW_CMD_STS_CMD_STS_BIT, false}}); + uint32_t ctrl_reg = 0; + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1); + ctrl_reg = + bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 1); + EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg); EXPECT_DIF_OK(dif_edn_set_auto_mode(&edn_, params)); } @@ -188,52 +193,61 @@ class GetStatusTest : public DifEdnTest {}; TEST_F(GetStatusTest, BadArgs) { bool flag; + uint32_t ctrl_reg = 0; EXPECT_DIF_BADARG(dif_edn_get_status(nullptr, kDifEdnStatusReady, &flag)); + + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1); + ctrl_reg = + bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0); + EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg); EXPECT_DIF_BADARG( dif_edn_get_status(&edn_, static_cast(-1), &flag)); + EXPECT_DIF_BADARG(dif_edn_get_status(&edn_, kDifEdnStatusReady, nullptr)); } TEST_F(GetStatusTest, Ok) { bool flag; - - EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, - { - {EDN_SW_CMD_STS_CMD_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_STS_BIT, false}, - {EDN_SW_CMD_STS_CMD_ACK_BIT, false}, - }); + uint32_t ctrl_reg = 0; + + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1); + ctrl_reg = + bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0); + EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg); EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusRegReady, &flag)); EXPECT_TRUE(flag); - EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, - { - {EDN_SW_CMD_STS_CMD_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_STS_BIT, false}, - {EDN_SW_CMD_STS_CMD_ACK_BIT, false}, - }); + ctrl_reg = 0; + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1); + ctrl_reg = + bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0); + EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg); EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusReady, &flag)); EXPECT_TRUE(flag); - EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, - { - {EDN_SW_CMD_STS_CMD_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_STS_BIT, false}, - {EDN_SW_CMD_STS_CMD_ACK_BIT, false}, - }); + ctrl_reg = 0; + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1); + ctrl_reg = + bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0); + EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg); EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusCsrngStatus, &flag)); EXPECT_FALSE(flag); - EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, - { - {EDN_SW_CMD_STS_CMD_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}, - {EDN_SW_CMD_STS_CMD_STS_BIT, false}, - {EDN_SW_CMD_STS_CMD_ACK_BIT, false}, - }); + ctrl_reg = 0; + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1); + ctrl_reg = + bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0); + ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0); + EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg); EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusCsrngAck, &flag)); EXPECT_FALSE(flag); } diff --git a/sw/device/lib/testing/csrng_testutils.c b/sw/device/lib/testing/csrng_testutils.c index 34c55a348cb7f..46c99098a5d63 100644 --- a/sw/device/lib/testing/csrng_testutils.c +++ b/sw/device/lib/testing/csrng_testutils.c @@ -188,9 +188,7 @@ status_t csrng_testutils_fips_generate_kat(const dif_csrng_t *csrng) { status_t csrng_testutils_cmd_status_check(const dif_csrng_t *csrng) { dif_csrng_cmd_status_t status; TRY(dif_csrng_get_cmd_interface_status(csrng, &status)); - TRY_CHECK(status.errors == 0); - TRY_CHECK(status.unhealthy_fifos == 0); - TRY_CHECK(status.errors != kDifCsrngCmdStatusError); + TRY_CHECK(status.cmd_sts == kDifCsrngCmdStsSuccess); return OK_STATUS(); } diff --git a/sw/device/lib/testing/entropy_testutils.c b/sw/device/lib/testing/entropy_testutils.c index 4ff593b9118a0..fc277b7552550 100644 --- a/sw/device/lib/testing/entropy_testutils.c +++ b/sw/device/lib/testing/entropy_testutils.c @@ -260,10 +260,10 @@ status_t entropy_testutils_error_check(const dif_entropy_src_t *entropy_src, dif_csrng_cmd_status_t status; TRY(dif_csrng_get_cmd_interface_status(csrng, &status)); - if (status.errors) { + if (status.cmd_sts != kDifCsrngCmdStsSuccess) { found_error = true; - LOG_ERROR("csrng error status. err: 0x%x, fifo_err: 0x%x, kind: 0x%x", - status.errors, status.unhealthy_fifos, status.kind); + LOG_ERROR("csrng error status. err: 0x%x, kind: 0x%x", status.cmd_sts, + status.kind); } uint32_t fifo_errors;