lowRISC · vogelpi · Jan 18, 2024 · Jan 17, 2024
@@ -114,12 +114,6 @@ In this diagram the auto-generated register submodule is shown within the periph
 This register block communicates with the rest of the peripheral logic to manage configuration and status communication with software.
 Also shown is the mandatory clock, and the optional bus (TL-UL) host, interrupts, alerts, and chip IO.
 
-Additionally an optional input `devmode` is shown which represents an indication to the peripheral what mode the SOC is operating in.
-For now this includes only two modes: development (`devmode = 1`) and production (`devmode = 0`).
-This is the beginning of a security feature that will convey the full life cycle mode status to the peripheral.
-In its current form, only the distinction of development mode vs. production mode is required in order to determine how to handle software errors (see the [Register Tooling](../../../../util/reggen/README.md) documentation for details).
-The full definition of life cycle modes will come upon further refinement of the security properties of the SOC.
-
 ## Peripheral Feature Details
 
 ### Configuration File

@@ -42,7 +42,6 @@ In addition, it instantiates the following interfaces and sets their handle into
 * FOO IOs
 * Interrupts ([`pins_if`](../sv/common_ifs/README.md))
 * Alerts ([`pins_if`](../sv/common_ifs/README.md))
-* Devmode ([`pins_if`](../sv/common_ifs/README.md))
 
 ### Common DV utility components
 The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

@@ -59,8 +59,6 @@ The following is a list of common features and settings:
   many as the DUT provides. The reason for going with a fixed width pins_if is
   to allow the intr_vif to be available in this base env cfg class (which does not
   know how many interrupt each IP DUT provides).
-* **devmode_vif**: This is a handle to the `pins_if #(1)` interface instance created
-  in the tb to hookup the DUT input `devmode`.
 * **tl_agent_cfg**: The downstream TileLink host agent created in the cip_base_env
   class requires the agent cfg handle to tell it how to configure the agent.
 * **alert_agent_cfgs**: Similar to tl_agent_cfg, the downstream alert device agent

@@ -29,10 +29,6 @@ class cip_base_env #(type CFG_T               = cip_base_env_cfg,
         cfg.num_interrupts > 0) begin
       `uvm_fatal(get_full_name(), "failed to get intr_vif from uvm_config_db")
     end
-    if (cfg.has_devmode && !uvm_config_db#(devmode_vif)::get(this, "", "devmode_vif",
-                                                             cfg.devmode_vif)) begin
-      `uvm_fatal(get_full_name(), "failed to get devmode_vif from uvm_config_db")
-    end
 
     // Only get rst_shadowed_vif if it is an IP level testbench,
     // and the IP contains shadowed registers.

@@ -46,15 +46,9 @@ class cip_base_env_cfg #(type RAL_T = dv_base_reg_block) extends dv_base_env_cfg
 
   // Common interfaces - interrupts, alerts, edn clk.
   intr_vif            intr_vif;
-  devmode_vif         devmode_vif;
   rst_shadowed_vif    rst_shadowed_vif;
   virtual clk_rst_if  edn_clk_rst_vif;
 
-  // en_devmode default sets to 1 because all IPs' devmode_i is tied off internally to 1
-  // ICEBOX(#16739): enable random drive devmode once design supports
-  bit  has_devmode = 1;
-  bit  en_devmode = 1;
-
   // If the data intg is passthru for the memory and the data intg value in mem is incorrect, it
   // won't trigger d_error in this mem block and the check is done in the processor
   // User can set this flag to disable the check for d_user.data_intg

@@ -389,10 +389,7 @@ class cip_base_scoreboard #(type RAL_T = dv_base_reg_block,
 
     unmapped_err = !is_tl_access_mapped_addr(item, ral_name);
     if (unmapped_err) begin
-      // if devmode is enabled, d_error will be set
-      if (cfg.en_devmode || cfg.devmode_vif.sample()) begin
-        exp_d_error = !cfg.ral_models[ral_name].get_unmapped_access_ok();
-      end
+      exp_d_error = !cfg.ral_models[ral_name].get_unmapped_access_ok();
     end
 
     mem_access_err = !is_tl_mem_access_allowed(item, ral_name, mem_byte_access_err, mem_wo_err,

@@ -36,7 +36,6 @@ package dv_utils_pkg;
 
   // typedef parameterized pins_if for ease of implementation for interrupts and alerts
   typedef virtual pins_if #(NUM_MAX_INTERRUPTS) intr_vif;
-  typedef virtual pins_if #(1)                  devmode_vif;
 
   // interface direction / mode - Host or Device
   typedef enum bit {

@@ -23,7 +23,7 @@
               - address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0`
               - size is greater than 2
             - OpenTitan defined error cases
-              - access unmapped address, expect `d_error = 1` when `devmode_i == 1`
+              - access unmapped address, expect `d_error = 1`
               - write a CSR with unaligned address, e.g. `a_address[1:0] != 0`
               - write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
               - write a memory with `a_mask != '1` when it doesn't support partial accesses

@@ -41,7 +41,6 @@ module tb;
 
   wire clk, rst_n;
   wire clk_aon, rst_aon_n;
-  wire devmode;
   wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
   wire wakeup_req;
   wire [ADC_CTRL_CHANNELS - 1 : 0] adc_channel_sel, adc_data_valid;
@@ -74,7 +73,6 @@ module tb;
   );
   pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts);
   pins_if #(1) wakeup_if (wakeup_req);
-  pins_if #(1) devmode_if (devmode);
   tl_if tl_if (
     .clk  (clk),
     .rst_n(rst_n)
@@ -113,7 +111,6 @@ module tb;
     uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_aon_rst_vif", clk_aon_rst_if);
     uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
     uvm_config_db#(wakeup_vif_t)::set(null, "*.env", "wakeup_vif", wakeup_if);
-    uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
     uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
     $timeformat(-12, 0, " ps", 12);
     run_test();

diff --git a/hw/ip/adc_ctrl/rtl/adc_ctrl.sv b/hw/ip/adc_ctrl/rtl/adc_ctrl.sv
@@ -75,8 +75,7 @@ module adc_ctrl
     .reg2hw(reg2hw),
     .hw2reg(hw2reg),
     // SEC_CM: BUS.INTEGRITY
-    .intg_err_o(alerts[0]),
-    .devmode_i(1'b1)
+    .intg_err_o(alerts[0])
   );
 
   // Instantiate DCD core module

diff --git a/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_top.sv b/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_top.sv
@@ -18,10 +18,7 @@ module adc_ctrl_reg_top (
   input  adc_ctrl_reg_pkg::adc_ctrl_hw2reg_t hw2reg, // Read
 
   // Integrity check errors
-  output logic intg_err_o,
-
-  // Config
-  input devmode_i // If 1, explicit error return for unmapped register access
+  output logic intg_err_o
 );
 
   import adc_ctrl_reg_pkg::* ;
@@ -121,7 +118,7 @@ module adc_ctrl_reg_top (
   // cdc oversampling signals
 
   assign reg_rdata = reg_rdata_next ;
-  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+  assign reg_error = addrmiss | wr_err | intg_err;
 
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}

@@ -14,7 +14,6 @@ module tb;
   `include "dv_macros.svh"
 
   wire                                    clk, rst_n, rst_shadowed_n;
-  wire                                    devmode;
   wire [NUM_MAX_INTERRUPTS-1:0]           interrupts;
   wire                                    edn_req;
   wire [$bits(lc_ctrl_pkg::lc_tx_t) : 0]  lc_escalate;
@@ -29,7 +28,6 @@ module tb;
   rst_shadowed_if rst_shadowed_if(.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n));
   pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts);
 
-  pins_if #(1) devmode_if(devmode);
   pins_if #($bits(lc_escalate)) lc_escalate_if (lc_escalate);
   pins_if #(1) idle_if (idle);
   tl_if tl_if(.clk(clk), .rst_n(rst_n));
@@ -79,7 +77,6 @@ module tb;
     uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif",
                                                  rst_shadowed_if);
     uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
-    uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
     uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
     uvm_config_db#(virtual aes_cov_if)::set(null, "*.env", "aes_cov_if", dut.u_aes_cov_if );
     uvm_config_db#(virtual key_sideload_if)

@@ -104,8 +104,7 @@ module aes
     .hw2reg,
     .shadowed_storage_err_o(shadowed_storage_err),
     .shadowed_update_err_o(shadowed_update_err),
-    .intg_err_o(intg_err_alert),
-    .devmode_i(1'b1)
+    .intg_err_o(intg_err_alert)
   );
 
   // SEC_CM: LC_ESCALATE_EN.INTERSIG.MUBI

@@ -20,10 +20,7 @@ module aes_reg_top (
   output logic shadowed_update_err_o,
 
   // Integrity check errors
-  output logic intg_err_o,
-
-  // Config
-  input devmode_i // If 1, explicit error return for unmapped register access
+  output logic intg_err_o
 );
 
   import aes_reg_pkg::* ;
@@ -123,7 +120,7 @@ module aes_reg_top (
   // cdc oversampling signals
 
   assign reg_rdata = reg_rdata_next ;
-  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+  assign reg_error = addrmiss | wr_err | intg_err;
 
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}

@@ -16,9 +16,6 @@ class aon_timer_env_cfg extends cip_base_env_cfg #(.RAL_T(aon_timer_reg_block));
 
   function new (string name="");
     super.new(name);
-
-    // The aon_timer RTL doesn't support a devmode input at the moment.
-    has_devmode = 1'b0;
   endfunction : new
 
   virtual function void initialize(bit [31:0] csr_base_addr = '1);

diff --git a/hw/ip/aon_timer/rtl/aon_timer.sv b/hw/ip/aon_timer/rtl/aon_timer.sv
@@ -97,8 +97,7 @@ module aon_timer import aon_timer_reg_pkg::*;
     .hw2reg,
 
     // SEC_CM: BUS.INTEGRITY
-    .intg_err_o (alerts[0]),
-    .devmode_i  (1'b1)
+    .intg_err_o (alerts[0])
   );
 
   ////////////

diff --git a/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv b/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
@@ -18,10 +18,7 @@ module aon_timer_reg_top (
   input  aon_timer_reg_pkg::aon_timer_hw2reg_t hw2reg, // Read
 
   // Integrity check errors
-  output logic intg_err_o,
-
-  // Config
-  input devmode_i // If 1, explicit error return for unmapped register access
+  output logic intg_err_o
 );
 
   import aon_timer_reg_pkg::* ;
@@ -121,7 +118,7 @@ module aon_timer_reg_top (
   // cdc oversampling signals
 
   assign reg_rdata = reg_rdata_next ;
-  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+  assign reg_error = addrmiss | wr_err | intg_err;
 
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}

diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl
@@ -194,8 +194,7 @@ from topgen.lib import Name
     .shadowed_storage_err_o(hw2reg.fatal_err_code.shadow_storage_err.de),
     .shadowed_update_err_o(hw2reg.recov_err_code.shadow_update_err.de),
     // SEC_CM: BUS.INTEGRITY
-    .intg_err_o(hw2reg.fatal_err_code.reg_intg.de),
-    .devmode_i(1'b1)
+    .intg_err_o(hw2reg.fatal_err_code.reg_intg.de)
   );
   assign hw2reg.fatal_err_code.reg_intg.d = 1'b1;
   assign hw2reg.recov_err_code.shadow_update_err.d = 1'b1;

@@ -31,8 +31,6 @@ In addition, it instantiates the following interfaces, connects them to the DUT
 * [TileLink host interface](../../../dv/sv/tl_agent/README.md)
 * CLKMGR IOs: `hw/ip/clkmgr/dv/env/clkmgr_if.sv`
 
-The Devmode ([`pins_if`](../../../dv/sv/common_ifs/README.md)) interface should be connected once the RTL adds support for it.
-
 ### Common DV utility components
 The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
 

@@ -53,10 +53,6 @@ module tb;
     .rst_n(rst_root_usb_n)
   );
 
-
-  // This is yet to be connected.
-  wire devmode;
-  pins_if #(1) devmode_if (devmode);
   tl_if tl_if (
     .clk  (clk),
     .rst_n(rst_n)
@@ -205,7 +201,6 @@ module tb;
     // FIXME Un-comment this once interrupts are created for this ip.
     // uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
 
-    uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
     uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
     uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif",
                                                  rst_shadowed_if);

diff --git a/hw/ip/clkmgr/rtl/clkmgr.sv b/hw/ip/clkmgr/rtl/clkmgr.sv
@@ -51,8 +51,7 @@ module clkmgr import clkmgr_pkg::*; (
     .tl_i,
     .tl_o,
     .reg2hw,
-    .hw2reg,
-    .devmode_i(1'b1)
+    .hw2reg
   );
 
 

diff --git a/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv b/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv
@@ -16,10 +16,7 @@ module clkmgr_reg_top (
   input  clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg, // Read
 
   // Integrity check errors
-  output logic intg_err_o,
-
-  // Config
-  input devmode_i // If 1, explicit error return for unmapped register access
+  output logic intg_err_o
 );
 
   import clkmgr_reg_pkg::* ;
@@ -119,7 +116,7 @@ module clkmgr_reg_top (
   // cdc oversampling signals
 
   assign reg_rdata = reg_rdata_next ;
-  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+  assign reg_error = addrmiss | wr_err | intg_err;
 
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}

@@ -29,7 +29,6 @@ In addition, it instantiates the following interfaces, connects them to the DUT
 * CSRNG IOs
 * Interrupts ([`pins_if`](../../../dv/sv/common_ifs/README.md)
 * Alerts ([`pins_if`](../../../dv/sv/common_ifs/README.md)
-* Devmode ([`pins_if`](../../../dv/sv/common_ifs/README.md)
 
 ### Common DV utility components
 The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

@@ -14,7 +14,7 @@ module tb;
   `include "uvm_macros.svh"
   `include "dv_macros.svh"
 
-  wire   clk, rst_n, devmode;
+  wire   clk, rst_n;
   wire   edn_disable, entropy_src_disable;
   wire   intr_cmd_req_done;
   wire   intr_entropy_req;
@@ -29,7 +29,6 @@ module tb;
   // interfaces
   clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
   pins_if#(NUM_MAX_INTERRUPTS) intr_if(interrupts);
-  pins_if#(1) devmode_if(devmode);
   pins_if#(MuBi8Width) otp_en_cs_sw_app_read_if(otp_en_cs_sw_app_read);
   pins_if#(MuBi4Width) lc_hw_debug_en_if(lc_hw_debug_en);
   tl_if tl_if(.clk(clk), .rst_n(rst_n));
@@ -103,7 +102,6 @@ module tb;
     clk_rst_if.set_active();
     uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
     uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
-    uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
     uvm_config_db#(virtual pins_if#(MuBi8Width))::set(null, "*.env", "otp_en_cs_sw_app_read_vif",
         otp_en_cs_sw_app_read_if);
     uvm_config_db#(virtual pins_if#(MuBi4Width))::set(null, "*.env", "lc_hw_debug_en_vif",

diff --git a/hw/ip/csrng/rtl/csrng.sv b/hw/ip/csrng/rtl/csrng.sv
@@ -72,8 +72,7 @@ module csrng
     .tl_o,
     .reg2hw,
     .hw2reg,
-    .intg_err_o(intg_err_alert[1]),
-    .devmode_i(1'b1)
+    .intg_err_o(intg_err_alert[1])
   );
 
   csrng_core #(

diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv
@@ -16,10 +16,7 @@ module csrng_reg_top (
   input  csrng_reg_pkg::csrng_hw2reg_t hw2reg, // Read
 
   // Integrity check errors
-  output logic intg_err_o,
-
-  // Config
-  input devmode_i // If 1, explicit error return for unmapped register access
+  output logic intg_err_o
 );
 
   import csrng_reg_pkg::* ;
@@ -119,7 +116,7 @@ module csrng_reg_top (
   // cdc oversampling signals
 
   assign reg_rdata = reg_rdata_next ;
-  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+  assign reg_error = addrmiss | wr_err | intg_err;
 
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}

@@ -29,7 +29,6 @@ In addition, it instantiates the following interfaces, connects them to the DUT
 * EDN IOs
 * Interrupts ([`pins_if`](../../../dv/sv/common_ifs/README.md)
 * Alerts ([`pins_if`](../../../dv/sv/common_ifs/README.md)
-* Devmode ([`pins_if`](../../../dv/sv/common_ifs/README.md)
 
 ### Common DV utility components
 The following utilities provide generic helper tasks and functions to perform activities that are common across the project: