The Read FIFO in SPI TPM module uses TPM CS# as a reset for both write
and read ports. The intention is to reset the FIFO at the end of every
SPI TPM transaction.

As TPM CS# is controlled by TPM host system, the timing of CS#
de-assertion (0 -> 1) is independant of the SYS_CLK. If release of CS#
coincidently hit the posedge of the SYS_CLK, there's chance the Read
FIFO depth signal may trigger metastability issues.

To avoid the issue, I may suggest two solutions quickly.

1. Convert the CS# rst synchronizer to sync assert, sync de-assert.
2. Add 2FF sync to the depth signal to eliminate metastability.

In this commit, I implement the option 2. Here's why I avoid the option 1.

Option 1 delays the assertion time of the reset on the write port of the
read FIFO by 2 SYS_CLK. To reset the internal pointers correctly, both
write/ read ports should be reset. To satisfy the requirement, CS#
should remain high (inactive) for at least 2 SYS_CLK (+ 1 SYS_CLK at
worst case). In real time scale, it is around 120ns. The minimum TPM CS#
inactive time can be as low as 50ns. So, I wanted to avoid the case.
However, in other logic inside TPM may require 2 SYS_CLK inactive time.

With the option 2, the TPM CS# inactive requirement is not needed.
However, the status represented in CSRs will be delayed by 2 SYS_CLK.
Fortunately, the read FIFO depth or notempty status are not latency
sensitive signals.

Signed-off-by: Eli Kim <[email protected]>

As the Read FIFO has been increased to max TPM transfer size, 64B,
current DIF, DV test sequence do not use the rdfifo not empty signal nor
rdfifo depth field in `TPM_STATUS`.

In previous commit, the approach to resolve the metastability issue on
RDC was to add 2FF. However, this commit removes the field so that the
data never crosses the reset domain.

Signed-off-by: Eli Kim <[email protected]>