[sram_ctrl] Minor style cleanup

hw/ip/sram_ctrl/doc/_index.md

@@ -208,12 +208,12 @@ The memory inside the SRAM controller can be used right away after a system rese
 However, since the scrambling key defaults to a predefined value, it is recommended that SW performs the following initialization steps as early in the boot process as possible.
 
 1. Request an updated ephemeral scrambling key from OTP by writing 0x1 to {{< regref "CTRL.RENEW_SCR_KEY" >}}.
-   SW can spin on {{< regref "STATUS.SCR_KEY_VALID" >}} to wait until the new key has been obtained.
-   This is however not strictly needed, since memory accesses to the SRAM will be stalled until the updated key has been obtained.
+   SW should spin on {{< regref "STATUS.SCR_KEY_VALID" >}} to wait until the new key has been obtained.
+   While this is not strictly needed since memory accesses to the SRAM will be stalled until the updated key has been obtained, the PC value upon a watchdog crash will be more informative when using a spin wait.
 
 2. (optional) Initialize the memory with pseudo random data by writing 0x1 to {{< regref "CTRL.INIT" >}}
-   SW can spin on {{< regref "STATUS.INIT_DONE" >}} to wait until the memory has been initialized.
-   This is however not strictly needed, since memory accesses to the SRAM will be stalled until the initialization is done.
+   SW should spin on {{< regref "STATUS.INIT_DONE" >}} to wait until the memory has been initialized.
+   While this is not strictly needed since memory accesses to the SRAM will be stalled until the initialization is done, the PC value upon a watchdog crash will be more informative when using a spin wait.
 
 3. (optional) Check the {{< regref "STATUS.SCR_KEY_SEED_VALID" >}} bit:
     - In case the scrambling key seeds have been fully provisioned to OTP, this bit should be set to 0x1. A value of 0x0 indicates that the OTP could be malfunctioning or has been tampered with.

hw/ip/sram_ctrl/rtl/sram_ctrl.sv

@@ -136,18 +136,21 @@ module sram_ctrl
   assign hw2reg.status.init_error.d  = 1'b1;
   assign hw2reg.status.init_error.de = init_error;
 
+  logic alert_req;
+  assign alert_req = (|bus_integ_error) | init_error;
+
   prim_alert_sender #(
     .AsyncOn(AlertAsyncOn[0]),
     .IsFatal(1)
   ) u_prim_alert_sender_parity (
     .clk_i,
     .rst_ni,
-    .alert_test_i  ( alert_test                    ),
-    .alert_req_i   ( |bus_integ_error | init_error ),
-    .alert_ack_o   (                               ),
-    .alert_state_o (                               ),
-    .alert_rx_i    ( alert_rx_i[0]                 ),
-    .alert_tx_o    ( alert_tx_o[0]                 )
+    .alert_test_i  ( alert_test    ),
+    .alert_req_i   ( alert_req     ),
+    .alert_ack_o   (               ),
+    .alert_state_o (               ),
+    .alert_rx_i    ( alert_rx_i[0] ),
+    .alert_tx_o    ( alert_tx_o[0] )
   );
 
   /////////////////////////
@@ -176,15 +179,15 @@ module sram_ctrl
   logic local_esc, local_esc_reg;
   // This signal only aggregates registered escalation signals and is used for transaction
   // blocking further below, which is on a timing-critical path.
-  assign local_esc_reg = reg2hw.status.escalated.q  ||
-                         reg2hw.status.init_error.q ||
+  assign local_esc_reg = reg2hw.status.escalated.q  |
+                         reg2hw.status.init_error.q |
                          reg2hw.status.bus_integ_error.q;
   // This signal aggregates all escalation trigger signals, including the ones that are generated in
   // the same cycle such as init_error and bus_integ_error. It is used for countermeasures that are
   // not on the critical path (such as clearing the scrambling keys).
-  assign local_esc = escalate         ||
-                     init_error       ||
-                     |bus_integ_error ||
+  assign local_esc = escalate           |
+                     init_error         |
+                     (|bus_integ_error) |
                      local_esc_reg;
 
   // Convert registered, local escalation sources to a multibit signal and combine this with