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I2C has four FIFOs; three are 64 entries deep and one is more than 256 entries deep. They are all between 8 and 13 bit wide. That's more than 3.5k bit for data storage alone.
Currently these FIFOs are composed of FFs, which isn't the most efficient way to store such amounts of data. Replacing them with one or multiple SRAMs (which can be single-ported if control logic correctly accounts for it) should significantly reduce I2C's area.
The text was updated successfully, but these errors were encountered:
I2C has four FIFOs; three are 64 entries deep and one is more than 256 entries deep. They are all between 8 and 13 bit wide. That's more than 3.5k bit for data storage alone.
Currently these FIFOs are composed of FFs, which isn't the most efficient way to store such amounts of data. Replacing them with one or multiple SRAMs (which can be single-ported if control logic correctly accounts for it) should significantly reduce I2C's area.
The text was updated successfully, but these errors were encountered: