[chip-test] chip_sw_pwrmgr_escalation_reset

[johngt]

Test point name

chip_sw_pwrmgr_escalation_reset

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

• None
• CW310
• Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• Device-side (C) component developed
• Bazel build rules developed
• Host-side component developed
• Test added to dvsim nightly regression (and passing at time of checking)
• For SiVal test cases, test is running relevant FPGA or silicon regression

[matutem]

I don't know why this issue was created: in the description at https://cs.opensource.google/opentitan/opentitan/+/master:hw/top_earlgrey/data/ip/chip_pwrmgr_testplan.hjson;drc=2d6a8ad26708e4c2681c8ddc2a0fa1c911a4461d;l=486 it says clearly This is not suitable for sival, and in si_stage it is marked as None. Perhaps these should be used to filter out what seems to be a flow that detects missing test items? I will similarly close other similar issues.