[chip-test] chip_sw_entropy_src_csrng

[johngt]

Test point name

chip_sw_entropy_src_csrng

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

• None
• CW310
• Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• Device-side (C) component developed
• Bazel build rules developed
• Host-side component developed
• Test added to dvsim nightly regression (and passing at time of checking)
• For SiVal test cases, test is running relevant FPGA or silicon regression

[johngt]

Possible duplicate of #20143

[johngt]

@vogelpi / @h-filali - this test exists already but the test is not linked to Bazel field of testplan. Please link that in and then close this issue.

[h-filali]

@vogelpi / @h-filali - this test exists already but the test is not linked to Bazel field of testplan. Please link that in and then close this issue.

Done as part of #21529