Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[chip-test] chip_sw_clkmgr_jitter_cycle_measurements #20230

Closed
6 of 10 tasks
matutem opened this issue Oct 30, 2023 · 0 comments · Fixed by #20283
Closed
6 of 10 tasks

[chip-test] chip_sw_clkmgr_jitter_cycle_measurements #20230

matutem opened this issue Oct 30, 2023 · 0 comments · Fixed by #20283
Assignees
@matutem
Labels
Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation

Comments

@matutem
Copy link
Contributor

matutem commented Oct 30, 2023 •
edited
Loading

Test point name

chip_sw_clkmgr_jitter_cycle_measurements

Host side component

None Required

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

matutem

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • HJSON test plan updated with test name (so it shows up in the dashboard)
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression
@matutem matutem added Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation labels Oct 30, 2023
@matutem matutem self-assigned this Oct 30, 2023
matutem added a commit to matutem/opentitan that referenced this issue Nov 7, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
a30023b 
…testpoint

Fixes lowRISC#20230

Signed-off-by: Guillermo Maturana <[email protected]>
@matutem matutem mentioned this issue Nov 7, 2023
Merged
matutem added a commit to matutem/opentitan that referenced this issue Nov 7, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
2d783ae 
…testpoint

Fixes lowRISC#20230

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit to matutem/opentitan that referenced this issue Nov 7, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
599d043 
…testpoint

Fixes lowRISC#20230

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit that referenced this issue Nov 8, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
a2c84ab 
…testpoint

Fixes #20230

Signed-off-by: Guillermo Maturana <[email protected]>
@msfschaffner msfschaffner mentioned this issue Feb 15, 2024
Closed
@matutem matutem mentioned this issue Feb 15, 2024
Closed
@jwnrt jwnrt changed the title [chip_sw_clkmgr_jitter] [chip-test] chip_sw_clkmgr_jitter_cycle_measurements Oct 28, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@matutem matutem

Labels
Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation
Projects
None yet
Milestone
No milestone
Development

Successfully merging a pull request may close this issue.

[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements testpoint matutem/opentitan
1 participant
@matutem