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[chip-test] chip_sw_i2c_host_tx_rx #19834

Closed
1 of 10 tasks
marnovandermaas opened this issue Oct 4, 2023 · 0 comments · Fixed by #20290
Closed
1 of 10 tasks

[chip-test] chip_sw_i2c_host_tx_rx #19834

marnovandermaas opened this issue Oct 4, 2023 · 0 comments · Fixed by #20290
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@engdoreis
Labels
Component:ChipLevelTest Used to filter the chip-level test backlog IP:i2c SiVal:TestRefactoring Top-level test refactoring needed to support SiVal
Milestone
Earlgrey ES SV2

Comments

@marnovandermaas
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Test point name

chip_sw_i2c_host_tx_rx

Host side component

Rust

OpenTitanTool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation Targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

marnovandermaas

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • HJSON test plan updated with test name (so it shows up in the dashboard)
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 4
@marnovandermaas marnovandermaas added IP:i2c Component:ChipLevelTest Used to filter the chip-level test backlog SiVal:draft/WIP Issue in draft state. Not assigned to a project yet. labels Oct 4, 2023
@marnovandermaas marnovandermaas mentioned this issue Oct 4, 2023
Closed
10 tasks
@marnovandermaas marnovandermaas added SiVal:TestRefactoring Top-level test refactoring needed to support SiVal and removed SiVal:draft/WIP Issue in draft state. Not assigned to a project yet. labels Oct 10, 2023
@marnovandermaas marnovandermaas added this to the Earlgrey ES SV2 milestone Oct 10, 2023
@engdoreis engdoreis mentioned this issue Nov 8, 2023
Merged
@hcallahan-lowrisc hcallahan-lowrisc mentioned this issue Jun 6, 2024
Closed
1 task
@jwnrt jwnrt changed the title [chip-test,sival] I2C host transmit & receive [chip-test] chip_sw_i2c_host_tx_rx Oct 28, 2024
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Assignees

@engdoreis engdoreis

Labels
Component:ChipLevelTest Used to filter the chip-level test backlog IP:i2c SiVal:TestRefactoring Top-level test refactoring needed to support SiVal
Projects
None yet
Milestone
Earlgrey ES SV2
Development

Successfully merging a pull request may close this issue.

[Sival, i2c] chip_sw_i2c_host_tx_rx engdoreis/opentitan
2 participants
@marnovandermaas @engdoreis