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[i2c,dv] Check I2C timing compliance via a SVA-based protocol checker #18722

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marnovandermaas opened this issue May 23, 2023 · 6 comments
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Component:DV DV issue: testbench, test case, etc. Earlgrey-PROD Candidate Temporary label to triage issues into Earlgrey-PROD Milestones IP:i2c Priority:P2 Priority: medium

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@marnovandermaas
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Description

This issue is here to track the work required to add assertions to the test bench. For example, SDA should not change at the same time as SCL, which caused the following issue: #18718

@msfschaffner
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msfschaffner commented May 24, 2023

Discussed in the V2 meeting, decided to:

@GregAC
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GregAC commented May 25, 2023

@marnovandermaas could you do the assertion for SDA/SCL not changing together ASAP as an aid to verifying: #18729?

@marnovandermaas
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@GregAC I've added this assertion as a commit to this PR: #18729

@msfschaffner
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Moving to M2.5 backlog since the SDA / SCL assertion has been merged.

@msfschaffner msfschaffner added the Earlgrey-PROD Candidate Temporary label to triage issues into Earlgrey-PROD Milestones label Oct 7, 2023
@msfschaffner msfschaffner added Priority:P2 Priority: medium and removed Priority:P1 Priority: high labels Jan 26, 2024
@andreaskurth
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V3, so M5 looks correct

@hcallahan-lowrisc hcallahan-lowrisc changed the title [i2c,dv] I2C timing assertions [i2c,dv] Check I2C timing compliance via a SVA-based protocol checker Jun 20, 2024
@hcallahan-lowrisc
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V3, hence moved to P4

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Component:DV DV issue: testbench, test case, etc. Earlgrey-PROD Candidate Temporary label to triage issues into Earlgrey-PROD Milestones IP:i2c Priority:P2 Priority: medium
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