[SPI Host] SPI Host test plan

[johngt]

Description

This issue details what has been tested as part of the SPI Host test plan.

The following features have been tested as part of this issue:

• The SPI host features:
  • Speed and Direction

    Direction/Speed	Dummy	Rx	Tx	Bidiretional
    Standard	x	x	x	x
    Dual	x	x	x	N/A
    Quad	x	x	x	N/A

  • TX FIFO (288 bytes).
  • RX FIFO (256 bytes).
  • 3 Bytes addressing mode.
  • 4 Bytes addressing mode.
  • Polarity phases (CPOL, CPHA) --> lower priority as there only one mode used in practice.
    • CPOL = 0
    • CPHA = 0
  • Chip select automatic control.
    • Merge commands with COMMAND.CSAAT.
  • Interrupts.
    • Error
    • Event
  • Error handling.
    • Issue command with SPI STATUS.READY is low.
• The following commands of a SPI NOR flash:
  • READ_JEDEC_ID (0x9F)
  • READ_SFDP (0x5A)
  • WRITE_ENABLE (0x06)
  • READ_STATUS_REGISTER (0x05)
  • WRITE_STATUS_REGISTER (0x01)
  • READ_DATA (0x03)
  • READ_FAST (0x0B)
  • PAGE_WRITE (0x02)
  • SECTOR_ERASE (0x20)
  • BLOCK_ERASE (0x52)
  • BLOCK_ERASE (0xD8)
  • CHIP_ERASE (0xC7/0x60)
  • RESET_DEVICE (0x99)
  • ENTER_QPI_MODE (0x38)
  • FAST_READ_DUAL_OUTPUT (0x3B)
  • QUAD_PAGE_WRITE (0x32)
  • FAST_READ_QUAD_OUTPUT (0x6B)
  • ENTER_4BYTE_ADDRESS_MODE(0xB7)
  • EXIT_4BYTE_ADDRESS_MODE(0xD8)

Please see the related closed source issue in the embargoed repo for more specific details about devices
https://github.com/lowRISC/ot-discrete-eg/issues/10