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[test-triage] chip_sw_pattgen_ios Timeout #18465

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johngt opened this issue May 9, 2023 · 4 comments
Closed
1 task

[test-triage] chip_sw_pattgen_ios Timeout #18465

johngt opened this issue May 9, 2023 · 4 comments
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Component:ChipLevelTest Used to filter the chip-level test backlog Component:DV DV issue: testbench, test case, etc. Component:TestTriage Priority:P2 Priority: medium

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@johngt
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johngt commented May 9, 2023

Hierarchy of regression failure

Chip Level

Failure Description

0.chip_sw_pattgen_ios.137904608
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest/run.log

  UVM_ERROR @ 8243.607436 us: (chip_sw_base_vseq.sv:254) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_patt_ios_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 5000000 ns
  
  UVM_INFO @ 8243.607436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Steps to Reproduce

  • GitHub Revision: bc163b70f
  • dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
    ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_pattgen_ios --build-seed 488598207 --fixed-seed 137904608 --waves fsdb
  • Kokoro build number if applicable

Tests with similar or related failures

  • chip_sw_pattgen_ios
@johngt johngt added Component:DV DV issue: testbench, test case, etc. Priority:P2 Priority: medium Component:TestTriage labels May 9, 2023
@johngt johngt added this to the Discrete: M2.5 milestone May 9, 2023
@johngt
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johngt commented May 9, 2023

Note previous timeout issue
https://github.com//lowRISC/opentitan/issues/16477

@luismarques
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failure reproduced. run.log: https://gist.github.com/luismarques/dafd36eb34b10226d2224749b8604f0a

@johngt
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johngt commented May 10, 2023

Thanks @luismarques
@GregAC
It looks like in the error reports that Ibex alerts /tlul / pattgen may be implicated

"../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 296: tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_rv_core_ibex__corei.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A: started at 8243607436ps failed at 8243607436ps
	Offending '((pend_req[0].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
UVM_ERROR @ 8243.607436 us: (tlul_assert.sv:296) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 8243.607436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

Increasing priority as this is no longer just a timeout issue.

@johngt johngt added Priority:P1 Priority: high and removed Priority:P2 Priority: medium labels May 10, 2023
@moidx moidx added the Component:ChipLevelTest Used to filter the chip-level test backlog label May 10, 2023
@moidx moidx self-assigned this May 10, 2023
@johngt
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johngt commented Jun 30, 2023

Not seen this test error for some time.
Closing and tagging @luismarques / @engdoreis in case they want to re-run and see if this is still an issue, but will assume it is not and close this out.

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Labels
Component:ChipLevelTest Used to filter the chip-level test backlog Component:DV DV issue: testbench, test case, etc. Component:TestTriage Priority:P2 Priority: medium
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