[chip, dv] Update test description of chip_sw_keymgr_sideload_kmac_error

Addressed the TBD in the testplan

Signed-off-by: Weicai Yang <[email protected]>

hw/top_earlgrey/data/chip_testplan.hjson

@@ -2434,13 +2434,18 @@
     {
       name: chip_sw_keymgr_sideload_kmac_error
       desc: '''
-            Verify the effect of KMAC returning an error during keymgr sideload operation.
+            Verify the effect of KMAC returning an error during a keymgr operation.
 
-            - Follow the steps in `chip_sw_keymgr_sideload_kmac` test.
+            - Configure keymgr to enter any of the 3 working states.
+            - Issue a keymgr operations.
             - While the KMAC is actively computing the digest, glitch the KMAC app sparse FSM to
               trigger a fault.
-            - Verify that KMAC returns an error signal to the keymgr.
-            - TBD
+            - Verify that KMAC returns an error signal to the keymgr via checking keymgr CSRs, when
+              the operation is done:
+              - Check `op_status` is set to `DONE_ERROR`.
+              - Check `fault_status.kmac_done` is set to 1.
+            - Note: at end of the C test, issue a reset if the test is running in DV, otherwise, the
+              fatal alert will prevent the simulation from finishing.
             '''
       stage: V3
       tests: []