From b4c80a621a824415ecb7a0391abd6963dc638e96 Mon Sep 17 00:00:00 2001 From: Andreas Kurth Date: Thu, 22 Feb 2024 06:50:46 +0000 Subject: [PATCH] [top_earlgrey] Add fourth I2C The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - rules/const.bzl - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue #19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth --- .../data/otp_ctrl_img_owner_sw_cfg.hjson | 8 +- hw/ip/pinmux/doc/registers.md | 2048 +++--- .../rstmgr/dv/cov/rstmgr_unr_excl.el | 4 + .../rstmgr/dv/env/rstmgr_env_pkg.sv | 1 + .../rstmgr/dv/env/rstmgr_scoreboard.sv | 1 + hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv | 2 + hw/top_earlgrey/cdc/cdc_waivers.data.tcl | 2 + .../data/autogen/top_earlgrey.gen.hjson | 514 +- hw/top_earlgrey/data/chip_conn_testplan.hjson | 16 + .../data/ip/chip_i2c_testplan.hjson | 3 +- .../data/ip/chip_rstmgr_testplan.hjson | 4 +- hw/top_earlgrey/data/pins_cw310.xdc | 4 +- .../data/pins_cw310_hyperdebug.xdc | 4 +- hw/top_earlgrey/data/pins_cw341.xdc | 4 +- hw/top_earlgrey/data/top_earlgrey.hjson | 9 + hw/top_earlgrey/data/xbar_peri.hjson | 10 +- hw/top_earlgrey/doc/datasheet.md | 2 +- hw/top_earlgrey/doc/design/README.md | 1 + .../doc/top_earlgrey_block_diagram.svg | 1680 ++++- .../dv/autogen/rstmgr_tgl_excl.cfg | 1 + .../dv/autogen/tb__alert_handler_connect.sv | 113 +- .../dv/autogen/tb__xbar_connect.sv | 2 + .../dv/autogen/xbar_env_pkg__params.sv | 5 + hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg | 4 + hw/top_earlgrey/dv/chip_sim_cfg.hjson | 7 + hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg | 1 + .../dv/env/autogen/chip_env_pkg__params.sv | 3 +- hw/top_earlgrey/dv/env/chip_common_pkg.sv | 2 +- hw/top_earlgrey/dv/env/chip_if.sv | 19 +- .../chip_sw_all_escalation_resets_vseq.sv | 1 + .../seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv | 4 +- hw/top_earlgrey/dv/tb/tb.sv | 2 + .../formal/conn_csvs/clkmgr_peri.csv | 1 + .../formal/conn_csvs/rstmgr_resets_o.csv | 1 + .../formal/conn_csvs/rstmgr_rst_en.csv | 1 + .../ip/ast/data/ast_cdc_abstract.sgdc | 2 + .../ip/pinmux/data/autogen/pinmux.hjson | 4 +- .../ip/pinmux/doc/autogen/pinout_asic.md | 2 + .../ip/pinmux/doc/autogen/pinout_cw310.md | 2 + .../ip/pinmux/doc/autogen/pinout_cw340.md | 2 + .../ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv | 2062 +++--- .../ip/pinmux/rtl/autogen/pinmux_reg_top.sv | 4436 ++++++------- .../data/autogen/xbar_peri.gen.hjson | 19 + .../ip/xbar_peri/data/autogen/xbar_peri.hjson | 6 + .../xbar_peri/dv/autogen/tb__xbar_connect.sv | 1 + .../ip/xbar_peri/dv/autogen/xbar_cover.cfg | 4 + .../dv/autogen/xbar_env_pkg__params.sv | 4 + .../ip/xbar_peri/dv/autogen/xbar_peri_bind.sv | 6 + .../ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv | 45 +- .../ip/xbar_peri/rtl/autogen/xbar_peri.sv | 262 +- .../alert_handler/data/alert_handler.hjson | 80 +- .../top_earlgrey_alert_handler.ipconfig.hjson | 80 +- .../alert_handler/doc/theory_of_operation.md | 4 +- .../rtl/alert_handler_reg_pkg.sv | 1232 ++-- .../rtl/alert_handler_reg_top.sv | 2802 ++++---- .../ip_autogen/rstmgr/data/rstmgr.hjson | 8 +- .../data/top_earlgrey_rstmgr.ipconfig.hjson | 29 + .../ip_autogen/rstmgr/doc/registers.md | 40 +- .../rstmgr/dv/cov/rstmgr_unr_excl.el | 4 + .../rstmgr/dv/env/rstmgr_env_pkg.sv | 1 + .../rstmgr/dv/env/rstmgr_scoreboard.sv | 1 + .../ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv | 2 + .../dv/sva/rstmgr_rst_en_track_sva_if.sv | 13 + .../ip_autogen/rstmgr/rtl/rstmgr.sv | 42 +- .../ip_autogen/rstmgr/rtl/rstmgr_pkg.sv | 5 +- .../ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv | 58 +- .../ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv | 163 +- .../ip_autogen/rv_plic/data/rv_plic.hjson | 122 +- .../data/top_earlgrey_rv_plic.ipconfig.hjson | 2 +- .../ip_autogen/rv_plic/rtl/rv_plic.sv | 19 +- .../ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv | 530 +- .../ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv | 5658 +++++++++++------ hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 613 +- .../rtl/autogen/top_earlgrey_pkg.sv | 309 +- .../sw/autogen/chip/top_earlgrey.rs | 968 +-- hw/top_earlgrey/sw/autogen/top_earlgrey.c | 20 +- hw/top_earlgrey/sw/autogen/top_earlgrey.h | 517 +- .../sw/autogen/top_earlgrey_memory.h | 17 + rules/const.bzl | 2 +- .../lib/dif/dif_alert_handler_unittest.cc | 2 +- sw/device/lib/dif/dif_rstmgr.c | 2 +- sw/device/lib/dif/dif_rv_plic_unittest.cc | 9 +- sw/device/lib/testing/i2c_testutils.c | 25 + sw/device/lib/testing/json/pinmux.h | 4 + .../tests/alert_handler_lpg_reset_toggle.c | 21 +- sw/device/tests/autogen/alert_test.c | 19 + sw/device/tests/autogen/plic_all_irqs_test.c | 57 + sw/device/tests/i2c_target_test.c | 6 +- sw/device/tests/pmod/i2c_host_eeprom_test.c | 6 +- sw/device/tests/pmod/i2c_host_fram_test.c | 6 +- sw/device/tests/power_virus_systemtest.c | 24 +- sw/device/tests/rstmgr_alert_info_test.c | 14 +- sw/device/tests/rstmgr_sw_rst_ctrl_test.c | 20 + .../tests/sim_dv/all_escalation_resets_test.c | 5 + .../tests/sim_dv/i2c_device_tx_rx_test.c | 10 +- sw/device/tests/sim_dv/i2c_host_tx_rx_test.c | 31 + .../opentitanlib/src/chip/autogen/earlgrey.rs | 120 +- sw/host/opentitanlib/src/otp/alert_handler.rs | 6 +- .../src/otp/alert_handler_regs.rs | 585 +- 99 files changed, 15362 insertions(+), 10292 deletions(-) diff --git a/hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson b/hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson index 3af295618c5d82..f4ddc168cd20a7 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson +++ b/hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson @@ -187,19 +187,19 @@ }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", - value: "0xf23b13fb", + value: "0xf2792a29", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", - value: "0x9c933414", + value: "0x9cd10dc6", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", - value: "0x68d8d091", + value: "0x689ae943", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", - value: "0x36ed9cb0", + value: "0x36afa562", } ], } diff --git a/hw/ip/pinmux/doc/registers.md b/hw/ip/pinmux/doc/registers.md index a5843f9b5b0031..345bcb32154939 100644 --- a/hw/ip/pinmux/doc/registers.md +++ b/hw/ip/pinmux/doc/registers.md @@ -68,516 +68,520 @@ Similar register descriptions can be generated with different parameterizations. | pinmux.[`MIO_PERIPH_INSEL_REGWEN_54`](#mio_periph_insel_regwen) | 0xdc | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_55`](#mio_periph_insel_regwen) | 0xe0 | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_56`](#mio_periph_insel_regwen) | 0xe4 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0xe8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0xec | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0xf0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0x11c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0x120 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0x124 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0x128 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0x12c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0x130 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0x134 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0x138 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0x13c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0x140 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0x144 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0x148 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0x14c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0x150 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0x154 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x158 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x15c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x160 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x164 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x168 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x16c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x170 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_35`](#mio_periph_insel) | 0x174 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_36`](#mio_periph_insel) | 0x178 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_37`](#mio_periph_insel) | 0x17c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_38`](#mio_periph_insel) | 0x180 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_39`](#mio_periph_insel) | 0x184 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_40`](#mio_periph_insel) | 0x188 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_41`](#mio_periph_insel) | 0x18c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_42`](#mio_periph_insel) | 0x190 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_43`](#mio_periph_insel) | 0x194 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_44`](#mio_periph_insel) | 0x198 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_45`](#mio_periph_insel) | 0x19c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_46`](#mio_periph_insel) | 0x1a0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_47`](#mio_periph_insel) | 0x1a4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_48`](#mio_periph_insel) | 0x1a8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_49`](#mio_periph_insel) | 0x1ac | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_50`](#mio_periph_insel) | 0x1b0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_51`](#mio_periph_insel) | 0x1b4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_52`](#mio_periph_insel) | 0x1b8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_53`](#mio_periph_insel) | 0x1bc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_54`](#mio_periph_insel) | 0x1c0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_55`](#mio_periph_insel) | 0x1c4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_56`](#mio_periph_insel) | 0x1c8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x1cc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x1d0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x1d4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x1d8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x1dc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x1e0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x1e4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x1e8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x1ec | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x1f0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x1f4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x1f8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x1fc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x200 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x204 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x208 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x20c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x210 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x214 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x218 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x21c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x220 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x224 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x228 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x22c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x230 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x234 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x238 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x23c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x240 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x244 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x248 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x24c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x250 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x254 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x258 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x25c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x260 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x264 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x268 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x26c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x270 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x274 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x278 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x27c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x280 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x284 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x288 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x28c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x290 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x294 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x298 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x29c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x2a0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x2a4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x2a8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x2ac | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x2b0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x2b4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x2b8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x2bc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x2c0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x2c4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x2c8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x2cc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x2d0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x2d4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x2d8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x2dc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x2e0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x2e4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x2e8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x2ec | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x2f0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x2f4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x2f8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x2fc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x300 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x304 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x308 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x30c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x310 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x314 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x318 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x31c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x320 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x324 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x328 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x32c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x330 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x334 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x338 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x33c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x340 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x344 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x348 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x34c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x350 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x354 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x358 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x35c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x360 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x364 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x368 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x36c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x370 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x374 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x378 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x37c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x380 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x384 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x388 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x38c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x390 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x394 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x398 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x39c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x3a0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x3a4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x3a8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x3ac | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x3b0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x3b4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x3b8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x3bc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x3c0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x3c4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x3c8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x3cc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x3d0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x3d4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x3d8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x3dc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x3e0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x3e4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x3e8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x3ec | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x3f0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x3f4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x3f8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x3fc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x400 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x404 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x408 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x40c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x410 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x414 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x418 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x41c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x420 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x424 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x428 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x42c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x430 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x434 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x438 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x43c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x440 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x444 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x448 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x44c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x450 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x454 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x458 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x45c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x460 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x464 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x468 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x46c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x470 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x474 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x478 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x47c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x480 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x484 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x488 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x48c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x490 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x494 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x498 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x49c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x4a0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x4a4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x4a8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x4ac | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x4b0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x4b4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x4b8 | 4 | Muxed pad attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x4bc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x4c0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x4c4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x4c8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x4cc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x4d0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x4d4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x4d8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x4dc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x4e0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x4e4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x4e8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x4ec | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x4f0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x4f4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x4f8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x4fc | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x500 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x504 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x508 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x50c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x510 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x514 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x518 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x51c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x520 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x524 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x528 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x52c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x530 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x534 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x538 | 4 | Dedicated pad attributes. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#MIO_PAD_SLEEP_STATUS_0) | 0x53c | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#MIO_PAD_SLEEP_STATUS_1) | 0x540 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x544 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x548 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x54c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x550 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x554 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x558 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x55c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x560 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x564 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x568 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x56c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x570 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x574 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x578 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x57c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x580 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x584 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x588 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x58c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x590 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x594 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x598 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x59c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x5a0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x5a4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x5a8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x5ac | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x5b0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x5b4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x5b8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x5bc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x5c0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x5c4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x5c8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x5cc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x5d0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x5d4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x5d8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x5dc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x5e0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x5e4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x5e8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x5ec | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x5f0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x5f4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x5f8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x5fc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x600 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x604 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x608 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x60c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x610 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x614 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x618 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x61c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x620 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x624 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x628 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x62c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x630 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x634 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x638 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x63c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x640 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x644 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x648 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x64c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x650 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x654 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x658 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x65c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x660 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x664 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x668 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x66c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x670 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x674 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x678 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x67c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x680 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x684 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x688 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x68c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x690 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x694 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x698 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x69c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x6a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x6a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x6a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x6ac | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x6b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x6b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x6b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x6bc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x6c0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x6c4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x6c8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x6cc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x6d0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x738 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x73c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x740 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x764 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x768 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x76c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x770 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x774 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`DIO_PAD_SLEEP_STATUS`](#DIO_PAD_SLEEP_STATUS) | 0x778 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x77c | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x780 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x784 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x788 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x78c | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x790 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x794 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x798 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x79c | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x7a0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x7a4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x7a8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x7ac | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x7b0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x7b4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x7b8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x7bc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x7c0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x7c4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x7c8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x7cc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x7d0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x7d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x7d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x7dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x7e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x7e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x7e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x7ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x7f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x7f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x7f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x7fc | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x800 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x804 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x808 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x80c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x810 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x814 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x818 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x81c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x820 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x824 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x828 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x82c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x830 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x834 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x838 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x83c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x840 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x844 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x848 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x84c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x850 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x854 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x858 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x85c | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x860 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x864 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x868 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x86c | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x870 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x874 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x878 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x87c | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x880 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x884 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x888 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x88c | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x890 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x894 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x898 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x89c | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x8a0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x8a4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x8a8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x8ac | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x8b0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x8b4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x8b8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x8bc | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x8c0 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x8c4 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x8c8 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x8cc | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x8d0 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x8d4 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x8d8 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_CAUSE`](#WKUP_CAUSE) | 0x8dc | 4 | Cause registers for wakeup detectors. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_57`](#mio_periph_insel_regwen) | 0xe8 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_58`](#mio_periph_insel_regwen) | 0xec | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0xf0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0x11c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0x120 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0x124 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0x128 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0x12c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0x130 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0x134 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0x138 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0x13c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0x140 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0x144 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0x148 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0x14c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0x150 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0x154 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0x158 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0x15c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x160 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x164 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x168 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x16c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x170 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x174 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x178 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_35`](#mio_periph_insel) | 0x17c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_36`](#mio_periph_insel) | 0x180 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_37`](#mio_periph_insel) | 0x184 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_38`](#mio_periph_insel) | 0x188 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_39`](#mio_periph_insel) | 0x18c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_40`](#mio_periph_insel) | 0x190 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_41`](#mio_periph_insel) | 0x194 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_42`](#mio_periph_insel) | 0x198 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_43`](#mio_periph_insel) | 0x19c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_44`](#mio_periph_insel) | 0x1a0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_45`](#mio_periph_insel) | 0x1a4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_46`](#mio_periph_insel) | 0x1a8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_47`](#mio_periph_insel) | 0x1ac | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_48`](#mio_periph_insel) | 0x1b0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_49`](#mio_periph_insel) | 0x1b4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_50`](#mio_periph_insel) | 0x1b8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_51`](#mio_periph_insel) | 0x1bc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_52`](#mio_periph_insel) | 0x1c0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_53`](#mio_periph_insel) | 0x1c4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_54`](#mio_periph_insel) | 0x1c8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_55`](#mio_periph_insel) | 0x1cc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_56`](#mio_periph_insel) | 0x1d0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_57`](#mio_periph_insel) | 0x1d4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_58`](#mio_periph_insel) | 0x1d8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x1dc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x1e0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x1e4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x1e8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x1ec | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x1f0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x1f4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x1f8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x1fc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x200 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x204 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x208 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x20c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x210 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x214 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x218 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x21c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x220 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x224 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x228 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x22c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x230 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x234 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x238 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x23c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x240 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x244 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x248 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x24c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x250 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x254 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x258 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x25c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x260 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x264 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x268 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x26c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x270 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x274 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x278 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x27c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x280 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x284 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x288 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x28c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x290 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x294 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x298 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x29c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x2a0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x2a4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x2a8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x2ac | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x2b0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x2b4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x2b8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x2bc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x2c0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x2c4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x2c8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x2cc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x2d0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x2d4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x2d8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x2dc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x2e0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x2e4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x2e8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x2ec | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x2f0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x2f4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x2f8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x2fc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x300 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x304 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x308 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x30c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x310 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x314 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x318 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x31c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x320 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x324 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x328 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x32c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x330 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x334 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x338 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x33c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x340 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x344 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x348 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x34c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x350 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x354 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x358 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x35c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x360 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x364 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x368 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x36c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x370 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x374 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x378 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x37c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x380 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x384 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x388 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x38c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x390 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x394 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x398 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x39c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x3a0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x3a4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x3a8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x3ac | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x3b0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x3b4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x3b8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x3bc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x3c0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x3c4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x3c8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x3cc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x3d0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x3d4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x3d8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x3dc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x3e0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x3e4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x3e8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x3ec | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x3f0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x3f4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x3f8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x3fc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x400 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x404 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x408 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x40c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x410 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x414 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x418 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x41c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x420 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x424 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x428 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x42c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x430 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x434 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x438 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x43c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x440 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x444 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x448 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x44c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x450 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x454 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x458 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x45c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x460 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x464 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x468 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x46c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x470 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x474 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x478 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x47c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x480 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x484 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x488 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x48c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x490 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x494 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x498 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x49c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x4a0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x4a4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x4a8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x4ac | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x4b0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x4b4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x4b8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x4bc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x4c0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x4c4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x4c8 | 4 | Muxed pad attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x4cc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x4d0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x4d4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x4d8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x4dc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x4e0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x4e4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x4e8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x4ec | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x4f0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x4f4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x4f8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x4fc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x500 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x504 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x508 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x50c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x510 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x514 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x518 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x51c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x520 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x524 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x528 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x52c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x530 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x534 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x538 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x53c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x540 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x544 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x548 | 4 | Dedicated pad attributes. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#MIO_PAD_SLEEP_STATUS_0) | 0x54c | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#MIO_PAD_SLEEP_STATUS_1) | 0x550 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x554 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x558 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x55c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x560 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x564 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x568 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x56c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x570 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x574 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x578 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x57c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x580 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x584 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x588 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x58c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x590 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x594 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x598 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x59c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x5a0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x5a4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x5a8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x5ac | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x5b0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x5b4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x5b8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x5bc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x5c0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x5c4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x5c8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x5cc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x5d0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x5d4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x5d8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x5dc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x5e0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x5e4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x5e8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x5ec | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x5f0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x5f4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x5f8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x5fc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x600 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x604 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x608 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x60c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x610 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x614 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x618 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x61c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x620 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x624 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x628 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x62c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x630 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x634 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x638 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x63c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x640 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x644 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x648 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x64c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x650 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x654 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x658 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x65c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x660 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x664 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x668 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x66c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x670 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x674 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x678 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x67c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x680 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x684 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x688 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x68c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x690 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x694 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x698 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x69c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x6a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x6a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x6a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x6ac | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x6b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x6b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x6b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x6bc | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x6c0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x6c4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x6c8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x6cc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x6d0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x738 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x73c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x740 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x764 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x768 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x76c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x770 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x774 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x778 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x77c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x780 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x784 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`DIO_PAD_SLEEP_STATUS`](#DIO_PAD_SLEEP_STATUS) | 0x788 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x78c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x790 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x794 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x798 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x79c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x7a0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x7a4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x7a8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x7ac | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x7b0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x7b4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x7b8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x7bc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x7c0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x7c4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x7c8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x7cc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x7d0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x7d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x7d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x7dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x7e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x7e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x7e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x7ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x7f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x7f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x7f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x7fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x800 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x804 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x808 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x80c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x810 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x814 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x818 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x81c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x820 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x824 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x828 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x82c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x830 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x834 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x838 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x83c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x840 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x844 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x848 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x84c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x850 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x854 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x858 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x85c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x860 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x864 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x868 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x86c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x870 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x874 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x878 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x87c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x880 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x884 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x888 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x88c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x890 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x894 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x898 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x89c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x8a0 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x8a4 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x8a8 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x8ac | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x8b0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x8b4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x8b8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x8bc | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x8c0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x8c4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x8c8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x8cc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x8d0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x8d4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x8d8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x8dc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x8e0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x8e4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x8e8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_CAUSE`](#WKUP_CAUSE) | 0x8ec | 4 | Cause registers for wakeup detectors. | ## ALERT_TEST Alert Test Register @@ -662,6 +666,8 @@ Register write enable for MIO peripheral input selects. | MIO_PERIPH_INSEL_REGWEN_54 | 0xdc | | MIO_PERIPH_INSEL_REGWEN_55 | 0xe0 | | MIO_PERIPH_INSEL_REGWEN_56 | 0xe4 | +| MIO_PERIPH_INSEL_REGWEN_57 | 0xe8 | +| MIO_PERIPH_INSEL_REGWEN_58 | 0xec | ### Fields @@ -684,63 +690,65 @@ For each peripheral input, this selects the muxable pad input. | Name | Offset | |:--------------------|:---------| -| MIO_PERIPH_INSEL_0 | 0xe8 | -| MIO_PERIPH_INSEL_1 | 0xec | -| MIO_PERIPH_INSEL_2 | 0xf0 | -| MIO_PERIPH_INSEL_3 | 0xf4 | -| MIO_PERIPH_INSEL_4 | 0xf8 | -| MIO_PERIPH_INSEL_5 | 0xfc | -| MIO_PERIPH_INSEL_6 | 0x100 | -| MIO_PERIPH_INSEL_7 | 0x104 | -| MIO_PERIPH_INSEL_8 | 0x108 | -| MIO_PERIPH_INSEL_9 | 0x10c | -| MIO_PERIPH_INSEL_10 | 0x110 | -| MIO_PERIPH_INSEL_11 | 0x114 | -| MIO_PERIPH_INSEL_12 | 0x118 | -| MIO_PERIPH_INSEL_13 | 0x11c | -| MIO_PERIPH_INSEL_14 | 0x120 | -| MIO_PERIPH_INSEL_15 | 0x124 | -| MIO_PERIPH_INSEL_16 | 0x128 | -| MIO_PERIPH_INSEL_17 | 0x12c | -| MIO_PERIPH_INSEL_18 | 0x130 | -| MIO_PERIPH_INSEL_19 | 0x134 | -| MIO_PERIPH_INSEL_20 | 0x138 | -| MIO_PERIPH_INSEL_21 | 0x13c | -| MIO_PERIPH_INSEL_22 | 0x140 | -| MIO_PERIPH_INSEL_23 | 0x144 | -| MIO_PERIPH_INSEL_24 | 0x148 | -| MIO_PERIPH_INSEL_25 | 0x14c | -| MIO_PERIPH_INSEL_26 | 0x150 | -| MIO_PERIPH_INSEL_27 | 0x154 | -| MIO_PERIPH_INSEL_28 | 0x158 | -| MIO_PERIPH_INSEL_29 | 0x15c | -| MIO_PERIPH_INSEL_30 | 0x160 | -| MIO_PERIPH_INSEL_31 | 0x164 | -| MIO_PERIPH_INSEL_32 | 0x168 | -| MIO_PERIPH_INSEL_33 | 0x16c | -| MIO_PERIPH_INSEL_34 | 0x170 | -| MIO_PERIPH_INSEL_35 | 0x174 | -| MIO_PERIPH_INSEL_36 | 0x178 | -| MIO_PERIPH_INSEL_37 | 0x17c | -| MIO_PERIPH_INSEL_38 | 0x180 | -| MIO_PERIPH_INSEL_39 | 0x184 | -| MIO_PERIPH_INSEL_40 | 0x188 | -| MIO_PERIPH_INSEL_41 | 0x18c | -| MIO_PERIPH_INSEL_42 | 0x190 | -| MIO_PERIPH_INSEL_43 | 0x194 | -| MIO_PERIPH_INSEL_44 | 0x198 | -| MIO_PERIPH_INSEL_45 | 0x19c | -| MIO_PERIPH_INSEL_46 | 0x1a0 | -| MIO_PERIPH_INSEL_47 | 0x1a4 | -| MIO_PERIPH_INSEL_48 | 0x1a8 | -| MIO_PERIPH_INSEL_49 | 0x1ac | -| MIO_PERIPH_INSEL_50 | 0x1b0 | -| MIO_PERIPH_INSEL_51 | 0x1b4 | -| MIO_PERIPH_INSEL_52 | 0x1b8 | -| MIO_PERIPH_INSEL_53 | 0x1bc | -| MIO_PERIPH_INSEL_54 | 0x1c0 | -| MIO_PERIPH_INSEL_55 | 0x1c4 | -| MIO_PERIPH_INSEL_56 | 0x1c8 | +| MIO_PERIPH_INSEL_0 | 0xf0 | +| MIO_PERIPH_INSEL_1 | 0xf4 | +| MIO_PERIPH_INSEL_2 | 0xf8 | +| MIO_PERIPH_INSEL_3 | 0xfc | +| MIO_PERIPH_INSEL_4 | 0x100 | +| MIO_PERIPH_INSEL_5 | 0x104 | +| MIO_PERIPH_INSEL_6 | 0x108 | +| MIO_PERIPH_INSEL_7 | 0x10c | +| MIO_PERIPH_INSEL_8 | 0x110 | +| MIO_PERIPH_INSEL_9 | 0x114 | +| MIO_PERIPH_INSEL_10 | 0x118 | +| MIO_PERIPH_INSEL_11 | 0x11c | +| MIO_PERIPH_INSEL_12 | 0x120 | +| MIO_PERIPH_INSEL_13 | 0x124 | +| MIO_PERIPH_INSEL_14 | 0x128 | +| MIO_PERIPH_INSEL_15 | 0x12c | +| MIO_PERIPH_INSEL_16 | 0x130 | +| MIO_PERIPH_INSEL_17 | 0x134 | +| MIO_PERIPH_INSEL_18 | 0x138 | +| MIO_PERIPH_INSEL_19 | 0x13c | +| MIO_PERIPH_INSEL_20 | 0x140 | +| MIO_PERIPH_INSEL_21 | 0x144 | +| MIO_PERIPH_INSEL_22 | 0x148 | +| MIO_PERIPH_INSEL_23 | 0x14c | +| MIO_PERIPH_INSEL_24 | 0x150 | +| MIO_PERIPH_INSEL_25 | 0x154 | +| MIO_PERIPH_INSEL_26 | 0x158 | +| MIO_PERIPH_INSEL_27 | 0x15c | +| MIO_PERIPH_INSEL_28 | 0x160 | +| MIO_PERIPH_INSEL_29 | 0x164 | +| MIO_PERIPH_INSEL_30 | 0x168 | +| MIO_PERIPH_INSEL_31 | 0x16c | +| MIO_PERIPH_INSEL_32 | 0x170 | +| MIO_PERIPH_INSEL_33 | 0x174 | +| MIO_PERIPH_INSEL_34 | 0x178 | +| MIO_PERIPH_INSEL_35 | 0x17c | +| MIO_PERIPH_INSEL_36 | 0x180 | +| MIO_PERIPH_INSEL_37 | 0x184 | +| MIO_PERIPH_INSEL_38 | 0x188 | +| MIO_PERIPH_INSEL_39 | 0x18c | +| MIO_PERIPH_INSEL_40 | 0x190 | +| MIO_PERIPH_INSEL_41 | 0x194 | +| MIO_PERIPH_INSEL_42 | 0x198 | +| MIO_PERIPH_INSEL_43 | 0x19c | +| MIO_PERIPH_INSEL_44 | 0x1a0 | +| MIO_PERIPH_INSEL_45 | 0x1a4 | +| MIO_PERIPH_INSEL_46 | 0x1a8 | +| MIO_PERIPH_INSEL_47 | 0x1ac | +| MIO_PERIPH_INSEL_48 | 0x1b0 | +| MIO_PERIPH_INSEL_49 | 0x1b4 | +| MIO_PERIPH_INSEL_50 | 0x1b8 | +| MIO_PERIPH_INSEL_51 | 0x1bc | +| MIO_PERIPH_INSEL_52 | 0x1c0 | +| MIO_PERIPH_INSEL_53 | 0x1c4 | +| MIO_PERIPH_INSEL_54 | 0x1c8 | +| MIO_PERIPH_INSEL_55 | 0x1cc | +| MIO_PERIPH_INSEL_56 | 0x1d0 | +| MIO_PERIPH_INSEL_57 | 0x1d4 | +| MIO_PERIPH_INSEL_58 | 0x1d8 | ### Fields @@ -763,53 +771,53 @@ Register write enable for MIO output selects. | Name | Offset | |:---------------------|:---------| -| MIO_OUTSEL_REGWEN_0 | 0x1cc | -| MIO_OUTSEL_REGWEN_1 | 0x1d0 | -| MIO_OUTSEL_REGWEN_2 | 0x1d4 | -| MIO_OUTSEL_REGWEN_3 | 0x1d8 | -| MIO_OUTSEL_REGWEN_4 | 0x1dc | -| MIO_OUTSEL_REGWEN_5 | 0x1e0 | -| MIO_OUTSEL_REGWEN_6 | 0x1e4 | -| MIO_OUTSEL_REGWEN_7 | 0x1e8 | -| MIO_OUTSEL_REGWEN_8 | 0x1ec | -| MIO_OUTSEL_REGWEN_9 | 0x1f0 | -| MIO_OUTSEL_REGWEN_10 | 0x1f4 | -| MIO_OUTSEL_REGWEN_11 | 0x1f8 | -| MIO_OUTSEL_REGWEN_12 | 0x1fc | -| MIO_OUTSEL_REGWEN_13 | 0x200 | -| MIO_OUTSEL_REGWEN_14 | 0x204 | -| MIO_OUTSEL_REGWEN_15 | 0x208 | -| MIO_OUTSEL_REGWEN_16 | 0x20c | -| MIO_OUTSEL_REGWEN_17 | 0x210 | -| MIO_OUTSEL_REGWEN_18 | 0x214 | -| MIO_OUTSEL_REGWEN_19 | 0x218 | -| MIO_OUTSEL_REGWEN_20 | 0x21c | -| MIO_OUTSEL_REGWEN_21 | 0x220 | -| MIO_OUTSEL_REGWEN_22 | 0x224 | -| MIO_OUTSEL_REGWEN_23 | 0x228 | -| MIO_OUTSEL_REGWEN_24 | 0x22c | -| MIO_OUTSEL_REGWEN_25 | 0x230 | -| MIO_OUTSEL_REGWEN_26 | 0x234 | -| MIO_OUTSEL_REGWEN_27 | 0x238 | -| MIO_OUTSEL_REGWEN_28 | 0x23c | -| MIO_OUTSEL_REGWEN_29 | 0x240 | -| MIO_OUTSEL_REGWEN_30 | 0x244 | -| MIO_OUTSEL_REGWEN_31 | 0x248 | -| MIO_OUTSEL_REGWEN_32 | 0x24c | -| MIO_OUTSEL_REGWEN_33 | 0x250 | -| MIO_OUTSEL_REGWEN_34 | 0x254 | -| MIO_OUTSEL_REGWEN_35 | 0x258 | -| MIO_OUTSEL_REGWEN_36 | 0x25c | -| MIO_OUTSEL_REGWEN_37 | 0x260 | -| MIO_OUTSEL_REGWEN_38 | 0x264 | -| MIO_OUTSEL_REGWEN_39 | 0x268 | -| MIO_OUTSEL_REGWEN_40 | 0x26c | -| MIO_OUTSEL_REGWEN_41 | 0x270 | -| MIO_OUTSEL_REGWEN_42 | 0x274 | -| MIO_OUTSEL_REGWEN_43 | 0x278 | -| MIO_OUTSEL_REGWEN_44 | 0x27c | -| MIO_OUTSEL_REGWEN_45 | 0x280 | -| MIO_OUTSEL_REGWEN_46 | 0x284 | +| MIO_OUTSEL_REGWEN_0 | 0x1dc | +| MIO_OUTSEL_REGWEN_1 | 0x1e0 | +| MIO_OUTSEL_REGWEN_2 | 0x1e4 | +| MIO_OUTSEL_REGWEN_3 | 0x1e8 | +| MIO_OUTSEL_REGWEN_4 | 0x1ec | +| MIO_OUTSEL_REGWEN_5 | 0x1f0 | +| MIO_OUTSEL_REGWEN_6 | 0x1f4 | +| MIO_OUTSEL_REGWEN_7 | 0x1f8 | +| MIO_OUTSEL_REGWEN_8 | 0x1fc | +| MIO_OUTSEL_REGWEN_9 | 0x200 | +| MIO_OUTSEL_REGWEN_10 | 0x204 | +| MIO_OUTSEL_REGWEN_11 | 0x208 | +| MIO_OUTSEL_REGWEN_12 | 0x20c | +| MIO_OUTSEL_REGWEN_13 | 0x210 | +| MIO_OUTSEL_REGWEN_14 | 0x214 | +| MIO_OUTSEL_REGWEN_15 | 0x218 | +| MIO_OUTSEL_REGWEN_16 | 0x21c | +| MIO_OUTSEL_REGWEN_17 | 0x220 | +| MIO_OUTSEL_REGWEN_18 | 0x224 | +| MIO_OUTSEL_REGWEN_19 | 0x228 | +| MIO_OUTSEL_REGWEN_20 | 0x22c | +| MIO_OUTSEL_REGWEN_21 | 0x230 | +| MIO_OUTSEL_REGWEN_22 | 0x234 | +| MIO_OUTSEL_REGWEN_23 | 0x238 | +| MIO_OUTSEL_REGWEN_24 | 0x23c | +| MIO_OUTSEL_REGWEN_25 | 0x240 | +| MIO_OUTSEL_REGWEN_26 | 0x244 | +| MIO_OUTSEL_REGWEN_27 | 0x248 | +| MIO_OUTSEL_REGWEN_28 | 0x24c | +| MIO_OUTSEL_REGWEN_29 | 0x250 | +| MIO_OUTSEL_REGWEN_30 | 0x254 | +| MIO_OUTSEL_REGWEN_31 | 0x258 | +| MIO_OUTSEL_REGWEN_32 | 0x25c | +| MIO_OUTSEL_REGWEN_33 | 0x260 | +| MIO_OUTSEL_REGWEN_34 | 0x264 | +| MIO_OUTSEL_REGWEN_35 | 0x268 | +| MIO_OUTSEL_REGWEN_36 | 0x26c | +| MIO_OUTSEL_REGWEN_37 | 0x270 | +| MIO_OUTSEL_REGWEN_38 | 0x274 | +| MIO_OUTSEL_REGWEN_39 | 0x278 | +| MIO_OUTSEL_REGWEN_40 | 0x27c | +| MIO_OUTSEL_REGWEN_41 | 0x280 | +| MIO_OUTSEL_REGWEN_42 | 0x284 | +| MIO_OUTSEL_REGWEN_43 | 0x288 | +| MIO_OUTSEL_REGWEN_44 | 0x28c | +| MIO_OUTSEL_REGWEN_45 | 0x290 | +| MIO_OUTSEL_REGWEN_46 | 0x294 | ### Fields @@ -832,53 +840,53 @@ For each muxable pad, this selects the peripheral output. | Name | Offset | |:--------------|:---------| -| MIO_OUTSEL_0 | 0x288 | -| MIO_OUTSEL_1 | 0x28c | -| MIO_OUTSEL_2 | 0x290 | -| MIO_OUTSEL_3 | 0x294 | -| MIO_OUTSEL_4 | 0x298 | -| MIO_OUTSEL_5 | 0x29c | -| MIO_OUTSEL_6 | 0x2a0 | -| MIO_OUTSEL_7 | 0x2a4 | -| MIO_OUTSEL_8 | 0x2a8 | -| MIO_OUTSEL_9 | 0x2ac | -| MIO_OUTSEL_10 | 0x2b0 | -| MIO_OUTSEL_11 | 0x2b4 | -| MIO_OUTSEL_12 | 0x2b8 | -| MIO_OUTSEL_13 | 0x2bc | -| MIO_OUTSEL_14 | 0x2c0 | -| MIO_OUTSEL_15 | 0x2c4 | -| MIO_OUTSEL_16 | 0x2c8 | -| MIO_OUTSEL_17 | 0x2cc | -| MIO_OUTSEL_18 | 0x2d0 | -| MIO_OUTSEL_19 | 0x2d4 | -| MIO_OUTSEL_20 | 0x2d8 | -| MIO_OUTSEL_21 | 0x2dc | -| MIO_OUTSEL_22 | 0x2e0 | -| MIO_OUTSEL_23 | 0x2e4 | -| MIO_OUTSEL_24 | 0x2e8 | -| MIO_OUTSEL_25 | 0x2ec | -| MIO_OUTSEL_26 | 0x2f0 | -| MIO_OUTSEL_27 | 0x2f4 | -| MIO_OUTSEL_28 | 0x2f8 | -| MIO_OUTSEL_29 | 0x2fc | -| MIO_OUTSEL_30 | 0x300 | -| MIO_OUTSEL_31 | 0x304 | -| MIO_OUTSEL_32 | 0x308 | -| MIO_OUTSEL_33 | 0x30c | -| MIO_OUTSEL_34 | 0x310 | -| MIO_OUTSEL_35 | 0x314 | -| MIO_OUTSEL_36 | 0x318 | -| MIO_OUTSEL_37 | 0x31c | -| MIO_OUTSEL_38 | 0x320 | -| MIO_OUTSEL_39 | 0x324 | -| MIO_OUTSEL_40 | 0x328 | -| MIO_OUTSEL_41 | 0x32c | -| MIO_OUTSEL_42 | 0x330 | -| MIO_OUTSEL_43 | 0x334 | -| MIO_OUTSEL_44 | 0x338 | -| MIO_OUTSEL_45 | 0x33c | -| MIO_OUTSEL_46 | 0x340 | +| MIO_OUTSEL_0 | 0x298 | +| MIO_OUTSEL_1 | 0x29c | +| MIO_OUTSEL_2 | 0x2a0 | +| MIO_OUTSEL_3 | 0x2a4 | +| MIO_OUTSEL_4 | 0x2a8 | +| MIO_OUTSEL_5 | 0x2ac | +| MIO_OUTSEL_6 | 0x2b0 | +| MIO_OUTSEL_7 | 0x2b4 | +| MIO_OUTSEL_8 | 0x2b8 | +| MIO_OUTSEL_9 | 0x2bc | +| MIO_OUTSEL_10 | 0x2c0 | +| MIO_OUTSEL_11 | 0x2c4 | +| MIO_OUTSEL_12 | 0x2c8 | +| MIO_OUTSEL_13 | 0x2cc | +| MIO_OUTSEL_14 | 0x2d0 | +| MIO_OUTSEL_15 | 0x2d4 | +| MIO_OUTSEL_16 | 0x2d8 | +| MIO_OUTSEL_17 | 0x2dc | +| MIO_OUTSEL_18 | 0x2e0 | +| MIO_OUTSEL_19 | 0x2e4 | +| MIO_OUTSEL_20 | 0x2e8 | +| MIO_OUTSEL_21 | 0x2ec | +| MIO_OUTSEL_22 | 0x2f0 | +| MIO_OUTSEL_23 | 0x2f4 | +| MIO_OUTSEL_24 | 0x2f8 | +| MIO_OUTSEL_25 | 0x2fc | +| MIO_OUTSEL_26 | 0x300 | +| MIO_OUTSEL_27 | 0x304 | +| MIO_OUTSEL_28 | 0x308 | +| MIO_OUTSEL_29 | 0x30c | +| MIO_OUTSEL_30 | 0x310 | +| MIO_OUTSEL_31 | 0x314 | +| MIO_OUTSEL_32 | 0x318 | +| MIO_OUTSEL_33 | 0x31c | +| MIO_OUTSEL_34 | 0x320 | +| MIO_OUTSEL_35 | 0x324 | +| MIO_OUTSEL_36 | 0x328 | +| MIO_OUTSEL_37 | 0x32c | +| MIO_OUTSEL_38 | 0x330 | +| MIO_OUTSEL_39 | 0x334 | +| MIO_OUTSEL_40 | 0x338 | +| MIO_OUTSEL_41 | 0x33c | +| MIO_OUTSEL_42 | 0x340 | +| MIO_OUTSEL_43 | 0x344 | +| MIO_OUTSEL_44 | 0x348 | +| MIO_OUTSEL_45 | 0x34c | +| MIO_OUTSEL_46 | 0x350 | ### Fields @@ -901,53 +909,53 @@ Register write enable for MIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| MIO_PAD_ATTR_REGWEN_0 | 0x344 | -| MIO_PAD_ATTR_REGWEN_1 | 0x348 | -| MIO_PAD_ATTR_REGWEN_2 | 0x34c | -| MIO_PAD_ATTR_REGWEN_3 | 0x350 | -| MIO_PAD_ATTR_REGWEN_4 | 0x354 | -| MIO_PAD_ATTR_REGWEN_5 | 0x358 | -| MIO_PAD_ATTR_REGWEN_6 | 0x35c | -| MIO_PAD_ATTR_REGWEN_7 | 0x360 | -| MIO_PAD_ATTR_REGWEN_8 | 0x364 | -| MIO_PAD_ATTR_REGWEN_9 | 0x368 | -| MIO_PAD_ATTR_REGWEN_10 | 0x36c | -| MIO_PAD_ATTR_REGWEN_11 | 0x370 | -| MIO_PAD_ATTR_REGWEN_12 | 0x374 | -| MIO_PAD_ATTR_REGWEN_13 | 0x378 | -| MIO_PAD_ATTR_REGWEN_14 | 0x37c | -| MIO_PAD_ATTR_REGWEN_15 | 0x380 | -| MIO_PAD_ATTR_REGWEN_16 | 0x384 | -| MIO_PAD_ATTR_REGWEN_17 | 0x388 | -| MIO_PAD_ATTR_REGWEN_18 | 0x38c | -| MIO_PAD_ATTR_REGWEN_19 | 0x390 | -| MIO_PAD_ATTR_REGWEN_20 | 0x394 | -| MIO_PAD_ATTR_REGWEN_21 | 0x398 | -| MIO_PAD_ATTR_REGWEN_22 | 0x39c | -| MIO_PAD_ATTR_REGWEN_23 | 0x3a0 | -| MIO_PAD_ATTR_REGWEN_24 | 0x3a4 | -| MIO_PAD_ATTR_REGWEN_25 | 0x3a8 | -| MIO_PAD_ATTR_REGWEN_26 | 0x3ac | -| MIO_PAD_ATTR_REGWEN_27 | 0x3b0 | -| MIO_PAD_ATTR_REGWEN_28 | 0x3b4 | -| MIO_PAD_ATTR_REGWEN_29 | 0x3b8 | -| MIO_PAD_ATTR_REGWEN_30 | 0x3bc | -| MIO_PAD_ATTR_REGWEN_31 | 0x3c0 | -| MIO_PAD_ATTR_REGWEN_32 | 0x3c4 | -| MIO_PAD_ATTR_REGWEN_33 | 0x3c8 | -| MIO_PAD_ATTR_REGWEN_34 | 0x3cc | -| MIO_PAD_ATTR_REGWEN_35 | 0x3d0 | -| MIO_PAD_ATTR_REGWEN_36 | 0x3d4 | -| MIO_PAD_ATTR_REGWEN_37 | 0x3d8 | -| MIO_PAD_ATTR_REGWEN_38 | 0x3dc | -| MIO_PAD_ATTR_REGWEN_39 | 0x3e0 | -| MIO_PAD_ATTR_REGWEN_40 | 0x3e4 | -| MIO_PAD_ATTR_REGWEN_41 | 0x3e8 | -| MIO_PAD_ATTR_REGWEN_42 | 0x3ec | -| MIO_PAD_ATTR_REGWEN_43 | 0x3f0 | -| MIO_PAD_ATTR_REGWEN_44 | 0x3f4 | -| MIO_PAD_ATTR_REGWEN_45 | 0x3f8 | -| MIO_PAD_ATTR_REGWEN_46 | 0x3fc | +| MIO_PAD_ATTR_REGWEN_0 | 0x354 | +| MIO_PAD_ATTR_REGWEN_1 | 0x358 | +| MIO_PAD_ATTR_REGWEN_2 | 0x35c | +| MIO_PAD_ATTR_REGWEN_3 | 0x360 | +| MIO_PAD_ATTR_REGWEN_4 | 0x364 | +| MIO_PAD_ATTR_REGWEN_5 | 0x368 | +| MIO_PAD_ATTR_REGWEN_6 | 0x36c | +| MIO_PAD_ATTR_REGWEN_7 | 0x370 | +| MIO_PAD_ATTR_REGWEN_8 | 0x374 | +| MIO_PAD_ATTR_REGWEN_9 | 0x378 | +| MIO_PAD_ATTR_REGWEN_10 | 0x37c | +| MIO_PAD_ATTR_REGWEN_11 | 0x380 | +| MIO_PAD_ATTR_REGWEN_12 | 0x384 | +| MIO_PAD_ATTR_REGWEN_13 | 0x388 | +| MIO_PAD_ATTR_REGWEN_14 | 0x38c | +| MIO_PAD_ATTR_REGWEN_15 | 0x390 | +| MIO_PAD_ATTR_REGWEN_16 | 0x394 | +| MIO_PAD_ATTR_REGWEN_17 | 0x398 | +| MIO_PAD_ATTR_REGWEN_18 | 0x39c | +| MIO_PAD_ATTR_REGWEN_19 | 0x3a0 | +| MIO_PAD_ATTR_REGWEN_20 | 0x3a4 | +| MIO_PAD_ATTR_REGWEN_21 | 0x3a8 | +| MIO_PAD_ATTR_REGWEN_22 | 0x3ac | +| MIO_PAD_ATTR_REGWEN_23 | 0x3b0 | +| MIO_PAD_ATTR_REGWEN_24 | 0x3b4 | +| MIO_PAD_ATTR_REGWEN_25 | 0x3b8 | +| MIO_PAD_ATTR_REGWEN_26 | 0x3bc | +| MIO_PAD_ATTR_REGWEN_27 | 0x3c0 | +| MIO_PAD_ATTR_REGWEN_28 | 0x3c4 | +| MIO_PAD_ATTR_REGWEN_29 | 0x3c8 | +| MIO_PAD_ATTR_REGWEN_30 | 0x3cc | +| MIO_PAD_ATTR_REGWEN_31 | 0x3d0 | +| MIO_PAD_ATTR_REGWEN_32 | 0x3d4 | +| MIO_PAD_ATTR_REGWEN_33 | 0x3d8 | +| MIO_PAD_ATTR_REGWEN_34 | 0x3dc | +| MIO_PAD_ATTR_REGWEN_35 | 0x3e0 | +| MIO_PAD_ATTR_REGWEN_36 | 0x3e4 | +| MIO_PAD_ATTR_REGWEN_37 | 0x3e8 | +| MIO_PAD_ATTR_REGWEN_38 | 0x3ec | +| MIO_PAD_ATTR_REGWEN_39 | 0x3f0 | +| MIO_PAD_ATTR_REGWEN_40 | 0x3f4 | +| MIO_PAD_ATTR_REGWEN_41 | 0x3f8 | +| MIO_PAD_ATTR_REGWEN_42 | 0x3fc | +| MIO_PAD_ATTR_REGWEN_43 | 0x400 | +| MIO_PAD_ATTR_REGWEN_44 | 0x404 | +| MIO_PAD_ATTR_REGWEN_45 | 0x408 | +| MIO_PAD_ATTR_REGWEN_46 | 0x40c | ### Fields @@ -972,53 +980,53 @@ all attributes. | Name | Offset | |:----------------|:---------| -| MIO_PAD_ATTR_0 | 0x400 | -| MIO_PAD_ATTR_1 | 0x404 | -| MIO_PAD_ATTR_2 | 0x408 | -| MIO_PAD_ATTR_3 | 0x40c | -| MIO_PAD_ATTR_4 | 0x410 | -| MIO_PAD_ATTR_5 | 0x414 | -| MIO_PAD_ATTR_6 | 0x418 | -| MIO_PAD_ATTR_7 | 0x41c | -| MIO_PAD_ATTR_8 | 0x420 | -| MIO_PAD_ATTR_9 | 0x424 | -| MIO_PAD_ATTR_10 | 0x428 | -| MIO_PAD_ATTR_11 | 0x42c | -| MIO_PAD_ATTR_12 | 0x430 | -| MIO_PAD_ATTR_13 | 0x434 | -| MIO_PAD_ATTR_14 | 0x438 | -| MIO_PAD_ATTR_15 | 0x43c | -| MIO_PAD_ATTR_16 | 0x440 | -| MIO_PAD_ATTR_17 | 0x444 | -| MIO_PAD_ATTR_18 | 0x448 | -| MIO_PAD_ATTR_19 | 0x44c | -| MIO_PAD_ATTR_20 | 0x450 | -| MIO_PAD_ATTR_21 | 0x454 | -| MIO_PAD_ATTR_22 | 0x458 | -| MIO_PAD_ATTR_23 | 0x45c | -| MIO_PAD_ATTR_24 | 0x460 | -| MIO_PAD_ATTR_25 | 0x464 | -| MIO_PAD_ATTR_26 | 0x468 | -| MIO_PAD_ATTR_27 | 0x46c | -| MIO_PAD_ATTR_28 | 0x470 | -| MIO_PAD_ATTR_29 | 0x474 | -| MIO_PAD_ATTR_30 | 0x478 | -| MIO_PAD_ATTR_31 | 0x47c | -| MIO_PAD_ATTR_32 | 0x480 | -| MIO_PAD_ATTR_33 | 0x484 | -| MIO_PAD_ATTR_34 | 0x488 | -| MIO_PAD_ATTR_35 | 0x48c | -| MIO_PAD_ATTR_36 | 0x490 | -| MIO_PAD_ATTR_37 | 0x494 | -| MIO_PAD_ATTR_38 | 0x498 | -| MIO_PAD_ATTR_39 | 0x49c | -| MIO_PAD_ATTR_40 | 0x4a0 | -| MIO_PAD_ATTR_41 | 0x4a4 | -| MIO_PAD_ATTR_42 | 0x4a8 | -| MIO_PAD_ATTR_43 | 0x4ac | -| MIO_PAD_ATTR_44 | 0x4b0 | -| MIO_PAD_ATTR_45 | 0x4b4 | -| MIO_PAD_ATTR_46 | 0x4b8 | +| MIO_PAD_ATTR_0 | 0x410 | +| MIO_PAD_ATTR_1 | 0x414 | +| MIO_PAD_ATTR_2 | 0x418 | +| MIO_PAD_ATTR_3 | 0x41c | +| MIO_PAD_ATTR_4 | 0x420 | +| MIO_PAD_ATTR_5 | 0x424 | +| MIO_PAD_ATTR_6 | 0x428 | +| MIO_PAD_ATTR_7 | 0x42c | +| MIO_PAD_ATTR_8 | 0x430 | +| MIO_PAD_ATTR_9 | 0x434 | +| MIO_PAD_ATTR_10 | 0x438 | +| MIO_PAD_ATTR_11 | 0x43c | +| MIO_PAD_ATTR_12 | 0x440 | +| MIO_PAD_ATTR_13 | 0x444 | +| MIO_PAD_ATTR_14 | 0x448 | +| MIO_PAD_ATTR_15 | 0x44c | +| MIO_PAD_ATTR_16 | 0x450 | +| MIO_PAD_ATTR_17 | 0x454 | +| MIO_PAD_ATTR_18 | 0x458 | +| MIO_PAD_ATTR_19 | 0x45c | +| MIO_PAD_ATTR_20 | 0x460 | +| MIO_PAD_ATTR_21 | 0x464 | +| MIO_PAD_ATTR_22 | 0x468 | +| MIO_PAD_ATTR_23 | 0x46c | +| MIO_PAD_ATTR_24 | 0x470 | +| MIO_PAD_ATTR_25 | 0x474 | +| MIO_PAD_ATTR_26 | 0x478 | +| MIO_PAD_ATTR_27 | 0x47c | +| MIO_PAD_ATTR_28 | 0x480 | +| MIO_PAD_ATTR_29 | 0x484 | +| MIO_PAD_ATTR_30 | 0x488 | +| MIO_PAD_ATTR_31 | 0x48c | +| MIO_PAD_ATTR_32 | 0x490 | +| MIO_PAD_ATTR_33 | 0x494 | +| MIO_PAD_ATTR_34 | 0x498 | +| MIO_PAD_ATTR_35 | 0x49c | +| MIO_PAD_ATTR_36 | 0x4a0 | +| MIO_PAD_ATTR_37 | 0x4a4 | +| MIO_PAD_ATTR_38 | 0x4a8 | +| MIO_PAD_ATTR_39 | 0x4ac | +| MIO_PAD_ATTR_40 | 0x4b0 | +| MIO_PAD_ATTR_41 | 0x4b4 | +| MIO_PAD_ATTR_42 | 0x4b8 | +| MIO_PAD_ATTR_43 | 0x4bc | +| MIO_PAD_ATTR_44 | 0x4c0 | +| MIO_PAD_ATTR_45 | 0x4c4 | +| MIO_PAD_ATTR_46 | 0x4c8 | ### Fields @@ -1084,22 +1092,22 @@ Register write enable for DIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| DIO_PAD_ATTR_REGWEN_0 | 0x4bc | -| DIO_PAD_ATTR_REGWEN_1 | 0x4c0 | -| DIO_PAD_ATTR_REGWEN_2 | 0x4c4 | -| DIO_PAD_ATTR_REGWEN_3 | 0x4c8 | -| DIO_PAD_ATTR_REGWEN_4 | 0x4cc | -| DIO_PAD_ATTR_REGWEN_5 | 0x4d0 | -| DIO_PAD_ATTR_REGWEN_6 | 0x4d4 | -| DIO_PAD_ATTR_REGWEN_7 | 0x4d8 | -| DIO_PAD_ATTR_REGWEN_8 | 0x4dc | -| DIO_PAD_ATTR_REGWEN_9 | 0x4e0 | -| DIO_PAD_ATTR_REGWEN_10 | 0x4e4 | -| DIO_PAD_ATTR_REGWEN_11 | 0x4e8 | -| DIO_PAD_ATTR_REGWEN_12 | 0x4ec | -| DIO_PAD_ATTR_REGWEN_13 | 0x4f0 | -| DIO_PAD_ATTR_REGWEN_14 | 0x4f4 | -| DIO_PAD_ATTR_REGWEN_15 | 0x4f8 | +| DIO_PAD_ATTR_REGWEN_0 | 0x4cc | +| DIO_PAD_ATTR_REGWEN_1 | 0x4d0 | +| DIO_PAD_ATTR_REGWEN_2 | 0x4d4 | +| DIO_PAD_ATTR_REGWEN_3 | 0x4d8 | +| DIO_PAD_ATTR_REGWEN_4 | 0x4dc | +| DIO_PAD_ATTR_REGWEN_5 | 0x4e0 | +| DIO_PAD_ATTR_REGWEN_6 | 0x4e4 | +| DIO_PAD_ATTR_REGWEN_7 | 0x4e8 | +| DIO_PAD_ATTR_REGWEN_8 | 0x4ec | +| DIO_PAD_ATTR_REGWEN_9 | 0x4f0 | +| DIO_PAD_ATTR_REGWEN_10 | 0x4f4 | +| DIO_PAD_ATTR_REGWEN_11 | 0x4f8 | +| DIO_PAD_ATTR_REGWEN_12 | 0x4fc | +| DIO_PAD_ATTR_REGWEN_13 | 0x500 | +| DIO_PAD_ATTR_REGWEN_14 | 0x504 | +| DIO_PAD_ATTR_REGWEN_15 | 0x508 | ### Fields @@ -1124,22 +1132,22 @@ all attributes. | Name | Offset | |:----------------|:---------| -| DIO_PAD_ATTR_0 | 0x4fc | -| DIO_PAD_ATTR_1 | 0x500 | -| DIO_PAD_ATTR_2 | 0x504 | -| DIO_PAD_ATTR_3 | 0x508 | -| DIO_PAD_ATTR_4 | 0x50c | -| DIO_PAD_ATTR_5 | 0x510 | -| DIO_PAD_ATTR_6 | 0x514 | -| DIO_PAD_ATTR_7 | 0x518 | -| DIO_PAD_ATTR_8 | 0x51c | -| DIO_PAD_ATTR_9 | 0x520 | -| DIO_PAD_ATTR_10 | 0x524 | -| DIO_PAD_ATTR_11 | 0x528 | -| DIO_PAD_ATTR_12 | 0x52c | -| DIO_PAD_ATTR_13 | 0x530 | -| DIO_PAD_ATTR_14 | 0x534 | -| DIO_PAD_ATTR_15 | 0x538 | +| DIO_PAD_ATTR_0 | 0x50c | +| DIO_PAD_ATTR_1 | 0x510 | +| DIO_PAD_ATTR_2 | 0x514 | +| DIO_PAD_ATTR_3 | 0x518 | +| DIO_PAD_ATTR_4 | 0x51c | +| DIO_PAD_ATTR_5 | 0x520 | +| DIO_PAD_ATTR_6 | 0x524 | +| DIO_PAD_ATTR_7 | 0x528 | +| DIO_PAD_ATTR_8 | 0x52c | +| DIO_PAD_ATTR_9 | 0x530 | +| DIO_PAD_ATTR_10 | 0x534 | +| DIO_PAD_ATTR_11 | 0x538 | +| DIO_PAD_ATTR_12 | 0x53c | +| DIO_PAD_ATTR_13 | 0x540 | +| DIO_PAD_ATTR_14 | 0x544 | +| DIO_PAD_ATTR_15 | 0x548 | ### Fields @@ -1198,7 +1206,7 @@ Invert input and output levels. ## MIO_PAD_SLEEP_STATUS_0 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x53c` +- Offset: `0x54c` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -1245,7 +1253,7 @@ Register indicating whether the corresponding pad is in sleep mode. ## MIO_PAD_SLEEP_STATUS_1 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x540` +- Offset: `0x550` - Reset default: `0x0` - Reset mask: `0x7fff` @@ -1283,53 +1291,53 @@ Register write enable for MIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| MIO_PAD_SLEEP_REGWEN_0 | 0x544 | -| MIO_PAD_SLEEP_REGWEN_1 | 0x548 | -| MIO_PAD_SLEEP_REGWEN_2 | 0x54c | -| MIO_PAD_SLEEP_REGWEN_3 | 0x550 | -| MIO_PAD_SLEEP_REGWEN_4 | 0x554 | -| MIO_PAD_SLEEP_REGWEN_5 | 0x558 | -| MIO_PAD_SLEEP_REGWEN_6 | 0x55c | -| MIO_PAD_SLEEP_REGWEN_7 | 0x560 | -| MIO_PAD_SLEEP_REGWEN_8 | 0x564 | -| MIO_PAD_SLEEP_REGWEN_9 | 0x568 | -| MIO_PAD_SLEEP_REGWEN_10 | 0x56c | -| MIO_PAD_SLEEP_REGWEN_11 | 0x570 | -| MIO_PAD_SLEEP_REGWEN_12 | 0x574 | -| MIO_PAD_SLEEP_REGWEN_13 | 0x578 | -| MIO_PAD_SLEEP_REGWEN_14 | 0x57c | -| MIO_PAD_SLEEP_REGWEN_15 | 0x580 | -| MIO_PAD_SLEEP_REGWEN_16 | 0x584 | -| MIO_PAD_SLEEP_REGWEN_17 | 0x588 | -| MIO_PAD_SLEEP_REGWEN_18 | 0x58c | -| MIO_PAD_SLEEP_REGWEN_19 | 0x590 | -| MIO_PAD_SLEEP_REGWEN_20 | 0x594 | -| MIO_PAD_SLEEP_REGWEN_21 | 0x598 | -| MIO_PAD_SLEEP_REGWEN_22 | 0x59c | -| MIO_PAD_SLEEP_REGWEN_23 | 0x5a0 | -| MIO_PAD_SLEEP_REGWEN_24 | 0x5a4 | -| MIO_PAD_SLEEP_REGWEN_25 | 0x5a8 | -| MIO_PAD_SLEEP_REGWEN_26 | 0x5ac | -| MIO_PAD_SLEEP_REGWEN_27 | 0x5b0 | -| MIO_PAD_SLEEP_REGWEN_28 | 0x5b4 | -| MIO_PAD_SLEEP_REGWEN_29 | 0x5b8 | -| MIO_PAD_SLEEP_REGWEN_30 | 0x5bc | -| MIO_PAD_SLEEP_REGWEN_31 | 0x5c0 | -| MIO_PAD_SLEEP_REGWEN_32 | 0x5c4 | -| MIO_PAD_SLEEP_REGWEN_33 | 0x5c8 | -| MIO_PAD_SLEEP_REGWEN_34 | 0x5cc | -| MIO_PAD_SLEEP_REGWEN_35 | 0x5d0 | -| MIO_PAD_SLEEP_REGWEN_36 | 0x5d4 | -| MIO_PAD_SLEEP_REGWEN_37 | 0x5d8 | -| MIO_PAD_SLEEP_REGWEN_38 | 0x5dc | -| MIO_PAD_SLEEP_REGWEN_39 | 0x5e0 | -| MIO_PAD_SLEEP_REGWEN_40 | 0x5e4 | -| MIO_PAD_SLEEP_REGWEN_41 | 0x5e8 | -| MIO_PAD_SLEEP_REGWEN_42 | 0x5ec | -| MIO_PAD_SLEEP_REGWEN_43 | 0x5f0 | -| MIO_PAD_SLEEP_REGWEN_44 | 0x5f4 | -| MIO_PAD_SLEEP_REGWEN_45 | 0x5f8 | -| MIO_PAD_SLEEP_REGWEN_46 | 0x5fc | +| MIO_PAD_SLEEP_REGWEN_0 | 0x554 | +| MIO_PAD_SLEEP_REGWEN_1 | 0x558 | +| MIO_PAD_SLEEP_REGWEN_2 | 0x55c | +| MIO_PAD_SLEEP_REGWEN_3 | 0x560 | +| MIO_PAD_SLEEP_REGWEN_4 | 0x564 | +| MIO_PAD_SLEEP_REGWEN_5 | 0x568 | +| MIO_PAD_SLEEP_REGWEN_6 | 0x56c | +| MIO_PAD_SLEEP_REGWEN_7 | 0x570 | +| MIO_PAD_SLEEP_REGWEN_8 | 0x574 | +| MIO_PAD_SLEEP_REGWEN_9 | 0x578 | +| MIO_PAD_SLEEP_REGWEN_10 | 0x57c | +| MIO_PAD_SLEEP_REGWEN_11 | 0x580 | +| MIO_PAD_SLEEP_REGWEN_12 | 0x584 | +| MIO_PAD_SLEEP_REGWEN_13 | 0x588 | +| MIO_PAD_SLEEP_REGWEN_14 | 0x58c | +| MIO_PAD_SLEEP_REGWEN_15 | 0x590 | +| MIO_PAD_SLEEP_REGWEN_16 | 0x594 | +| MIO_PAD_SLEEP_REGWEN_17 | 0x598 | +| MIO_PAD_SLEEP_REGWEN_18 | 0x59c | +| MIO_PAD_SLEEP_REGWEN_19 | 0x5a0 | +| MIO_PAD_SLEEP_REGWEN_20 | 0x5a4 | +| MIO_PAD_SLEEP_REGWEN_21 | 0x5a8 | +| MIO_PAD_SLEEP_REGWEN_22 | 0x5ac | +| MIO_PAD_SLEEP_REGWEN_23 | 0x5b0 | +| MIO_PAD_SLEEP_REGWEN_24 | 0x5b4 | +| MIO_PAD_SLEEP_REGWEN_25 | 0x5b8 | +| MIO_PAD_SLEEP_REGWEN_26 | 0x5bc | +| MIO_PAD_SLEEP_REGWEN_27 | 0x5c0 | +| MIO_PAD_SLEEP_REGWEN_28 | 0x5c4 | +| MIO_PAD_SLEEP_REGWEN_29 | 0x5c8 | +| MIO_PAD_SLEEP_REGWEN_30 | 0x5cc | +| MIO_PAD_SLEEP_REGWEN_31 | 0x5d0 | +| MIO_PAD_SLEEP_REGWEN_32 | 0x5d4 | +| MIO_PAD_SLEEP_REGWEN_33 | 0x5d8 | +| MIO_PAD_SLEEP_REGWEN_34 | 0x5dc | +| MIO_PAD_SLEEP_REGWEN_35 | 0x5e0 | +| MIO_PAD_SLEEP_REGWEN_36 | 0x5e4 | +| MIO_PAD_SLEEP_REGWEN_37 | 0x5e8 | +| MIO_PAD_SLEEP_REGWEN_38 | 0x5ec | +| MIO_PAD_SLEEP_REGWEN_39 | 0x5f0 | +| MIO_PAD_SLEEP_REGWEN_40 | 0x5f4 | +| MIO_PAD_SLEEP_REGWEN_41 | 0x5f8 | +| MIO_PAD_SLEEP_REGWEN_42 | 0x5fc | +| MIO_PAD_SLEEP_REGWEN_43 | 0x600 | +| MIO_PAD_SLEEP_REGWEN_44 | 0x604 | +| MIO_PAD_SLEEP_REGWEN_45 | 0x608 | +| MIO_PAD_SLEEP_REGWEN_46 | 0x60c | ### Fields @@ -1352,53 +1360,53 @@ Enables the sleep mode of the corresponding muxed pad. | Name | Offset | |:--------------------|:---------| -| MIO_PAD_SLEEP_EN_0 | 0x600 | -| MIO_PAD_SLEEP_EN_1 | 0x604 | -| MIO_PAD_SLEEP_EN_2 | 0x608 | -| MIO_PAD_SLEEP_EN_3 | 0x60c | -| MIO_PAD_SLEEP_EN_4 | 0x610 | -| MIO_PAD_SLEEP_EN_5 | 0x614 | -| MIO_PAD_SLEEP_EN_6 | 0x618 | -| MIO_PAD_SLEEP_EN_7 | 0x61c | -| MIO_PAD_SLEEP_EN_8 | 0x620 | -| MIO_PAD_SLEEP_EN_9 | 0x624 | -| MIO_PAD_SLEEP_EN_10 | 0x628 | -| MIO_PAD_SLEEP_EN_11 | 0x62c | -| MIO_PAD_SLEEP_EN_12 | 0x630 | -| MIO_PAD_SLEEP_EN_13 | 0x634 | -| MIO_PAD_SLEEP_EN_14 | 0x638 | -| MIO_PAD_SLEEP_EN_15 | 0x63c | -| MIO_PAD_SLEEP_EN_16 | 0x640 | -| MIO_PAD_SLEEP_EN_17 | 0x644 | -| MIO_PAD_SLEEP_EN_18 | 0x648 | -| MIO_PAD_SLEEP_EN_19 | 0x64c | -| MIO_PAD_SLEEP_EN_20 | 0x650 | -| MIO_PAD_SLEEP_EN_21 | 0x654 | -| MIO_PAD_SLEEP_EN_22 | 0x658 | -| MIO_PAD_SLEEP_EN_23 | 0x65c | -| MIO_PAD_SLEEP_EN_24 | 0x660 | -| MIO_PAD_SLEEP_EN_25 | 0x664 | -| MIO_PAD_SLEEP_EN_26 | 0x668 | -| MIO_PAD_SLEEP_EN_27 | 0x66c | -| MIO_PAD_SLEEP_EN_28 | 0x670 | -| MIO_PAD_SLEEP_EN_29 | 0x674 | -| MIO_PAD_SLEEP_EN_30 | 0x678 | -| MIO_PAD_SLEEP_EN_31 | 0x67c | -| MIO_PAD_SLEEP_EN_32 | 0x680 | -| MIO_PAD_SLEEP_EN_33 | 0x684 | -| MIO_PAD_SLEEP_EN_34 | 0x688 | -| MIO_PAD_SLEEP_EN_35 | 0x68c | -| MIO_PAD_SLEEP_EN_36 | 0x690 | -| MIO_PAD_SLEEP_EN_37 | 0x694 | -| MIO_PAD_SLEEP_EN_38 | 0x698 | -| MIO_PAD_SLEEP_EN_39 | 0x69c | -| MIO_PAD_SLEEP_EN_40 | 0x6a0 | -| MIO_PAD_SLEEP_EN_41 | 0x6a4 | -| MIO_PAD_SLEEP_EN_42 | 0x6a8 | -| MIO_PAD_SLEEP_EN_43 | 0x6ac | -| MIO_PAD_SLEEP_EN_44 | 0x6b0 | -| MIO_PAD_SLEEP_EN_45 | 0x6b4 | -| MIO_PAD_SLEEP_EN_46 | 0x6b8 | +| MIO_PAD_SLEEP_EN_0 | 0x610 | +| MIO_PAD_SLEEP_EN_1 | 0x614 | +| MIO_PAD_SLEEP_EN_2 | 0x618 | +| MIO_PAD_SLEEP_EN_3 | 0x61c | +| MIO_PAD_SLEEP_EN_4 | 0x620 | +| MIO_PAD_SLEEP_EN_5 | 0x624 | +| MIO_PAD_SLEEP_EN_6 | 0x628 | +| MIO_PAD_SLEEP_EN_7 | 0x62c | +| MIO_PAD_SLEEP_EN_8 | 0x630 | +| MIO_PAD_SLEEP_EN_9 | 0x634 | +| MIO_PAD_SLEEP_EN_10 | 0x638 | +| MIO_PAD_SLEEP_EN_11 | 0x63c | +| MIO_PAD_SLEEP_EN_12 | 0x640 | +| MIO_PAD_SLEEP_EN_13 | 0x644 | +| MIO_PAD_SLEEP_EN_14 | 0x648 | +| MIO_PAD_SLEEP_EN_15 | 0x64c | +| MIO_PAD_SLEEP_EN_16 | 0x650 | +| MIO_PAD_SLEEP_EN_17 | 0x654 | +| MIO_PAD_SLEEP_EN_18 | 0x658 | +| MIO_PAD_SLEEP_EN_19 | 0x65c | +| MIO_PAD_SLEEP_EN_20 | 0x660 | +| MIO_PAD_SLEEP_EN_21 | 0x664 | +| MIO_PAD_SLEEP_EN_22 | 0x668 | +| MIO_PAD_SLEEP_EN_23 | 0x66c | +| MIO_PAD_SLEEP_EN_24 | 0x670 | +| MIO_PAD_SLEEP_EN_25 | 0x674 | +| MIO_PAD_SLEEP_EN_26 | 0x678 | +| MIO_PAD_SLEEP_EN_27 | 0x67c | +| MIO_PAD_SLEEP_EN_28 | 0x680 | +| MIO_PAD_SLEEP_EN_29 | 0x684 | +| MIO_PAD_SLEEP_EN_30 | 0x688 | +| MIO_PAD_SLEEP_EN_31 | 0x68c | +| MIO_PAD_SLEEP_EN_32 | 0x690 | +| MIO_PAD_SLEEP_EN_33 | 0x694 | +| MIO_PAD_SLEEP_EN_34 | 0x698 | +| MIO_PAD_SLEEP_EN_35 | 0x69c | +| MIO_PAD_SLEEP_EN_36 | 0x6a0 | +| MIO_PAD_SLEEP_EN_37 | 0x6a4 | +| MIO_PAD_SLEEP_EN_38 | 0x6a8 | +| MIO_PAD_SLEEP_EN_39 | 0x6ac | +| MIO_PAD_SLEEP_EN_40 | 0x6b0 | +| MIO_PAD_SLEEP_EN_41 | 0x6b4 | +| MIO_PAD_SLEEP_EN_42 | 0x6b8 | +| MIO_PAD_SLEEP_EN_43 | 0x6bc | +| MIO_PAD_SLEEP_EN_44 | 0x6c0 | +| MIO_PAD_SLEEP_EN_45 | 0x6c4 | +| MIO_PAD_SLEEP_EN_46 | 0x6c8 | ### Fields @@ -1431,53 +1439,53 @@ Defines sleep behavior of the corresponding muxed pad. | Name | Offset | |:----------------------|:---------| -| MIO_PAD_SLEEP_MODE_0 | 0x6bc | -| MIO_PAD_SLEEP_MODE_1 | 0x6c0 | -| MIO_PAD_SLEEP_MODE_2 | 0x6c4 | -| MIO_PAD_SLEEP_MODE_3 | 0x6c8 | -| MIO_PAD_SLEEP_MODE_4 | 0x6cc | -| MIO_PAD_SLEEP_MODE_5 | 0x6d0 | -| MIO_PAD_SLEEP_MODE_6 | 0x6d4 | -| MIO_PAD_SLEEP_MODE_7 | 0x6d8 | -| MIO_PAD_SLEEP_MODE_8 | 0x6dc | -| MIO_PAD_SLEEP_MODE_9 | 0x6e0 | -| MIO_PAD_SLEEP_MODE_10 | 0x6e4 | -| MIO_PAD_SLEEP_MODE_11 | 0x6e8 | -| MIO_PAD_SLEEP_MODE_12 | 0x6ec | -| MIO_PAD_SLEEP_MODE_13 | 0x6f0 | -| MIO_PAD_SLEEP_MODE_14 | 0x6f4 | -| MIO_PAD_SLEEP_MODE_15 | 0x6f8 | -| MIO_PAD_SLEEP_MODE_16 | 0x6fc | -| MIO_PAD_SLEEP_MODE_17 | 0x700 | -| MIO_PAD_SLEEP_MODE_18 | 0x704 | -| MIO_PAD_SLEEP_MODE_19 | 0x708 | -| MIO_PAD_SLEEP_MODE_20 | 0x70c | -| MIO_PAD_SLEEP_MODE_21 | 0x710 | -| MIO_PAD_SLEEP_MODE_22 | 0x714 | -| MIO_PAD_SLEEP_MODE_23 | 0x718 | -| MIO_PAD_SLEEP_MODE_24 | 0x71c | -| MIO_PAD_SLEEP_MODE_25 | 0x720 | -| MIO_PAD_SLEEP_MODE_26 | 0x724 | -| MIO_PAD_SLEEP_MODE_27 | 0x728 | -| MIO_PAD_SLEEP_MODE_28 | 0x72c | -| MIO_PAD_SLEEP_MODE_29 | 0x730 | -| MIO_PAD_SLEEP_MODE_30 | 0x734 | -| MIO_PAD_SLEEP_MODE_31 | 0x738 | -| MIO_PAD_SLEEP_MODE_32 | 0x73c | -| MIO_PAD_SLEEP_MODE_33 | 0x740 | -| MIO_PAD_SLEEP_MODE_34 | 0x744 | -| MIO_PAD_SLEEP_MODE_35 | 0x748 | -| MIO_PAD_SLEEP_MODE_36 | 0x74c | -| MIO_PAD_SLEEP_MODE_37 | 0x750 | -| MIO_PAD_SLEEP_MODE_38 | 0x754 | -| MIO_PAD_SLEEP_MODE_39 | 0x758 | -| MIO_PAD_SLEEP_MODE_40 | 0x75c | -| MIO_PAD_SLEEP_MODE_41 | 0x760 | -| MIO_PAD_SLEEP_MODE_42 | 0x764 | -| MIO_PAD_SLEEP_MODE_43 | 0x768 | -| MIO_PAD_SLEEP_MODE_44 | 0x76c | -| MIO_PAD_SLEEP_MODE_45 | 0x770 | -| MIO_PAD_SLEEP_MODE_46 | 0x774 | +| MIO_PAD_SLEEP_MODE_0 | 0x6cc | +| MIO_PAD_SLEEP_MODE_1 | 0x6d0 | +| MIO_PAD_SLEEP_MODE_2 | 0x6d4 | +| MIO_PAD_SLEEP_MODE_3 | 0x6d8 | +| MIO_PAD_SLEEP_MODE_4 | 0x6dc | +| MIO_PAD_SLEEP_MODE_5 | 0x6e0 | +| MIO_PAD_SLEEP_MODE_6 | 0x6e4 | +| MIO_PAD_SLEEP_MODE_7 | 0x6e8 | +| MIO_PAD_SLEEP_MODE_8 | 0x6ec | +| MIO_PAD_SLEEP_MODE_9 | 0x6f0 | +| MIO_PAD_SLEEP_MODE_10 | 0x6f4 | +| MIO_PAD_SLEEP_MODE_11 | 0x6f8 | +| MIO_PAD_SLEEP_MODE_12 | 0x6fc | +| MIO_PAD_SLEEP_MODE_13 | 0x700 | +| MIO_PAD_SLEEP_MODE_14 | 0x704 | +| MIO_PAD_SLEEP_MODE_15 | 0x708 | +| MIO_PAD_SLEEP_MODE_16 | 0x70c | +| MIO_PAD_SLEEP_MODE_17 | 0x710 | +| MIO_PAD_SLEEP_MODE_18 | 0x714 | +| MIO_PAD_SLEEP_MODE_19 | 0x718 | +| MIO_PAD_SLEEP_MODE_20 | 0x71c | +| MIO_PAD_SLEEP_MODE_21 | 0x720 | +| MIO_PAD_SLEEP_MODE_22 | 0x724 | +| MIO_PAD_SLEEP_MODE_23 | 0x728 | +| MIO_PAD_SLEEP_MODE_24 | 0x72c | +| MIO_PAD_SLEEP_MODE_25 | 0x730 | +| MIO_PAD_SLEEP_MODE_26 | 0x734 | +| MIO_PAD_SLEEP_MODE_27 | 0x738 | +| MIO_PAD_SLEEP_MODE_28 | 0x73c | +| MIO_PAD_SLEEP_MODE_29 | 0x740 | +| MIO_PAD_SLEEP_MODE_30 | 0x744 | +| MIO_PAD_SLEEP_MODE_31 | 0x748 | +| MIO_PAD_SLEEP_MODE_32 | 0x74c | +| MIO_PAD_SLEEP_MODE_33 | 0x750 | +| MIO_PAD_SLEEP_MODE_34 | 0x754 | +| MIO_PAD_SLEEP_MODE_35 | 0x758 | +| MIO_PAD_SLEEP_MODE_36 | 0x75c | +| MIO_PAD_SLEEP_MODE_37 | 0x760 | +| MIO_PAD_SLEEP_MODE_38 | 0x764 | +| MIO_PAD_SLEEP_MODE_39 | 0x768 | +| MIO_PAD_SLEEP_MODE_40 | 0x76c | +| MIO_PAD_SLEEP_MODE_41 | 0x770 | +| MIO_PAD_SLEEP_MODE_42 | 0x774 | +| MIO_PAD_SLEEP_MODE_43 | 0x778 | +| MIO_PAD_SLEEP_MODE_44 | 0x77c | +| MIO_PAD_SLEEP_MODE_45 | 0x780 | +| MIO_PAD_SLEEP_MODE_46 | 0x784 | ### Fields @@ -1504,7 +1512,7 @@ Value to drive in deep sleep. ## DIO_PAD_SLEEP_STATUS Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x778` +- Offset: `0x788` - Reset default: `0x0` - Reset mask: `0xffff` @@ -1543,22 +1551,22 @@ Register write enable for DIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| DIO_PAD_SLEEP_REGWEN_0 | 0x77c | -| DIO_PAD_SLEEP_REGWEN_1 | 0x780 | -| DIO_PAD_SLEEP_REGWEN_2 | 0x784 | -| DIO_PAD_SLEEP_REGWEN_3 | 0x788 | -| DIO_PAD_SLEEP_REGWEN_4 | 0x78c | -| DIO_PAD_SLEEP_REGWEN_5 | 0x790 | -| DIO_PAD_SLEEP_REGWEN_6 | 0x794 | -| DIO_PAD_SLEEP_REGWEN_7 | 0x798 | -| DIO_PAD_SLEEP_REGWEN_8 | 0x79c | -| DIO_PAD_SLEEP_REGWEN_9 | 0x7a0 | -| DIO_PAD_SLEEP_REGWEN_10 | 0x7a4 | -| DIO_PAD_SLEEP_REGWEN_11 | 0x7a8 | -| DIO_PAD_SLEEP_REGWEN_12 | 0x7ac | -| DIO_PAD_SLEEP_REGWEN_13 | 0x7b0 | -| DIO_PAD_SLEEP_REGWEN_14 | 0x7b4 | -| DIO_PAD_SLEEP_REGWEN_15 | 0x7b8 | +| DIO_PAD_SLEEP_REGWEN_0 | 0x78c | +| DIO_PAD_SLEEP_REGWEN_1 | 0x790 | +| DIO_PAD_SLEEP_REGWEN_2 | 0x794 | +| DIO_PAD_SLEEP_REGWEN_3 | 0x798 | +| DIO_PAD_SLEEP_REGWEN_4 | 0x79c | +| DIO_PAD_SLEEP_REGWEN_5 | 0x7a0 | +| DIO_PAD_SLEEP_REGWEN_6 | 0x7a4 | +| DIO_PAD_SLEEP_REGWEN_7 | 0x7a8 | +| DIO_PAD_SLEEP_REGWEN_8 | 0x7ac | +| DIO_PAD_SLEEP_REGWEN_9 | 0x7b0 | +| DIO_PAD_SLEEP_REGWEN_10 | 0x7b4 | +| DIO_PAD_SLEEP_REGWEN_11 | 0x7b8 | +| DIO_PAD_SLEEP_REGWEN_12 | 0x7bc | +| DIO_PAD_SLEEP_REGWEN_13 | 0x7c0 | +| DIO_PAD_SLEEP_REGWEN_14 | 0x7c4 | +| DIO_PAD_SLEEP_REGWEN_15 | 0x7c8 | ### Fields @@ -1581,22 +1589,22 @@ Enables the sleep mode of the corresponding dedicated pad. | Name | Offset | |:--------------------|:---------| -| DIO_PAD_SLEEP_EN_0 | 0x7bc | -| DIO_PAD_SLEEP_EN_1 | 0x7c0 | -| DIO_PAD_SLEEP_EN_2 | 0x7c4 | -| DIO_PAD_SLEEP_EN_3 | 0x7c8 | -| DIO_PAD_SLEEP_EN_4 | 0x7cc | -| DIO_PAD_SLEEP_EN_5 | 0x7d0 | -| DIO_PAD_SLEEP_EN_6 | 0x7d4 | -| DIO_PAD_SLEEP_EN_7 | 0x7d8 | -| DIO_PAD_SLEEP_EN_8 | 0x7dc | -| DIO_PAD_SLEEP_EN_9 | 0x7e0 | -| DIO_PAD_SLEEP_EN_10 | 0x7e4 | -| DIO_PAD_SLEEP_EN_11 | 0x7e8 | -| DIO_PAD_SLEEP_EN_12 | 0x7ec | -| DIO_PAD_SLEEP_EN_13 | 0x7f0 | -| DIO_PAD_SLEEP_EN_14 | 0x7f4 | -| DIO_PAD_SLEEP_EN_15 | 0x7f8 | +| DIO_PAD_SLEEP_EN_0 | 0x7cc | +| DIO_PAD_SLEEP_EN_1 | 0x7d0 | +| DIO_PAD_SLEEP_EN_2 | 0x7d4 | +| DIO_PAD_SLEEP_EN_3 | 0x7d8 | +| DIO_PAD_SLEEP_EN_4 | 0x7dc | +| DIO_PAD_SLEEP_EN_5 | 0x7e0 | +| DIO_PAD_SLEEP_EN_6 | 0x7e4 | +| DIO_PAD_SLEEP_EN_7 | 0x7e8 | +| DIO_PAD_SLEEP_EN_8 | 0x7ec | +| DIO_PAD_SLEEP_EN_9 | 0x7f0 | +| DIO_PAD_SLEEP_EN_10 | 0x7f4 | +| DIO_PAD_SLEEP_EN_11 | 0x7f8 | +| DIO_PAD_SLEEP_EN_12 | 0x7fc | +| DIO_PAD_SLEEP_EN_13 | 0x800 | +| DIO_PAD_SLEEP_EN_14 | 0x804 | +| DIO_PAD_SLEEP_EN_15 | 0x808 | ### Fields @@ -1629,22 +1637,22 @@ Defines sleep behavior of the corresponding dedicated pad. | Name | Offset | |:----------------------|:---------| -| DIO_PAD_SLEEP_MODE_0 | 0x7fc | -| DIO_PAD_SLEEP_MODE_1 | 0x800 | -| DIO_PAD_SLEEP_MODE_2 | 0x804 | -| DIO_PAD_SLEEP_MODE_3 | 0x808 | -| DIO_PAD_SLEEP_MODE_4 | 0x80c | -| DIO_PAD_SLEEP_MODE_5 | 0x810 | -| DIO_PAD_SLEEP_MODE_6 | 0x814 | -| DIO_PAD_SLEEP_MODE_7 | 0x818 | -| DIO_PAD_SLEEP_MODE_8 | 0x81c | -| DIO_PAD_SLEEP_MODE_9 | 0x820 | -| DIO_PAD_SLEEP_MODE_10 | 0x824 | -| DIO_PAD_SLEEP_MODE_11 | 0x828 | -| DIO_PAD_SLEEP_MODE_12 | 0x82c | -| DIO_PAD_SLEEP_MODE_13 | 0x830 | -| DIO_PAD_SLEEP_MODE_14 | 0x834 | -| DIO_PAD_SLEEP_MODE_15 | 0x838 | +| DIO_PAD_SLEEP_MODE_0 | 0x80c | +| DIO_PAD_SLEEP_MODE_1 | 0x810 | +| DIO_PAD_SLEEP_MODE_2 | 0x814 | +| DIO_PAD_SLEEP_MODE_3 | 0x818 | +| DIO_PAD_SLEEP_MODE_4 | 0x81c | +| DIO_PAD_SLEEP_MODE_5 | 0x820 | +| DIO_PAD_SLEEP_MODE_6 | 0x824 | +| DIO_PAD_SLEEP_MODE_7 | 0x828 | +| DIO_PAD_SLEEP_MODE_8 | 0x82c | +| DIO_PAD_SLEEP_MODE_9 | 0x830 | +| DIO_PAD_SLEEP_MODE_10 | 0x834 | +| DIO_PAD_SLEEP_MODE_11 | 0x838 | +| DIO_PAD_SLEEP_MODE_12 | 0x83c | +| DIO_PAD_SLEEP_MODE_13 | 0x840 | +| DIO_PAD_SLEEP_MODE_14 | 0x844 | +| DIO_PAD_SLEEP_MODE_15 | 0x848 | ### Fields @@ -1678,14 +1686,14 @@ Register write enable for wakeup detectors. | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_REGWEN_0 | 0x83c | -| WKUP_DETECTOR_REGWEN_1 | 0x840 | -| WKUP_DETECTOR_REGWEN_2 | 0x844 | -| WKUP_DETECTOR_REGWEN_3 | 0x848 | -| WKUP_DETECTOR_REGWEN_4 | 0x84c | -| WKUP_DETECTOR_REGWEN_5 | 0x850 | -| WKUP_DETECTOR_REGWEN_6 | 0x854 | -| WKUP_DETECTOR_REGWEN_7 | 0x858 | +| WKUP_DETECTOR_REGWEN_0 | 0x84c | +| WKUP_DETECTOR_REGWEN_1 | 0x850 | +| WKUP_DETECTOR_REGWEN_2 | 0x854 | +| WKUP_DETECTOR_REGWEN_3 | 0x858 | +| WKUP_DETECTOR_REGWEN_4 | 0x85c | +| WKUP_DETECTOR_REGWEN_5 | 0x860 | +| WKUP_DETECTOR_REGWEN_6 | 0x864 | +| WKUP_DETECTOR_REGWEN_7 | 0x868 | ### Fields @@ -1711,14 +1719,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-------------------|:---------| -| WKUP_DETECTOR_EN_0 | 0x85c | -| WKUP_DETECTOR_EN_1 | 0x860 | -| WKUP_DETECTOR_EN_2 | 0x864 | -| WKUP_DETECTOR_EN_3 | 0x868 | -| WKUP_DETECTOR_EN_4 | 0x86c | -| WKUP_DETECTOR_EN_5 | 0x870 | -| WKUP_DETECTOR_EN_6 | 0x874 | -| WKUP_DETECTOR_EN_7 | 0x878 | +| WKUP_DETECTOR_EN_0 | 0x86c | +| WKUP_DETECTOR_EN_1 | 0x870 | +| WKUP_DETECTOR_EN_2 | 0x874 | +| WKUP_DETECTOR_EN_3 | 0x878 | +| WKUP_DETECTOR_EN_4 | 0x87c | +| WKUP_DETECTOR_EN_5 | 0x880 | +| WKUP_DETECTOR_EN_6 | 0x884 | +| WKUP_DETECTOR_EN_7 | 0x888 | ### Fields @@ -1747,14 +1755,14 @@ The reason for that is that the pulse width counter is NOT cleared upon a mode c | Name | Offset | |:----------------|:---------| -| WKUP_DETECTOR_0 | 0x87c | -| WKUP_DETECTOR_1 | 0x880 | -| WKUP_DETECTOR_2 | 0x884 | -| WKUP_DETECTOR_3 | 0x888 | -| WKUP_DETECTOR_4 | 0x88c | -| WKUP_DETECTOR_5 | 0x890 | -| WKUP_DETECTOR_6 | 0x894 | -| WKUP_DETECTOR_7 | 0x898 | +| WKUP_DETECTOR_0 | 0x88c | +| WKUP_DETECTOR_1 | 0x890 | +| WKUP_DETECTOR_2 | 0x894 | +| WKUP_DETECTOR_3 | 0x898 | +| WKUP_DETECTOR_4 | 0x89c | +| WKUP_DETECTOR_5 | 0x8a0 | +| WKUP_DETECTOR_6 | 0x8a4 | +| WKUP_DETECTOR_7 | 0x8a8 | ### Fields @@ -1804,14 +1812,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_CNT_TH_0 | 0x89c | -| WKUP_DETECTOR_CNT_TH_1 | 0x8a0 | -| WKUP_DETECTOR_CNT_TH_2 | 0x8a4 | -| WKUP_DETECTOR_CNT_TH_3 | 0x8a8 | -| WKUP_DETECTOR_CNT_TH_4 | 0x8ac | -| WKUP_DETECTOR_CNT_TH_5 | 0x8b0 | -| WKUP_DETECTOR_CNT_TH_6 | 0x8b4 | -| WKUP_DETECTOR_CNT_TH_7 | 0x8b8 | +| WKUP_DETECTOR_CNT_TH_0 | 0x8ac | +| WKUP_DETECTOR_CNT_TH_1 | 0x8b0 | +| WKUP_DETECTOR_CNT_TH_2 | 0x8b4 | +| WKUP_DETECTOR_CNT_TH_3 | 0x8b8 | +| WKUP_DETECTOR_CNT_TH_4 | 0x8bc | +| WKUP_DETECTOR_CNT_TH_5 | 0x8c0 | +| WKUP_DETECTOR_CNT_TH_6 | 0x8c4 | +| WKUP_DETECTOR_CNT_TH_7 | 0x8c8 | ### Fields @@ -1835,14 +1843,14 @@ This register is NOT synced to the AON domain since the muxing mechanism is impl | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_PADSEL_0 | 0x8bc | -| WKUP_DETECTOR_PADSEL_1 | 0x8c0 | -| WKUP_DETECTOR_PADSEL_2 | 0x8c4 | -| WKUP_DETECTOR_PADSEL_3 | 0x8c8 | -| WKUP_DETECTOR_PADSEL_4 | 0x8cc | -| WKUP_DETECTOR_PADSEL_5 | 0x8d0 | -| WKUP_DETECTOR_PADSEL_6 | 0x8d4 | -| WKUP_DETECTOR_PADSEL_7 | 0x8d8 | +| WKUP_DETECTOR_PADSEL_0 | 0x8cc | +| WKUP_DETECTOR_PADSEL_1 | 0x8d0 | +| WKUP_DETECTOR_PADSEL_2 | 0x8d4 | +| WKUP_DETECTOR_PADSEL_3 | 0x8d8 | +| WKUP_DETECTOR_PADSEL_4 | 0x8dc | +| WKUP_DETECTOR_PADSEL_5 | 0x8e0 | +| WKUP_DETECTOR_PADSEL_6 | 0x8e4 | +| WKUP_DETECTOR_PADSEL_7 | 0x8e8 | ### Fields @@ -1867,7 +1875,7 @@ Cause registers for wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed. -- Offset: `0x8dc` +- Offset: `0x8ec` - Reset default: `0x0` - Reset mask: `0xff` diff --git a/hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el b/hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el index d262656329e919..7f62a02d0ba8df 100644 --- a/hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el +++ b/hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el @@ -15,6 +15,10 @@ CHECKSUM: "258095983 1288805244" INSTANCE: tb.dut ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c3_n [0] "logic resets_o.rst_i2c3_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c3_n [0] "logic resets_o.rst_i2c3_n[1:0]" +ANNOTATION: "VC_COV_UNR" Toggle 0to1 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" ANNOTATION: "VC_COV_UNR" Toggle 1to0 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" diff --git a/hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv b/hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv index 0a44cd8c83fba8..8da78ae40c4bf6 100644 --- a/hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv +++ b/hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv @@ -42,6 +42,7 @@ package rstmgr_env_pkg; "u_d0_i2c0", "u_d0_i2c1", "u_d0_i2c2", + "u_d0_i2c3", "u_d0_lc", "u_d0_lc_io", "u_d0_lc_io_div2", diff --git a/hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv b/hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv index e39a53001b674e..2e59284d01839f 100644 --- a/hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv +++ b/hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv @@ -113,6 +113,7 @@ class rstmgr_scoreboard extends cip_base_scoreboard #( "5": blocked = `gmv(ral.sw_rst_regwen[5]) == 0; "6": blocked = `gmv(ral.sw_rst_regwen[6]) == 0; "7": blocked = `gmv(ral.sw_rst_regwen[7]) == 0; + "8": blocked = `gmv(ral.sw_rst_regwen[8]) == 0; default: `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", ral_name)) endcase diff --git a/hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv b/hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv index babe8cac35e622..87932b75bbf524 100644 --- a/hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv +++ b/hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv @@ -49,6 +49,7 @@ module rstmgr_bind; .parent_rst_n(rst_sys_src_n[1]), .ctrl_ns(reg2hw.sw_rst_ctrl_n), .rst_ens({ + rst_en_o.i2c3[1] == prim_mubi_pkg::MuBi4True, rst_en_o.i2c2[1] == prim_mubi_pkg::MuBi4True, rst_en_o.i2c1[1] == prim_mubi_pkg::MuBi4True, rst_en_o.i2c0[1] == prim_mubi_pkg::MuBi4True, @@ -59,6 +60,7 @@ module rstmgr_bind; rst_en_o.spi_device[1] == prim_mubi_pkg::MuBi4True }), .rst_ns({ + resets_o.rst_i2c3_n[1], resets_o.rst_i2c2_n[1], resets_o.rst_i2c1_n[1], resets_o.rst_i2c0_n[1], diff --git a/hw/top_earlgrey/cdc/cdc_waivers.data.tcl b/hw/top_earlgrey/cdc/cdc_waivers.data.tcl index 9dcc1f16e8e448..7012eb4e7fc607 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.data.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.data.tcl @@ -5,6 +5,8 @@ # Verix CDC waiver file set_rule_status -rule {CNTL} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal =~ "IO*") && (Association == "None") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} +set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c3.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} +set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c3.i2c_core.sda_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c2.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c2.i2c_core.sda_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c1.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index c6e18e30117d4c..2a52dd91a40e8e 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -515,6 +515,20 @@ parent: lc_src clock: io_div4 } + { + name: i2c3 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c3_n + parent: lc_src + clock: io_div4 + } ] } num_cores: "1" @@ -1018,6 +1032,53 @@ null: 0x400A0000 } } + { + name: i2c3 + type: i2c + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: i2c3 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: i2c3 + default: "" + end_idx: -1 + top_signame: i2c3_tl + index: -1 + } + ] + base_addrs: + { + null: 0x400B0000 + } + } { name: pattgen type: pattgen @@ -8591,6 +8652,10 @@ [ peri.tl_i2c2 ] + i2c3.tl: + [ + peri.tl_i2c3 + ] pattgen.tl: [ peri.tl_pattgen @@ -9721,6 +9786,7 @@ i2c0 i2c1 i2c2 + i2c3 pattgen gpio spi_device @@ -9883,6 +9949,24 @@ stub: false req_fifo_pass: true } + { + name: i2c3 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: i2c + addr_range: + [ + { + base_addr: 0x400b0000 + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } { name: pattgen type: device @@ -10344,6 +10428,18 @@ top_signame: i2c2_tl index: -1 } + { + name: tl_i2c3 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: i2c3_tl + index: -1 + } { name: tl_pattgen struct: tl @@ -11412,6 +11508,14 @@ desc: "" attr: "" } + { + instance: i2c3 + port: "" + connection: muxed + pad: "" + desc: "" + attr: "" + } { instance: pattgen port: "" @@ -12121,6 +12225,28 @@ desc: "" glob_idx: 37 } + { + name: i2c3_sda + width: 1 + type: inout + idx: -1 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 38 + } + { + name: i2c3_scl + width: 1 + type: inout + idx: -1 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 39 + } { name: spi_host1_sd width: 4 @@ -12130,7 +12256,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 38 + glob_idx: 40 } { name: spi_host1_sd @@ -12141,7 +12267,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 39 + glob_idx: 41 } { name: spi_host1_sd @@ -12152,7 +12278,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 40 + glob_idx: 42 } { name: spi_host1_sd @@ -12163,7 +12289,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 41 + glob_idx: 43 } { name: sysrst_ctrl_aon_ec_rst_l @@ -12218,7 +12344,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 42 + glob_idx: 44 } { name: uart1_rx @@ -12229,7 +12355,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 43 + glob_idx: 45 } { name: uart2_rx @@ -12240,7 +12366,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 44 + glob_idx: 46 } { name: uart3_rx @@ -12251,7 +12377,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 45 + glob_idx: 47 } { name: spi_device_tpm_csb @@ -12262,7 +12388,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 46 + glob_idx: 48 } { name: flash_ctrl_tck @@ -12273,7 +12399,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 47 + glob_idx: 49 } { name: flash_ctrl_tms @@ -12284,7 +12410,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 48 + glob_idx: 50 } { name: flash_ctrl_tdi @@ -12295,7 +12421,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 49 + glob_idx: 51 } { name: sysrst_ctrl_aon_ac_present @@ -12306,7 +12432,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 50 + glob_idx: 52 } { name: sysrst_ctrl_aon_key0_in @@ -12317,7 +12443,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 51 + glob_idx: 53 } { name: sysrst_ctrl_aon_key1_in @@ -12328,7 +12454,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 52 + glob_idx: 54 } { name: sysrst_ctrl_aon_key2_in @@ -12339,7 +12465,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 53 + glob_idx: 55 } { name: sysrst_ctrl_aon_pwrb_in @@ -12350,7 +12476,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 54 + glob_idx: 56 } { name: sysrst_ctrl_aon_lid_open @@ -12361,7 +12487,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 55 + glob_idx: 57 } { name: usbdev_sense @@ -12372,7 +12498,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 56 + glob_idx: 58 } { name: spi_host0_sck @@ -12405,7 +12531,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 42 + glob_idx: 44 } { name: uart1_tx @@ -12416,7 +12542,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 43 + glob_idx: 45 } { name: uart2_tx @@ -12427,7 +12553,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 44 + glob_idx: 46 } { name: uart3_tx @@ -12438,7 +12564,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 45 + glob_idx: 47 } { name: pattgen_pda0_tx @@ -12449,7 +12575,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 46 + glob_idx: 48 } { name: pattgen_pcl0_tx @@ -12460,7 +12586,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 47 + glob_idx: 49 } { name: pattgen_pda1_tx @@ -12471,7 +12597,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 48 + glob_idx: 50 } { name: pattgen_pcl1_tx @@ -12482,7 +12608,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 49 + glob_idx: 51 } { name: spi_host1_sck @@ -12493,7 +12619,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 50 + glob_idx: 52 } { name: spi_host1_csb @@ -12504,7 +12630,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 51 + glob_idx: 53 } { name: flash_ctrl_tdo @@ -12515,7 +12641,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 52 + glob_idx: 54 } { name: sensor_ctrl_aon_ast_debug_out @@ -12526,7 +12652,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 53 + glob_idx: 55 } { name: sensor_ctrl_aon_ast_debug_out @@ -12537,7 +12663,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 54 + glob_idx: 56 } { name: sensor_ctrl_aon_ast_debug_out @@ -12548,7 +12674,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 55 + glob_idx: 57 } { name: sensor_ctrl_aon_ast_debug_out @@ -12559,7 +12685,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 56 + glob_idx: 58 } { name: sensor_ctrl_aon_ast_debug_out @@ -12570,7 +12696,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 57 + glob_idx: 59 } { name: sensor_ctrl_aon_ast_debug_out @@ -12581,7 +12707,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 58 + glob_idx: 60 } { name: sensor_ctrl_aon_ast_debug_out @@ -12592,7 +12718,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 59 + glob_idx: 61 } { name: sensor_ctrl_aon_ast_debug_out @@ -12603,7 +12729,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 60 + glob_idx: 62 } { name: sensor_ctrl_aon_ast_debug_out @@ -12614,7 +12740,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 61 + glob_idx: 63 } { name: pwm_aon_pwm @@ -12625,7 +12751,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 62 + glob_idx: 64 } { name: pwm_aon_pwm @@ -12636,7 +12762,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 63 + glob_idx: 65 } { name: pwm_aon_pwm @@ -12647,7 +12773,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 64 + glob_idx: 66 } { name: pwm_aon_pwm @@ -12658,7 +12784,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 65 + glob_idx: 67 } { name: pwm_aon_pwm @@ -12669,7 +12795,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 66 + glob_idx: 68 } { name: pwm_aon_pwm @@ -12680,7 +12806,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 67 + glob_idx: 69 } { name: otp_ctrl_test @@ -12691,7 +12817,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 68 + glob_idx: 70 } { name: sysrst_ctrl_aon_bat_disable @@ -12702,7 +12828,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 69 + glob_idx: 71 } { name: sysrst_ctrl_aon_key0_out @@ -12713,7 +12839,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 70 + glob_idx: 72 } { name: sysrst_ctrl_aon_key1_out @@ -12724,7 +12850,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 71 + glob_idx: 73 } { name: sysrst_ctrl_aon_key2_out @@ -12735,7 +12861,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 72 + glob_idx: 74 } { name: sysrst_ctrl_aon_pwrb_out @@ -12746,7 +12872,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 73 + glob_idx: 75 } { name: sysrst_ctrl_aon_z3_wakeup @@ -12757,7 +12883,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 74 + glob_idx: 76 } ] io_counts: @@ -12771,7 +12897,7 @@ } muxed: { - inouts: 42 + inouts: 44 inputs: 15 outputs: 33 pads: 47 @@ -13306,6 +13432,7 @@ i2c0 i2c1 i2c2 + i2c3 pattgen rv_timer otp_ctrl @@ -13846,6 +13973,96 @@ type: interrupt module_name: i2c2 } + { + name: i2c3_fmt_threshold + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_rx_threshold + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_fmt_overflow + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_rx_overflow + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_nak + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_scl_interference + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_sda_interference + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_stretch_timeout + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_sda_unstable + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_cmd_complete + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_tx_stretch + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_tx_overflow + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_acq_full + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_unexp_stop + width: 1 + type: interrupt + module_name: i2c3 + } + { + name: i2c3_host_timeout + width: 1 + type: interrupt + module_name: i2c3 + } { name: pattgen_done_ch0 width: 1 @@ -14242,6 +14459,7 @@ i2c0 i2c1 i2c2 + i2c3 pattgen rv_timer otp_ctrl @@ -14358,6 +14576,15 @@ lpg_name: peri_i2c2_0 lpg_idx: 4 } + { + name: i2c3_fatal_fault + width: 1 + type: alert + async: "1" + module_name: i2c3 + lpg_name: peri_i2c3_0 + lpg_idx: 5 + } { name: pattgen_fatal_fault width: 1 @@ -14374,7 +14601,7 @@ async: "1" module_name: rv_timer lpg_name: timers_lc_io_div4_0 - lpg_idx: 5 + lpg_idx: 6 } { name: otp_ctrl_fatal_macro_error @@ -14383,7 +14610,7 @@ async: "1" module_name: otp_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: otp_ctrl_fatal_check_error @@ -14392,7 +14619,7 @@ async: "1" module_name: otp_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: otp_ctrl_fatal_bus_integ_error @@ -14401,7 +14628,7 @@ async: "1" module_name: otp_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: otp_ctrl_fatal_prim_otp_alert @@ -14410,7 +14637,7 @@ async: "1" module_name: otp_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: otp_ctrl_recov_prim_otp_alert @@ -14419,7 +14646,7 @@ async: "1" module_name: otp_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: lc_ctrl_fatal_prog_error @@ -14428,7 +14655,7 @@ async: "1" module_name: lc_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: lc_ctrl_fatal_state_error @@ -14437,7 +14664,7 @@ async: "1" module_name: lc_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: lc_ctrl_fatal_bus_integ_error @@ -14446,7 +14673,7 @@ async: "1" module_name: lc_ctrl lpg_name: secure_lc_io_div4_0 - lpg_idx: 6 + lpg_idx: 7 } { name: spi_host0_fatal_fault @@ -14455,7 +14682,7 @@ async: "1" module_name: spi_host0 lpg_name: peri_spi_host0_0 - lpg_idx: 7 + lpg_idx: 8 } { name: spi_host1_fatal_fault @@ -14464,7 +14691,7 @@ async: "1" module_name: spi_host1 lpg_name: peri_spi_host1_0 - lpg_idx: 8 + lpg_idx: 9 } { name: usbdev_fatal_fault @@ -14473,7 +14700,7 @@ async: "1" module_name: usbdev lpg_name: peri_usb_0 - lpg_idx: 9 + lpg_idx: 10 } { name: pwrmgr_aon_fatal_fault @@ -14482,7 +14709,7 @@ async: "1" module_name: pwrmgr_aon lpg_name: powerup_por_io_div4_Aon - lpg_idx: 10 + lpg_idx: 11 } { name: rstmgr_aon_fatal_fault @@ -14491,7 +14718,7 @@ async: "1" module_name: rstmgr_aon lpg_name: powerup_lc_io_div4_Aon - lpg_idx: 11 + lpg_idx: 12 } { name: rstmgr_aon_fatal_cnsty_fault @@ -14500,7 +14727,7 @@ async: "1" module_name: rstmgr_aon lpg_name: powerup_lc_io_div4_Aon - lpg_idx: 11 + lpg_idx: 12 } { name: clkmgr_aon_recov_fault @@ -14509,7 +14736,7 @@ async: "1" module_name: clkmgr_aon lpg_name: powerup_lc_io_div4_Aon - lpg_idx: 11 + lpg_idx: 12 } { name: clkmgr_aon_fatal_fault @@ -14518,7 +14745,7 @@ async: "1" module_name: clkmgr_aon lpg_name: powerup_lc_io_div4_Aon - lpg_idx: 11 + lpg_idx: 12 } { name: sysrst_ctrl_aon_fatal_fault @@ -14527,7 +14754,7 @@ async: "1" module_name: sysrst_ctrl_aon lpg_name: secure_lc_io_div4_Aon - lpg_idx: 12 + lpg_idx: 13 } { name: adc_ctrl_aon_fatal_fault @@ -14536,7 +14763,7 @@ async: "1" module_name: adc_ctrl_aon lpg_name: peri_lc_io_div4_Aon - lpg_idx: 13 + lpg_idx: 14 } { name: pwm_aon_fatal_fault @@ -14545,7 +14772,7 @@ async: "1" module_name: pwm_aon lpg_name: peri_lc_io_div4_Aon - lpg_idx: 13 + lpg_idx: 14 } { name: pinmux_aon_fatal_fault @@ -14554,7 +14781,7 @@ async: "1" module_name: pinmux_aon lpg_name: powerup_lc_io_div4_Aon - lpg_idx: 11 + lpg_idx: 12 } { name: aon_timer_aon_fatal_fault @@ -14563,7 +14790,7 @@ async: "1" module_name: aon_timer_aon lpg_name: timers_lc_io_div4_Aon - lpg_idx: 14 + lpg_idx: 15 } { name: sensor_ctrl_aon_recov_alert @@ -14572,7 +14799,7 @@ async: "1" module_name: sensor_ctrl_aon lpg_name: secure_lc_io_div4_Aon - lpg_idx: 12 + lpg_idx: 13 } { name: sensor_ctrl_aon_fatal_alert @@ -14581,7 +14808,7 @@ async: "1" module_name: sensor_ctrl_aon lpg_name: secure_lc_io_div4_Aon - lpg_idx: 12 + lpg_idx: 13 } { name: sram_ctrl_ret_aon_fatal_error @@ -14590,7 +14817,7 @@ async: "1" module_name: sram_ctrl_ret_aon lpg_name: infra_lc_io_div4_Aon - lpg_idx: 16 + lpg_idx: 17 } { name: flash_ctrl_recov_err @@ -14599,7 +14826,7 @@ async: "1" module_name: flash_ctrl lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: flash_ctrl_fatal_std_err @@ -14608,7 +14835,7 @@ async: "1" module_name: flash_ctrl lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: flash_ctrl_fatal_err @@ -14617,7 +14844,7 @@ async: "1" module_name: flash_ctrl lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: flash_ctrl_fatal_prim_flash_alert @@ -14626,7 +14853,7 @@ async: "1" module_name: flash_ctrl lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: flash_ctrl_recov_prim_flash_alert @@ -14635,7 +14862,7 @@ async: "1" module_name: flash_ctrl lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: rv_dm_fatal_fault @@ -14644,7 +14871,7 @@ async: "1" module_name: rv_dm lpg_name: infra_sys_0 - lpg_idx: 18 + lpg_idx: 19 } { name: rv_plic_fatal_fault @@ -14653,7 +14880,7 @@ async: "1" module_name: rv_plic lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: aes_recov_ctrl_update_err @@ -14662,7 +14889,7 @@ async: "1" module_name: aes lpg_name: aes_trans_lc_0 - lpg_idx: 20 + lpg_idx: 21 } { name: aes_fatal_fault @@ -14671,7 +14898,7 @@ async: "1" module_name: aes lpg_name: aes_trans_lc_0 - lpg_idx: 20 + lpg_idx: 21 } { name: hmac_fatal_fault @@ -14680,7 +14907,7 @@ async: "1" module_name: hmac lpg_name: hmac_trans_lc_0 - lpg_idx: 21 + lpg_idx: 22 } { name: kmac_recov_operation_err @@ -14689,7 +14916,7 @@ async: "1" module_name: kmac lpg_name: kmac_trans_lc_0 - lpg_idx: 22 + lpg_idx: 23 } { name: kmac_fatal_fault_err @@ -14698,7 +14925,7 @@ async: "1" module_name: kmac lpg_name: kmac_trans_lc_0 - lpg_idx: 22 + lpg_idx: 23 } { name: otbn_fatal @@ -14707,7 +14934,7 @@ async: "1" module_name: otbn lpg_name: otbn_trans_lc_0 - lpg_idx: 23 + lpg_idx: 24 } { name: otbn_recov @@ -14716,7 +14943,7 @@ async: "1" module_name: otbn lpg_name: otbn_trans_lc_0 - lpg_idx: 23 + lpg_idx: 24 } { name: keymgr_recov_operation_err @@ -14725,7 +14952,7 @@ async: "1" module_name: keymgr lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: keymgr_fatal_fault_err @@ -14734,7 +14961,7 @@ async: "1" module_name: keymgr lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: csrng_recov_alert @@ -14743,7 +14970,7 @@ async: "1" module_name: csrng lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: csrng_fatal_alert @@ -14752,7 +14979,7 @@ async: "1" module_name: csrng lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: entropy_src_recov_alert @@ -14761,7 +14988,7 @@ async: "1" module_name: entropy_src lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: entropy_src_fatal_alert @@ -14770,7 +14997,7 @@ async: "1" module_name: entropy_src lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: edn0_recov_alert @@ -14779,7 +15006,7 @@ async: "1" module_name: edn0 lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: edn0_fatal_alert @@ -14788,7 +15015,7 @@ async: "1" module_name: edn0 lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: edn1_recov_alert @@ -14797,7 +15024,7 @@ async: "1" module_name: edn1 lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: edn1_fatal_alert @@ -14806,7 +15033,7 @@ async: "1" module_name: edn1 lpg_name: secure_lc_0 - lpg_idx: 19 + lpg_idx: 20 } { name: sram_ctrl_main_fatal_error @@ -14815,7 +15042,7 @@ async: "1" module_name: sram_ctrl_main lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: rom_ctrl_fatal @@ -14824,7 +15051,7 @@ async: "1" module_name: rom_ctrl lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: rv_core_ibex_fatal_sw_err @@ -14833,7 +15060,7 @@ async: "1" module_name: rv_core_ibex lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: rv_core_ibex_recov_sw_err @@ -14842,7 +15069,7 @@ async: "1" module_name: rv_core_ibex lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: rv_core_ibex_fatal_hw_err @@ -14851,7 +15078,7 @@ async: "1" module_name: rv_core_ibex lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } { name: rv_core_ibex_recov_hw_err @@ -14860,7 +15087,7 @@ async: "1" module_name: rv_core_ibex lpg_name: infra_lc_0 - lpg_idx: 17 + lpg_idx: 18 } ] exported_rsts: {} @@ -14986,6 +15213,30 @@ domain: "0" } } + { + name: peri_i2c3_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_io_peri: io + clk_usb_peri: usb + clk_aon_peri: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + reset_connection: + { + name: i2c3 + domain: "0" + } + } { name: timers_lc_io_div4_0 clock_group: @@ -15598,6 +15849,19 @@ top_signame: i2c2_tl index: -1 } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: i2c3 + default: "" + end_idx: -1 + top_signame: i2c3_tl + index: -1 + } { name: tl struct: tl @@ -20113,6 +20377,18 @@ top_signame: i2c2_tl index: -1 } + { + name: tl_i2c3 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: i2c3_tl + index: -1 + } { name: tl_pattgen struct: tl @@ -22910,6 +23186,28 @@ suffix: rsp default: "" } + { + package: tlul_pkg + struct: tl_h2d + signame: i2c3_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: i2c3_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } { package: tlul_pkg struct: tl_h2d diff --git a/hw/top_earlgrey/data/chip_conn_testplan.hjson b/hw/top_earlgrey/data/chip_conn_testplan.hjson index 22dee284bd4a6d..cf207e45171b1a 100644 --- a/hw/top_earlgrey/data/chip_conn_testplan.hjson +++ b/hw/top_earlgrey/data/chip_conn_testplan.hjson @@ -439,6 +439,7 @@ - i2c0 clk_i - i2c1 clk_i - i2c2 clk_i + - i2c3 clk_i - pattgen clk_i - uart0 clk_i - uart1 clk_i @@ -452,6 +453,7 @@ "clkmgr_peri_clk_i2c0_clk", "clkmgr_peri_clk_i2c1_clk", "clkmgr_peri_clk_i2c2_clk", + "clkmgr_peri_clk_i2c3_clk", "clkmgr_peri_clk_pattgen_clk", "clkmgr_peri_clk_uart0_clk", "clkmgr_peri_clk_uart1_clk", @@ -905,6 +907,13 @@ tests: ["rstmgr_i2c2_d0_i2c2_rst_ni"] tags: ["conn"] } + { + name: rst_i2c3_n_d0 + desc: '''Verify rstmgr's rst_i2c3_n[1] is connected to i2c3's rst_ni.''' + stage: V2 + tests: ["rstmgr_i2c3_d0_i2c3_rst_ni"] + tags: ["conn"] + } { name: rst_lc_aon_aon desc: '''Verify rstmgr's rst_lc_aon_n[0] is connected to the following: @@ -1268,6 +1277,13 @@ tests: ["rstmgr_i2c2_d0_alert_4_rst_en"] tags: ["conn"] } + { + name: rst_en_i2c3_d0 + desc: '''Verify rstmgr's rst_en_o.i2c3[1] connects to alert_handler's lpg_rst_en[4].''' + stage: V2 + tests: ["rstmgr_i2c3_d0_alert_4_rst_en"] + tags: ["conn"] + } { name: rst_en_lc_d0 desc: '''Verify rstmgr's rst_en_o.lc[1] connects to alert_handler's lpg_rst_en[19].''' diff --git a/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson b/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson index 111538b1ed4775..bfb6f76f38d72a 100644 --- a/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson @@ -28,7 +28,8 @@ bazel: ["//sw/device/tests/pmod:i2c_host_eeprom_test"] tests: ["chip_sw_i2c_host_tx_rx", "chip_sw_i2c_host_tx_rx_idx1", - "chip_sw_i2c_host_tx_rx_idx2"] + "chip_sw_i2c_host_tx_rx_idx2", + "chip_sw_i2c_host_tx_rx_idx3"] } { name: chip_sw_i2c_device_tx_rx diff --git a/hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson b/hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson index b3288f51566da1..a74659d3ae238b 100644 --- a/hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson @@ -178,7 +178,7 @@ - Pulse the reset to the peripheral via software. - Read the resister after reset and verify it returns the reset value. - Repeat these steps for each of these software resettable peripherals: - `spi_device`, `spi_host0`, `spi_host1`, `usb`, `i2c0`, `i2c1`, `i2c2`. + `spi_device`, `spi_host0`, `spi_host1`, `usb`, `i2c0`, `i2c1`, `i2c2`, `i2c3`. Notice the two `spi_host` IPs receive two different resets, `spi_host*`. @@ -195,6 +195,8 @@ "RMA", ] features: [ + "RSTMGR.SW_RST.I2C3_ENABLE", + "RSTMGR.SW_RST.I2C3_REQUEST", "RSTMGR.SW_RST.I2C2_ENABLE", "RSTMGR.SW_RST.I2C2_REQUEST", "RSTMGR.SW_RST.I2C1_ENABLE", diff --git a/hw/top_earlgrey/data/pins_cw310.xdc b/hw/top_earlgrey/data/pins_cw310.xdc index bd5d3263009cd2..2f1aa5e4d68f68 100644 --- a/hw/top_earlgrey/data/pins_cw310.xdc +++ b/hw/top_earlgrey/data/pins_cw310.xdc @@ -79,8 +79,8 @@ set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS33 } [g set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { IOC7 }]; # P18:USRUSB_VBUS_DETECT set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOC8 }]; # W21:USB_A18 TAP Strap 0 (SAM3X):A18 set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; # M22:PMOD2_IO1 EarlGrey:GPIO (BoB):PMOD1_CSB3 -set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { IOC10 }]; # N19:PMOD2_IO3 EarlGrey:GPIO (BoB):PMOD1_CSB5 -set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { IOC11 }]; # P26:PMOD2_IO4 EarlGrey:GPIO (BoB):PMOD1_CSB6 +set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { IOC10 }]; # N19:PMOD2_IO3 EarlGrey:I2C3_SCL (BoB):PMOD1_CSB5 +set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { IOC11 }]; # P26:PMOD2_IO4 EarlGrey:I2C3_SDA (BoB):PMOD1_CSB6 set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { IOC12 }]; # P24:PMOD1_IO6 EarlGrey:GPIO (BoB):PMOD2_CSB2 ############# ## IOR bank # diff --git a/hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc b/hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc index dff7a1bbd7881d..28b731e84ab941 100644 --- a/hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc +++ b/hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc @@ -75,8 +75,8 @@ set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 DRIVE 8 } [get_ports { set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { IOC7 }]; # USRUSB_VBUS_DETECT set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 DRIVE 8 } [get_ports { IOC8 }]; # J5.18 USERIOB-18, TAP STRAP 0 set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; # PMOD2_IO1 (GPIO) -set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 DRIVE 8 } [get_ports { IOC10 }]; # J4.36 USERIOA-36, OPEN-DRAIN ALERT -set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 DRIVE 8 } [get_ports { IOC11 }]; # J4.38 USERIOA-38, OPEN-DRAIN ALERT +set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 DRIVE 8 } [get_ports { IOC10 }]; # J4.36 USERIOA-36, I2C SCL +set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 DRIVE 8 } [get_ports { IOC11 }]; # J4.38 USERIOA-38, I2C SDA set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 DRIVE 8 } [get_ports { IOC12 }]; # J4.40 USERIOA-40, OPEN-DRAIN ALERT diff --git a/hw/top_earlgrey/data/pins_cw341.xdc b/hw/top_earlgrey/data/pins_cw341.xdc index 9de5dbbc56c70e..4b889c0a649301 100644 --- a/hw/top_earlgrey/data/pins_cw341.xdc +++ b/hw/top_earlgrey/data/pins_cw341.xdc @@ -57,8 +57,8 @@ set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS18 } [get_ports { IOC6 } set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS18 } [get_ports { IOC7 }]; # EarlGrey:VBUS_DETECT set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOC8 }]; # EarlGrey:TAP_STRAP0 CW340:PB12 SAM3X:SAM_JTAGSTRAP1 set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS18 } [get_ports { IOC9 }]; # EarlGrey:GPIO -set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS18 } [get_ports { IOC10 }]; # EarlGrey:GPIO -set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS18 } [get_ports { IOC11 }]; # EarlGrey:GPIO +set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS18 } [get_ports { IOC10 }]; # EarlGrey:I2C_HOST_SCL +set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS18 } [get_ports { IOC11 }]; # EarlGrey:I2C_HOST_SDA set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS18 } [get_ports { IOC12 }]; # EarlGrey:GPIO ## IOR bank diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index bdebb8b7224678..3275e16d8abcc8 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -160,6 +160,7 @@ { name: "i2c0", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true }, { name: "i2c1", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true }, { name: "i2c2", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true }, + { name: "i2c3", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true }, ] }, @@ -276,6 +277,13 @@ reset_connections: {rst_ni: "i2c2"}, base_addr: "0x400A0000", }, + { name: "i2c3", + type: "i2c", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + reset_connections: {rst_ni: "i2c3"}, + base_addr: "0x400B0000", + }, { name: "pattgen", type: "pattgen", clock_srcs: {clk_i: "io_div4"}, @@ -1344,6 +1352,7 @@ { instance: "i2c0", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "i2c1", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "i2c2", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "i2c3", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "pattgen", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "spi_device", port: 'tpm_csb', connection: 'muxed' , pad: '' , desc: ''}, { instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''}, diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson index 6ccf799c22d920..b1c9ed4b49b5f3 100644 --- a/hw/top_earlgrey/data/xbar_peri.hjson +++ b/hw/top_earlgrey/data/xbar_peri.hjson @@ -59,6 +59,12 @@ reset: "rst_peri_ni", pipeline: false }, + { name: "i2c3", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, { name: "pattgen", type: "device", clock: "clk_peri_i", @@ -182,8 +188,8 @@ ], connections: { main: [ - "uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "pattgen", - "gpio", "spi_device", "rv_timer", + "uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "i2c3", + "pattgen", "gpio", "spi_device", "rv_timer", "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon", "otp_ctrl.core", "otp_ctrl.prim", "lc_ctrl", "sensor_ctrl_aon", "alert_handler", "ast", "sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs", diff --git a/hw/top_earlgrey/doc/datasheet.md b/hw/top_earlgrey/doc/datasheet.md index e5190ab9eda271..6761e9c9789c7a 100644 --- a/hw/top_earlgrey/doc/datasheet.md +++ b/hw/top_earlgrey/doc/datasheet.md @@ -80,7 +80,7 @@ The OpenTitan Earl Grey chip provides the following features:
  • 47x multiplexable IO pads with pad control
  • 32x GPIO (using multiplexable IO)
  • 4x UART (using multiplexable IO)
    • -
  • 3x I2C with host and device modes (using multiplexable IO)
    • +
  • 4x I2C with host and device modes (using multiplexable IO)
  • SPI device (using fixed IO) with TPM, generic, flash and passthrough modes
  • 2x SPI host (using both fixed and multiplexable IO)
  • USB device at full speed
    • diff --git a/hw/top_earlgrey/doc/design/README.md b/hw/top_earlgrey/doc/design/README.md index 37cf32ae964e4f..9f9368a730e2e2 100644 --- a/hw/top_earlgrey/doc/design/README.md +++ b/hw/top_earlgrey/doc/design/README.md @@ -406,6 +406,7 @@ For the purpose of `top_earlgrey`, the first option has been chosen to benefit s | i2c0 | i2c | 0x40080000 (regs) | | i2c1 | i2c | 0x40090000 (regs) | | i2c2 | i2c | 0x400A0000 (regs) | +| i2c3 | i2c | 0x400B0000 (regs) | | pattgen | pattgen | 0x400E0000 (regs) | | rv_timer | rv_timer | 0x40100000 (regs) | | otp_ctrl | otp_ctrl | 0x40130000 (core) | diff --git a/hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg b/hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg index f78ebab020fb29..d4833d34bb9246 100644 --- a/hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg +++ b/hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg @@ -1 +1,1679 @@ - \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/top_earlgrey/dv/autogen/rstmgr_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/rstmgr_tgl_excl.cfg index 6b1f219167873d..d081b4c9cca65e 100644 --- a/hw/top_earlgrey/dv/autogen/rstmgr_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/rstmgr_tgl_excl.cfg @@ -31,3 +31,4 @@ -node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c0_n[0] -node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c1_n[0] -node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c2_n[0] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c3_n[0] diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index fb7d17fa7d9de1..4204fb3d34a6f2 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv @@ -13,59 +13,60 @@ assign alert_if[5].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0]; assign alert_if[6].alert_tx = `CHIP_HIER.u_i2c0.alert_tx_o[0]; assign alert_if[7].alert_tx = `CHIP_HIER.u_i2c1.alert_tx_o[0]; assign alert_if[8].alert_tx = `CHIP_HIER.u_i2c2.alert_tx_o[0]; -assign alert_if[9].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0]; -assign alert_if[10].alert_tx = `CHIP_HIER.u_rv_timer.alert_tx_o[0]; -assign alert_if[11].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0]; -assign alert_if[12].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1]; -assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2]; -assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[3]; -assign alert_if[15].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[4]; -assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0]; -assign alert_if[17].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1]; -assign alert_if[18].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2]; -assign alert_if[19].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0]; -assign alert_if[20].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0]; -assign alert_if[21].alert_tx = `CHIP_HIER.u_usbdev.alert_tx_o[0]; -assign alert_if[22].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0]; -assign alert_if[23].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0]; -assign alert_if[24].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[1]; -assign alert_if[25].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0]; -assign alert_if[26].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[1]; -assign alert_if[27].alert_tx = `CHIP_HIER.u_sysrst_ctrl_aon.alert_tx_o[0]; -assign alert_if[28].alert_tx = `CHIP_HIER.u_adc_ctrl_aon.alert_tx_o[0]; -assign alert_if[29].alert_tx = `CHIP_HIER.u_pwm_aon.alert_tx_o[0]; -assign alert_if[30].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0]; -assign alert_if[31].alert_tx = `CHIP_HIER.u_aon_timer_aon.alert_tx_o[0]; -assign alert_if[32].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0]; -assign alert_if[33].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1]; -assign alert_if[34].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; -assign alert_if[35].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; -assign alert_if[36].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; -assign alert_if[37].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; -assign alert_if[38].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; -assign alert_if[39].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[4]; -assign alert_if[40].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0]; -assign alert_if[41].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; -assign alert_if[42].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; -assign alert_if[43].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; -assign alert_if[44].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; -assign alert_if[45].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; -assign alert_if[46].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; -assign alert_if[47].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[48].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; -assign alert_if[49].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; -assign alert_if[50].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; -assign alert_if[51].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; -assign alert_if[52].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1]; -assign alert_if[53].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; -assign alert_if[54].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; -assign alert_if[55].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; -assign alert_if[56].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1]; -assign alert_if[57].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; -assign alert_if[58].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1]; -assign alert_if[59].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; -assign alert_if[60].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0]; -assign alert_if[61].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0]; -assign alert_if[62].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1]; -assign alert_if[63].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2]; -assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3]; +assign alert_if[9].alert_tx = `CHIP_HIER.u_i2c3.alert_tx_o[0]; +assign alert_if[10].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0]; +assign alert_if[11].alert_tx = `CHIP_HIER.u_rv_timer.alert_tx_o[0]; +assign alert_if[12].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0]; +assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1]; +assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2]; +assign alert_if[15].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[3]; +assign alert_if[16].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[4]; +assign alert_if[17].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0]; +assign alert_if[18].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1]; +assign alert_if[19].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2]; +assign alert_if[20].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0]; +assign alert_if[21].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0]; +assign alert_if[22].alert_tx = `CHIP_HIER.u_usbdev.alert_tx_o[0]; +assign alert_if[23].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0]; +assign alert_if[24].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0]; +assign alert_if[25].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[1]; +assign alert_if[26].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0]; +assign alert_if[27].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[1]; +assign alert_if[28].alert_tx = `CHIP_HIER.u_sysrst_ctrl_aon.alert_tx_o[0]; +assign alert_if[29].alert_tx = `CHIP_HIER.u_adc_ctrl_aon.alert_tx_o[0]; +assign alert_if[30].alert_tx = `CHIP_HIER.u_pwm_aon.alert_tx_o[0]; +assign alert_if[31].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0]; +assign alert_if[32].alert_tx = `CHIP_HIER.u_aon_timer_aon.alert_tx_o[0]; +assign alert_if[33].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0]; +assign alert_if[34].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1]; +assign alert_if[35].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; +assign alert_if[36].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; +assign alert_if[37].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; +assign alert_if[38].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; +assign alert_if[39].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; +assign alert_if[40].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[4]; +assign alert_if[41].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0]; +assign alert_if[42].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; +assign alert_if[43].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[44].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[45].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[46].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[47].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; +assign alert_if[48].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[49].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[50].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; +assign alert_if[51].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; +assign alert_if[52].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[53].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1]; +assign alert_if[54].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; +assign alert_if[55].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; +assign alert_if[56].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[57].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1]; +assign alert_if[58].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[59].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1]; +assign alert_if[60].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[61].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0]; +assign alert_if[62].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0]; +assign alert_if[63].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1]; +assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2]; +assign alert_if[65].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3]; diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index 947a20a6a1d427..f915eab7327c3a 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv @@ -71,6 +71,7 @@ tl_if uart3_tl_if(clk_io_div4, rst_n); tl_if i2c0_tl_if(clk_io_div4, rst_n); tl_if i2c1_tl_if(clk_io_div4, rst_n); tl_if i2c2_tl_if(clk_io_div4, rst_n); +tl_if i2c3_tl_if(clk_io_div4, rst_n); tl_if pattgen_tl_if(clk_io_div4, rst_n); tl_if pwm_aon_tl_if(clk_io_div4, rst_n); tl_if gpio_tl_if(clk_io_div4, rst_n); @@ -153,6 +154,7 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(i2c0, i2c0, tl) `DRIVE_CHIP_TL_DEVICE_IF(i2c1, i2c1, tl) `DRIVE_CHIP_TL_DEVICE_IF(i2c2, i2c2, tl) + `DRIVE_CHIP_TL_DEVICE_IF(i2c3, i2c3, tl) `DRIVE_CHIP_TL_DEVICE_IF(pattgen, pattgen, tl) `DRIVE_CHIP_TL_DEVICE_IF(pwm_aon, pwm_aon, tl) `DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl) diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index ff71673aca7488..07fc3918041460 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv @@ -97,6 +97,9 @@ tl_device_t xbar_devices[$] = '{ '{"i2c2", '{ '{32'h400a0000, 32'h400a007f} }}, + '{"i2c3", '{ + '{32'h400b0000, 32'h400b007f} + }}, '{"pattgen", '{ '{32'h400e0000, 32'h400e003f} }}, @@ -179,6 +182,7 @@ tl_host_t xbar_hosts[$] = '{ "i2c0", "i2c1", "i2c2", + "i2c3", "pattgen", "gpio", "spi_device", @@ -231,6 +235,7 @@ tl_host_t xbar_hosts[$] = '{ "i2c0", "i2c1", "i2c2", + "i2c3", "pattgen", "gpio", "spi_device", diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg index 90eee5db4256d9..694caf8a3463b2 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg @@ -133,6 +133,10 @@ -node tb.dut*.u_i2c2 tl_*i.a_address[18:18] -node tb.dut*.u_i2c2 tl_*i.a_address[29:20] -node tb.dut*.u_i2c2 tl_*i.a_address[31:31] +-node tb.dut*.u_i2c3 tl_*i.a_address[15:7] +-node tb.dut*.u_i2c3 tl_*i.a_address[18:18] +-node tb.dut*.u_i2c3 tl_*i.a_address[29:20] +-node tb.dut*.u_i2c3 tl_*i.a_address[31:31] -node tb.dut*.u_pattgen tl_*i.a_address[16:6] -node tb.dut*.u_pattgen tl_*i.a_address[29:20] -node tb.dut*.u_pattgen tl_*i.a_address[31:31] diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index 1ca08184334493..58964a6fe2431d 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -695,6 +695,13 @@ run_opts: ["+i2c_idx=2"] en_run_modes: ["sw_test_mode_test_rom"] } + { + name: chip_sw_i2c_host_tx_rx_idx3 + uvm_test_seq: chip_sw_i2c_host_tx_rx_vseq + sw_images: ["//sw/device/tests/sim_dv:i2c_host_tx_rx_test:1:new_rules"] + run_opts: ["+i2c_idx=3"] + en_run_modes: ["sw_test_mode_test_rom"] + } { name: chip_sw_i2c_device_tx_rx uvm_test_seq: chip_sw_i2c_device_tx_rx_vseq diff --git a/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg b/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg index 4907dc77685c27..70a1e96984d733 100644 --- a/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg +++ b/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg @@ -16,6 +16,7 @@ +node tb.dut.top_earlgrey.u_i2c0 *tl_* +node tb.dut.top_earlgrey.u_i2c1 *tl_* +node tb.dut.top_earlgrey.u_i2c2 *tl_* ++node tb.dut.top_earlgrey.u_i2c3 *tl_* +node tb.dut.top_earlgrey.u_pattgen *tl_* +node tb.dut.top_earlgrey.u_rv_timer *tl_* +node tb.dut.top_earlgrey.u_usbdev *tl_* diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index 96e5b30936ed11..e8e28d2fac79dd 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv @@ -14,6 +14,7 @@ parameter string LIST_OF_ALERTS[] = { "i2c0_fatal_fault", "i2c1_fatal_fault", "i2c2_fatal_fault", + "i2c3_fatal_fault", "pattgen_fatal_fault", "rv_timer_fatal_fault", "otp_ctrl_fatal_macro_error", @@ -72,4 +73,4 @@ parameter string LIST_OF_ALERTS[] = { "rv_core_ibex_recov_hw_err" }; -parameter uint NUM_ALERTS = 65; +parameter uint NUM_ALERTS = 66; diff --git a/hw/top_earlgrey/dv/env/chip_common_pkg.sv b/hw/top_earlgrey/dv/env/chip_common_pkg.sv index 37d379585378d2..0168b5b23d643b 100644 --- a/hw/top_earlgrey/dv/env/chip_common_pkg.sv +++ b/hw/top_earlgrey/dv/env/chip_common_pkg.sv @@ -11,7 +11,7 @@ package chip_common_pkg; parameter dv_utils_pkg::uint NUM_GPIOS = 32; parameter dv_utils_pkg::uint NUM_UARTS = 4; parameter dv_utils_pkg::uint NUM_SPI_HOSTS = 2; - parameter dv_utils_pkg::uint NUM_I2CS = 3; + parameter dv_utils_pkg::uint NUM_I2CS = 4; parameter dv_utils_pkg::uint NUM_PWM_CHANNELS = pwm_reg_pkg::NOutputs; parameter dv_utils_pkg::uint NUM_PATTGEN_CH = pattgen_agent_pkg::NUM_PATTGEN_CHANNELS; diff --git a/hw/top_earlgrey/dv/env/chip_if.sv b/hw/top_earlgrey/dv/env/chip_if.sv index 252da1b18e4a38..4c5f277041303f 100644 --- a/hw/top_earlgrey/dv/env/chip_if.sv +++ b/hw/top_earlgrey/dv/env/chip_if.sv @@ -529,21 +529,29 @@ interface chip_if; // Functional (muxed) interface: I2Cs. bit [NUM_I2CS-1:0] __enable_i2c = {NUM_I2CS{1'b0}}; // Internal signal. - // {ioa7, ioa8}, {iob9, iob10}, {iob11, iob12} are the i2c connections + // {ioa7, ioa8}, {iob9, iob10}, {iob11, iob12}, {ioc10, ioc11} are the i2c connections localparam int AssignedI2cSclIos [NUM_I2CS] = { top_earlgrey_pkg::MioPadIoa8, top_earlgrey_pkg::MioPadIob9, - top_earlgrey_pkg::MioPadIob11 + top_earlgrey_pkg::MioPadIob11, + top_earlgrey_pkg::MioPadIoc10 }; localparam int AssignedI2cSdaIos [NUM_I2CS] = { top_earlgrey_pkg::MioPadIoa7, top_earlgrey_pkg::MioPadIob10, - top_earlgrey_pkg::MioPadIob12 + top_earlgrey_pkg::MioPadIob12, + top_earlgrey_pkg::MioPadIoc11 }; // This part unfortunately has to be hardcoded since the macro cannot interpret a genvar. - wire [NUM_I2CS-1:0]i2c_clks = {`I2C_HIER(2).clk_i, `I2C_HIER(1).clk_i, `I2C_HIER(0).clk_i}; - wire [NUM_I2CS-1:0]i2c_rsts = {`I2C_HIER(2).rst_ni, `I2C_HIER(1).rst_ni, `I2C_HIER(0).rst_ni}; + wire [NUM_I2CS-1:0]i2c_clks = {`I2C_HIER(3).clk_i, + `I2C_HIER(2).clk_i, + `I2C_HIER(1).clk_i, + `I2C_HIER(0).clk_i}; + wire [NUM_I2CS-1:0]i2c_rsts = {`I2C_HIER(3).rst_ni, + `I2C_HIER(2).rst_ni, + `I2C_HIER(1).rst_ni, + `I2C_HIER(0).rst_ni}; for (genvar i = 0; i < NUM_I2CS; i++) begin : gen_i2c_if i2c_if i2c_if( @@ -1006,6 +1014,7 @@ interface chip_if; PeripheralI2c0: path = {path, ".", `DV_STRINGIFY(`I2C_HIER(0))}; PeripheralI2c1: path = {path, ".", `DV_STRINGIFY(`I2C_HIER(1))}; PeripheralI2c2: path = {path, ".", `DV_STRINGIFY(`I2C_HIER(2))}; + PeripheralI2c3: path = {path, ".", `DV_STRINGIFY(`I2C_HIER(3))}; PeripheralKeymgr: path = {path, ".", `DV_STRINGIFY(`KEYMGR_HIER)}; PeripheralKmac: path = {path, ".", `DV_STRINGIFY(`KMAC_HIER)}; PeripheralLcCtrl: path = {path, ".", `DV_STRINGIFY(`LC_CTRL_HIER)}; diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv index 6a6762eeaaced5..69e0a9d2f8ae3c 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv @@ -31,6 +31,7 @@ class chip_sw_all_escalation_resets_vseq extends chip_sw_base_vseq; '{"*i2c0*prim_reg_we_check*", TopEarlgreyAlertIdI2c0FatalFault}, '{"*i2c1*prim_reg_we_check*", TopEarlgreyAlertIdI2c1FatalFault}, '{"*i2c2*prim_reg_we_check*", TopEarlgreyAlertIdI2c2FatalFault}, + '{"*i2c3*prim_reg_we_check*", TopEarlgreyAlertIdI2c3FatalFault}, '{"*keymgr*prim_reg_we_check*", TopEarlgreyAlertIdKeymgrFatalFaultErr}, '{"*kmac*prim_reg_we_check*", TopEarlgreyAlertIdKmacFatalFaultErr}, // TODO TopEarlgreyAlertIdLcCtrlFatalProgError: done in sw/device/tests/sim_dv/lc_ctrl_program_error.c? diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv index 161f14b8e46b0f..ff40240877ea1e 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv @@ -3,8 +3,8 @@ // SPDX-License-Identifier: Apache-2.0 // By default this test will use a randomly selected instance i2c_idx. -// To make a dedicated test for instance i, where i is in {0,1,2}, the test -// shuld run with an option: +// To make a dedicated test for instance i, where i is in [0, NUM_I2CS), the +// test should run with an option: // run_opts: ["+i2c_idx=i"] class chip_sw_i2c_device_tx_rx_vseq extends chip_sw_i2c_tx_rx_vseq; diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv index 43eb3899669a28..96e44de6d5b710 100644 --- a/hw/top_earlgrey/dv/tb/tb.sv +++ b/hw/top_earlgrey/dv/tb/tb.sv @@ -640,6 +640,7 @@ module tb; $assertoff(0, dut.top_earlgrey.u_i2c0); $assertoff(0, dut.top_earlgrey.u_i2c1); $assertoff(0, dut.top_earlgrey.u_i2c2); + $assertoff(0, dut.top_earlgrey.u_i2c3); $assertoff(0, dut.top_earlgrey.u_pinmux_aon); $assertoff(0, dut.top_earlgrey.u_spi_device); $assertoff(0, dut.top_earlgrey.u_spi_host0); @@ -656,6 +657,7 @@ module tb; $asserton(0, dut.top_earlgrey.u_i2c0); $asserton(0, dut.top_earlgrey.u_i2c1); $asserton(0, dut.top_earlgrey.u_i2c2); + $asserton(0, dut.top_earlgrey.u_i2c3); $asserton(0, dut.top_earlgrey.u_pinmux_aon); $asserton(0, dut.top_earlgrey.u_spi_device); $asserton(0, dut.top_earlgrey.u_spi_host0); diff --git a/hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv b/hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv index 86b5a74823bbbc..8f1ca2dcd15988 100644 --- a/hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv +++ b/hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv @@ -21,6 +21,7 @@ CONNECTION, CLKMGR_PERI_CLK_SPI_HOST1_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.c CONNECTION, CLKMGR_PERI_CLK_I2C0_CLK, top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri, top_earlgrey.u_i2c0, clk_i CONNECTION, CLKMGR_PERI_CLK_I2C1_CLK, top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri, top_earlgrey.u_i2c1, clk_i CONNECTION, CLKMGR_PERI_CLK_I2C2_CLK, top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri, top_earlgrey.u_i2c2, clk_i +CONNECTION, CLKMGR_PERI_CLK_I2C3_CLK, top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri, top_earlgrey.u_i2c3, clk_i CONNECTION, CLKMGR_PERI_CLK_PATTGEN_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.clk_io_div4_peri, top_earlgrey.u_pattgen, clk_i diff --git a/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv b/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv index 048f53be1f5f5e..dcbe81d1c962e2 100644 --- a/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv +++ b/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv @@ -18,6 +18,7 @@ CONNECTION, RSTMGR_SPI_DEVICE_D0_SPI_DEVICE_RST_NI, top_earlgrey.u_rstmgr_aon, r CONNECTION, RSTMGR_I2C0_D0_I2C0_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_i2c0_n[1], top_earlgrey.u_i2c0, rst_ni CONNECTION, RSTMGR_I2C1_D0_I2C1_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_i2c1_n[1], top_earlgrey.u_i2c1, rst_ni CONNECTION, RSTMGR_I2C2_D0_I2C2_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_i2c2_n[1], top_earlgrey.u_i2c2, rst_ni +CONNECTION, RSTMGR_I2C3_D0_I2C3_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_i2c3_n[1], top_earlgrey.u_i2c3, rst_ni CONNECTION, RSTMGR_LC_IO_DIV4_D0_PATTGEN_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_io_div4_n[1], top_earlgrey.u_pattgen, rst_ni CONNECTION, RSTMGR_LC_IO_DIV4_D0_RV_TIMER_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_io_div4_n[1], top_earlgrey.u_rv_timer, rst_ni CONNECTION, RSTMGR_LC_IO_DIV4_D0_OTP_CTRL_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_io_div4_n[1], top_earlgrey.u_otp_ctrl, rst_ni diff --git a/hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv b/hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv index 57ca9dd6ecf625..80e3bd8b651327 100644 --- a/hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv +++ b/hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv @@ -14,6 +14,7 @@ CONNECTION, RSTMGR_SPI_DEVICE_D0_ALERT_1_RST_EN, top_earlgrey.u_rstmgr_aon, rst_ CONNECTION, RSTMGR_I2C0_D0_ALERT_2_RST_EN, top_earlgrey.u_rstmgr_aon, rst_en_o.i2c0[1], top_earlgrey.u_alert_handler, lpg_rst_en_i[2] CONNECTION, RSTMGR_I2C1_D0_ALERT_3_RST_EN, top_earlgrey.u_rstmgr_aon, rst_en_o.i2c1[1], top_earlgrey.u_alert_handler, lpg_rst_en_i[3] CONNECTION, RSTMGR_I2C2_D0_ALERT_4_RST_EN, top_earlgrey.u_rstmgr_aon, rst_en_o.i2c2[1], top_earlgrey.u_alert_handler, lpg_rst_en_i[4] +CONNECTION, RSTMGR_I2C3_D0_ALERT_4_RST_EN, top_earlgrey.u_rstmgr_aon, rst_en_o.i2c3[1], top_earlgrey.u_alert_handler, lpg_rst_en_i[4] CONNECTION, RSTMGR_LC_IO_DIV4_D0_ALERT_5_RST_EN, top_earlgrey.u_rstmgr_aon, rst_en_o.lc_io_div4[1], top_earlgrey.u_alert_handler, lpg_rst_en_i[5] CONNECTION, RSTMGR_LC_IO_DIV4_D0_ALERT_6_RST_EN, top_earlgrey.u_rstmgr_aon, rst_en_o.lc_io_div4[1], top_earlgrey.u_alert_handler, lpg_rst_en_i[6] CONNECTION, RSTMGR_SPI_HOST0_D0_ALERT_7_RST_EN, top_earlgrey.u_rstmgr_aon, rst_en_o.spi_host0[1], top_earlgrey.u_alert_handler, lpg_rst_en_i[7] diff --git a/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc b/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc index c8fe774ef738a6..e4a73e3f2bd34f 100644 --- a/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc +++ b/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc @@ -355,6 +355,8 @@ abstract_port -ports "sns_clks_i[clk_io_powerup]" -ignore -comment "hanging path abstract_port -ports "sns_clks_i[clk_main_powerup]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_aon_powerup]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_io_div4_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c3_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c3_n][1]" -ignore -comment "hanging path" abstract_port -ports "sns_rsts_i[rst_i2c2_n][0]" -ignore -comment "hanging path" abstract_port -ports "sns_rsts_i[rst_i2c2_n][1]" -ignore -comment "hanging path" abstract_port -ports "sns_rsts_i[rst_i2c1_n][0]" -ignore -comment "hanging path" diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson index 3fe1512f43f6fb..e04efe90d46419 100644 --- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson +++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson @@ -342,13 +342,13 @@ { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", - default: "57", + default: "59", local: "true" }, { name: "NMioPeriphOut", desc: "Number of muxed peripheral outputs", type: "int", - default: "75", + default: "77", local: "true" }, { name: "NMioPads", diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md index 1b7d81e9e1dad1..be91da8c709112 100644 --- a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md +++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md @@ -131,6 +131,8 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

    i2c1_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c1Scl / kTopEarlgreyPinmuxPeripheralInI2c1Scl

    |

    | |

    i2c2_sda

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c2Sda / kTopEarlgreyPinmuxPeripheralInI2c2Sda

    |

    | |

    i2c2_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c2Scl / kTopEarlgreyPinmuxPeripheralInI2c2Scl

    |

    | +|

    i2c3_sda

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c3Sda / kTopEarlgreyPinmuxPeripheralInI2c3Sda

    |

    | +|

    i2c3_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c3Scl / kTopEarlgreyPinmuxPeripheralInI2c3Scl

    |

    | |

    spi_host1_sd[0]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd0 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0

    |

    | |

    spi_host1_sd[1]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd1 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1

    |

    | |

    spi_host1_sd[2]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd2 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2

    |

    | diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md index d037f12afd3a03..42b0d30719b37d 100644 --- a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md +++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md @@ -135,6 +135,8 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

    i2c1_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c1Scl / kTopEarlgreyPinmuxPeripheralInI2c1Scl

    |

    | |

    i2c2_sda

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c2Sda / kTopEarlgreyPinmuxPeripheralInI2c2Sda

    |

    | |

    i2c2_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c2Scl / kTopEarlgreyPinmuxPeripheralInI2c2Scl

    |

    | +|

    i2c3_sda

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c3Sda / kTopEarlgreyPinmuxPeripheralInI2c3Sda

    |

    | +|

    i2c3_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c3Scl / kTopEarlgreyPinmuxPeripheralInI2c3Scl

    |

    | |

    spi_host1_sd[0]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd0 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0

    |

    | |

    spi_host1_sd[1]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd1 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1

    |

    | |

    spi_host1_sd[2]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd2 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2

    |

    | diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw340.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw340.md index 542720388d924f..c5bcc87ff7ad0e 100644 --- a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw340.md +++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw340.md @@ -134,6 +134,8 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

    i2c1_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c1Scl / kTopEarlgreyPinmuxPeripheralInI2c1Scl

    |

    | |

    i2c2_sda

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c2Sda / kTopEarlgreyPinmuxPeripheralInI2c2Sda

    |

    | |

    i2c2_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c2Scl / kTopEarlgreyPinmuxPeripheralInI2c2Scl

    |

    | +|

    i2c3_sda

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c3Sda / kTopEarlgreyPinmuxPeripheralInI2c3Sda

    |

    | +|

    i2c3_scl

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselI2c3Scl / kTopEarlgreyPinmuxPeripheralInI2c3Scl

    |

    | |

    spi_host1_sd[0]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd0 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0

    |

    | |

    spi_host1_sd[1]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd1 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1

    |

    | |

    spi_host1_sd[2]

    |

    muxed

    |

    -

    |

    kTopEarlgreyPinmuxOutselSpiHost1Sd2 / kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2

    |

    | diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv index 16b3dae2e8e318..54b235b1a5866b 100644 --- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv +++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv @@ -8,8 +8,8 @@ package pinmux_reg_pkg; // Param list parameter int AttrDw = 13; - parameter int NMioPeriphIn = 57; - parameter int NMioPeriphOut = 75; + parameter int NMioPeriphIn = 59; + parameter int NMioPeriphOut = 77; parameter int NMioPads = 47; parameter int NDioPads = 16; parameter int NWkupDetect = 8; @@ -243,8 +243,8 @@ package pinmux_reg_pkg; // Register -> HW type typedef struct packed { - pinmux_reg2hw_alert_test_reg_t alert_test; // [2478:2477] - pinmux_reg2hw_mio_periph_insel_mreg_t [56:0] mio_periph_insel; // [2476:2135] + pinmux_reg2hw_alert_test_reg_t alert_test; // [2490:2489] + pinmux_reg2hw_mio_periph_insel_mreg_t [58:0] mio_periph_insel; // [2488:2135] pinmux_reg2hw_mio_outsel_mreg_t [46:0] mio_outsel; // [2134:1806] pinmux_reg2hw_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1805:772] pinmux_reg2hw_dio_pad_attr_mreg_t [15:0] dio_pad_attr; // [771:420] @@ -329,516 +329,520 @@ package pinmux_reg_pkg; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET = 12'h dc; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET = 12'h e0; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET = 12'h e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 100; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 104; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 108; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 10c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 110; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 114; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 118; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 11c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 120; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 124; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 128; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 12c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 130; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 134; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 138; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 13c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 140; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 144; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 148; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 14c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 150; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 154; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 158; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 15c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 160; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 164; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 168; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 16c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 170; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 174; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 178; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 17c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 180; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 184; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 188; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 18c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 190; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 194; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 198; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 19c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 1f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 1f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 1f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 1fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 200; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 204; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 208; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 20c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 210; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 214; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 218; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 21c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 220; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 224; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 228; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 22c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 230; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 234; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 238; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 23c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 240; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 244; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 248; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 24c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 250; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 254; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 258; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 25c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 260; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 264; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 268; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 26c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 270; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 274; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 278; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 27c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 280; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 284; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 288; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 28c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 290; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 294; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 298; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 29c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 2e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 2ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 2f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 2f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 2f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 2fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 300; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 304; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 308; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 30c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 310; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 314; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 318; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 31c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 320; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 324; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 328; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 32c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 330; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 334; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 338; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 33c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 340; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 344; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 348; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 34c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 350; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 354; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 358; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 35c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 360; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 364; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 368; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 36c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 370; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 374; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 378; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 37c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 380; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 384; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 388; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 38c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 390; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 394; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 398; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 39c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 3e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 3ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 3f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 3f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 3f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 3fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 400; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 404; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 408; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 40c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 410; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 414; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 418; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 41c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 420; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 424; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 428; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 42c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 430; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 434; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 438; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 43c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 440; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 444; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 448; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 44c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 450; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 454; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 458; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 45c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 460; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 464; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 468; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 46c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 470; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 474; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 478; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 47c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 480; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 484; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 488; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 48c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 490; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 494; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 498; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 49c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4bc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4c0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4c4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4c8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 4f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 4f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 4f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 4fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 500; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 504; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 508; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 50c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 510; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 514; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 518; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 51c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 520; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 524; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 528; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 52c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 530; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 534; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 538; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 53c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 540; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 544; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 548; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 54c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 550; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 554; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 558; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 55c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 560; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 564; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 568; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 56c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 570; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 574; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 578; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 57c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 580; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 584; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 588; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 58c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 590; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 594; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 598; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 59c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 5d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 5d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 5dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 5e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 5e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 5e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 5ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 5f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 5f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 5f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 5fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 600; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 604; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 608; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 60c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 610; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 614; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 618; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 61c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 620; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 624; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 628; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 62c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 630; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 634; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 638; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 63c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 640; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 644; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 648; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 64c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 650; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 654; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 658; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 65c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 660; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 664; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 668; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 66c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 670; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 674; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 678; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 67c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 680; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 684; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 688; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 68c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 690; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 694; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 698; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 69c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 6d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 6d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 6dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 6e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 6e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 6e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 6ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 6f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 6f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 6f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 6fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 700; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 704; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 708; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 70c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 710; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 714; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 718; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 71c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 720; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 724; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 728; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 72c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 730; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 734; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 738; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 73c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 740; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 744; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 748; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 74c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 750; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 754; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 758; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 75c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 760; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 764; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 768; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 76c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 770; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 774; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 778; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 77c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 780; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 784; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 788; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 78c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 790; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 794; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 798; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 79c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7a0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7a4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7a8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7ac; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7b0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7b4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 7bc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 7c0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 7c4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 7c8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 7cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 7d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 7d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 7d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 7dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 7e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 7e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 7e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 7ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 7f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 7f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 7f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 7fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 800; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 804; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 808; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 80c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 810; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 814; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 818; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 81c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 820; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 824; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 828; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 82c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 830; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 834; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 838; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 83c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 840; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 844; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 848; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 84c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 850; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 854; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 858; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 85c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 860; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 864; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 868; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 86c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 870; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 874; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 878; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 87c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 880; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 884; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 888; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 88c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 890; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 894; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 898; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 89c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 8a0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 8a4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 8a8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 8ac; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 8b0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 8b4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 8b8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 8bc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 8c0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 8c4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 8c8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 8cc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 8d0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 8d4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 8d8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 8dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET = 12'h e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET = 12'h ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h 100; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h 104; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 108; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 10c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 110; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 114; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 118; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 11c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 120; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 124; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 128; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 12c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 130; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 134; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 138; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 13c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 140; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 144; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 148; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 14c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 150; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 154; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 158; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 15c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 160; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 164; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 168; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 16c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 170; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 174; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 178; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 17c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 180; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 184; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 188; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 18c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 190; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 194; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 198; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 19c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 1a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 1a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_57_OFFSET = 12'h 1d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_58_OFFSET = 12'h 1d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 200; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 204; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 208; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 20c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 210; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 214; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 218; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 21c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 220; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 224; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 228; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 22c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 230; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 234; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 238; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 23c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 240; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 244; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 248; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 24c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 250; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 254; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 258; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 25c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 260; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 264; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 268; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 26c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 270; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 274; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 278; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 27c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 280; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 284; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 288; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 28c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 290; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 294; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 298; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 29c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 300; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 304; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 308; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 30c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 310; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 314; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 318; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 31c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 320; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 324; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 344; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 348; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 34c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 350; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 354; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 358; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 35c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 360; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 364; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 368; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 36c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 370; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 374; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 378; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 37c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 380; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 400; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 404; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 408; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 40c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 410; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 414; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 418; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 41c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 420; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 424; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 428; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 42c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 430; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 434; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 438; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 43c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 440; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 444; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 448; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 44c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 450; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 454; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 458; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 45c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 460; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 464; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 468; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 46c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 470; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 474; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 478; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 47c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 480; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 484; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 488; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 48c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 490; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 494; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 498; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 49c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 500; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 504; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 508; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 50c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 510; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 514; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 518; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 51c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 520; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 524; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 528; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 52c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 530; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 534; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 538; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 53c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 540; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 544; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 548; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 54c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 550; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 554; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 558; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 55c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 560; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 564; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 568; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 56c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 570; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 574; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 578; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 57c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 580; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 584; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 588; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 58c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 590; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 594; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 598; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 59c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 600; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 604; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 608; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 60c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 610; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 614; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 618; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 61c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 620; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 624; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 628; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 62c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 630; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 634; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 638; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 63c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 640; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 644; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 648; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 64c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 650; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 654; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 658; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 65c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 660; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 664; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 668; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 66c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 670; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 674; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 678; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 67c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 680; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 684; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 688; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 68c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 690; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 694; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 698; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 69c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 6a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 6a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 6a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 6ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 6e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 6e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 6ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 6f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 6f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 6f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 6fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 700; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 704; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 708; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 70c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 710; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 714; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 718; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 71c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 720; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 724; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 728; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 72c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 730; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 734; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 738; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 73c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 740; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 744; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 748; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 74c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 750; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 754; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 758; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 75c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 760; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 764; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 768; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 76c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 770; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 774; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 778; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 77c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 780; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 784; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 788; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 78c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 790; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 794; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 798; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 79c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 7a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 7a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 7a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 7ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 7cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 7d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 7d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 7d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 7dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 7e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 7e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 7e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 7ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 7f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 7f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 7f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 7fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 800; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 804; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 808; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 80c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 810; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 814; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 818; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 81c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 820; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 824; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 828; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 82c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 830; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 834; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 838; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 83c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 840; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 844; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 848; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 84c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 850; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 854; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 858; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 85c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 860; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 864; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 868; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 86c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 870; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 874; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 878; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 87c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 880; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 884; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 888; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 88c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 890; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 894; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 898; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 89c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 8a0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 8a4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 8a8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 8ac; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 8b0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 8b4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 8b8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 8bc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 8c0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 8c4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 8c8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 8cc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 8d0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 8d4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 8d8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 8dc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 8e0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 8e4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 8e8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 8ec; // Reset values for hwext registers and their fields parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0; @@ -1534,6 +1538,8 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_REGWEN_54, PINMUX_MIO_PERIPH_INSEL_REGWEN_55, PINMUX_MIO_PERIPH_INSEL_REGWEN_56, + PINMUX_MIO_PERIPH_INSEL_REGWEN_57, + PINMUX_MIO_PERIPH_INSEL_REGWEN_58, PINMUX_MIO_PERIPH_INSEL_0, PINMUX_MIO_PERIPH_INSEL_1, PINMUX_MIO_PERIPH_INSEL_2, @@ -1591,6 +1597,8 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_54, PINMUX_MIO_PERIPH_INSEL_55, PINMUX_MIO_PERIPH_INSEL_56, + PINMUX_MIO_PERIPH_INSEL_57, + PINMUX_MIO_PERIPH_INSEL_58, PINMUX_MIO_OUTSEL_REGWEN_0, PINMUX_MIO_OUTSEL_REGWEN_1, PINMUX_MIO_OUTSEL_REGWEN_2, @@ -2047,7 +2055,7 @@ package pinmux_reg_pkg; } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [568] = '{ + parameter logic [3:0] PINMUX_PERMIT [572] = '{ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 @@ -2106,516 +2114,520 @@ package pinmux_reg_pkg; 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_REGWEN_54 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_REGWEN_55 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_REGWEN_56 - 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_0 - 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_1 - 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_2 - 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_3 - 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_4 - 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_5 - 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_6 - 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_7 - 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_8 - 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_9 - 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_10 - 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_11 - 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_12 - 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_13 - 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_14 - 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_15 - 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_16 - 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_17 - 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_18 - 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_19 - 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_20 - 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_21 - 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_22 - 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_23 - 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_24 - 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_25 - 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_26 - 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_27 - 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_28 - 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_29 - 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_30 - 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_31 - 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_32 - 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_33 - 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_34 - 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_35 - 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_36 - 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_37 - 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_38 - 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_39 - 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_40 - 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_41 - 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_42 - 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_43 - 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_44 - 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_45 - 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_46 - 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_47 - 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_48 - 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_49 - 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_50 - 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_51 - 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_52 - 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_53 - 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_54 - 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_55 - 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_56 - 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_0 - 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_1 - 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_2 - 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_3 - 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_4 - 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_5 - 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_6 - 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_7 - 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_8 - 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_9 - 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_10 - 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_11 - 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_12 - 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_13 - 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_14 - 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_15 - 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_16 - 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_17 - 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_18 - 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_19 - 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_20 - 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_21 - 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_22 - 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_23 - 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_24 - 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_25 - 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_26 - 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_27 - 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_28 - 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_29 - 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_30 - 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_31 - 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_32 - 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_33 - 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_34 - 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_35 - 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_36 - 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_37 - 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_38 - 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_39 - 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_40 - 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_41 - 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_42 - 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_43 - 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_44 - 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_45 - 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_46 - 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_0 - 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_1 - 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_2 - 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_3 - 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_4 - 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_5 - 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_6 - 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_7 - 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_8 - 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_9 - 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_10 - 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_11 - 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_12 - 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_13 - 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_14 - 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_15 - 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_16 - 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_17 - 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_18 - 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_19 - 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_20 - 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_21 - 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_22 - 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_23 - 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_24 - 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_25 - 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_26 - 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_27 - 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_28 - 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_29 - 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_30 - 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_31 - 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_32 - 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_33 - 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_34 - 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_35 - 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_36 - 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_37 - 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_38 - 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_39 - 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_40 - 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_41 - 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_42 - 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_43 - 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_44 - 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_45 - 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_46 - 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[212] PINMUX_MIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_15 - 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_16 - 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_17 - 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_18 - 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_19 - 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_20 - 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_21 - 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_22 - 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_23 - 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_24 - 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_25 - 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_26 - 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_27 - 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_28 - 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_29 - 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_30 - 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_31 - 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_32 - 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_33 - 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_34 - 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_35 - 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_36 - 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_37 - 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_38 - 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_39 - 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_40 - 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_41 - 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_42 - 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_43 - 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_44 - 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_45 - 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_46 - 4'b 0111, // index[256] PINMUX_MIO_PAD_ATTR_0 - 4'b 0111, // index[257] PINMUX_MIO_PAD_ATTR_1 - 4'b 0111, // index[258] PINMUX_MIO_PAD_ATTR_2 - 4'b 0111, // index[259] PINMUX_MIO_PAD_ATTR_3 - 4'b 0111, // index[260] PINMUX_MIO_PAD_ATTR_4 - 4'b 0111, // index[261] PINMUX_MIO_PAD_ATTR_5 - 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_6 - 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_7 - 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_8 - 4'b 0111, // index[265] PINMUX_MIO_PAD_ATTR_9 - 4'b 0111, // index[266] PINMUX_MIO_PAD_ATTR_10 - 4'b 0111, // index[267] PINMUX_MIO_PAD_ATTR_11 - 4'b 0111, // index[268] PINMUX_MIO_PAD_ATTR_12 - 4'b 0111, // index[269] PINMUX_MIO_PAD_ATTR_13 - 4'b 0111, // index[270] PINMUX_MIO_PAD_ATTR_14 - 4'b 0111, // index[271] PINMUX_MIO_PAD_ATTR_15 - 4'b 0111, // index[272] PINMUX_MIO_PAD_ATTR_16 - 4'b 0111, // index[273] PINMUX_MIO_PAD_ATTR_17 - 4'b 0111, // index[274] PINMUX_MIO_PAD_ATTR_18 - 4'b 0111, // index[275] PINMUX_MIO_PAD_ATTR_19 - 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_20 - 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_21 - 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_22 - 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_23 - 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_24 - 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_25 - 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_26 - 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_27 - 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_28 - 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_29 - 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_30 - 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_31 - 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_32 - 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_33 - 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_34 - 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_35 - 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_36 - 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_37 - 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_38 - 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_39 - 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_40 - 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_41 - 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_42 - 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_43 - 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_44 - 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_45 - 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_46 - 4'b 0001, // index[303] PINMUX_DIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[304] PINMUX_DIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[305] PINMUX_DIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[306] PINMUX_DIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_15 - 4'b 0111, // index[319] PINMUX_DIO_PAD_ATTR_0 - 4'b 0111, // index[320] PINMUX_DIO_PAD_ATTR_1 - 4'b 0111, // index[321] PINMUX_DIO_PAD_ATTR_2 - 4'b 0111, // index[322] PINMUX_DIO_PAD_ATTR_3 - 4'b 0111, // index[323] PINMUX_DIO_PAD_ATTR_4 - 4'b 0111, // index[324] PINMUX_DIO_PAD_ATTR_5 - 4'b 0111, // index[325] PINMUX_DIO_PAD_ATTR_6 - 4'b 0111, // index[326] PINMUX_DIO_PAD_ATTR_7 - 4'b 0111, // index[327] PINMUX_DIO_PAD_ATTR_8 - 4'b 0111, // index[328] PINMUX_DIO_PAD_ATTR_9 - 4'b 0111, // index[329] PINMUX_DIO_PAD_ATTR_10 - 4'b 0111, // index[330] PINMUX_DIO_PAD_ATTR_11 - 4'b 0111, // index[331] PINMUX_DIO_PAD_ATTR_12 - 4'b 0111, // index[332] PINMUX_DIO_PAD_ATTR_13 - 4'b 0111, // index[333] PINMUX_DIO_PAD_ATTR_14 - 4'b 0111, // index[334] PINMUX_DIO_PAD_ATTR_15 - 4'b 1111, // index[335] PINMUX_MIO_PAD_SLEEP_STATUS_0 - 4'b 0011, // index[336] PINMUX_MIO_PAD_SLEEP_STATUS_1 - 4'b 0001, // index[337] PINMUX_MIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[338] PINMUX_MIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[339] PINMUX_MIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[340] PINMUX_MIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[341] PINMUX_MIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[342] PINMUX_MIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_16 - 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_17 - 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_18 - 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_19 - 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_20 - 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_21 - 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_22 - 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_23 - 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_24 - 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_25 - 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_26 - 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_27 - 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_28 - 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_29 - 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_30 - 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_31 - 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_32 - 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_33 - 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_34 - 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_35 - 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_36 - 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_37 - 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_38 - 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_39 - 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_40 - 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_41 - 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_42 - 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_43 - 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_44 - 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_45 - 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_46 - 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_16 - 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_17 - 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_18 - 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_19 - 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_20 - 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_21 - 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_22 - 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_23 - 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_24 - 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_25 - 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_26 - 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_27 - 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_28 - 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_29 - 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_30 - 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_31 - 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_32 - 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_33 - 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_34 - 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_35 - 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_36 - 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_37 - 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_38 - 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_39 - 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_40 - 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_41 - 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_42 - 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_43 - 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_44 - 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_45 - 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_46 - 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_16 - 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_17 - 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_18 - 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_19 - 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_20 - 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_21 - 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_22 - 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_23 - 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_24 - 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_25 - 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_26 - 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_27 - 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_28 - 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_29 - 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_30 - 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_31 - 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_32 - 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_33 - 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_34 - 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_35 - 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_36 - 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_37 - 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_38 - 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_39 - 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_40 - 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_41 - 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_42 - 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_43 - 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_44 - 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_45 - 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_46 - 4'b 0011, // index[478] PINMUX_DIO_PAD_SLEEP_STATUS - 4'b 0001, // index[479] PINMUX_DIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[480] PINMUX_DIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[481] PINMUX_DIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[482] PINMUX_DIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[483] PINMUX_DIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[484] PINMUX_DIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[485] PINMUX_DIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[486] PINMUX_DIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[487] PINMUX_DIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[488] PINMUX_DIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[489] PINMUX_DIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[527] PINMUX_WKUP_DETECTOR_REGWEN_0 - 4'b 0001, // index[528] PINMUX_WKUP_DETECTOR_REGWEN_1 - 4'b 0001, // index[529] PINMUX_WKUP_DETECTOR_REGWEN_2 - 4'b 0001, // index[530] PINMUX_WKUP_DETECTOR_REGWEN_3 - 4'b 0001, // index[531] PINMUX_WKUP_DETECTOR_REGWEN_4 - 4'b 0001, // index[532] PINMUX_WKUP_DETECTOR_REGWEN_5 - 4'b 0001, // index[533] PINMUX_WKUP_DETECTOR_REGWEN_6 - 4'b 0001, // index[534] PINMUX_WKUP_DETECTOR_REGWEN_7 - 4'b 0001, // index[535] PINMUX_WKUP_DETECTOR_EN_0 - 4'b 0001, // index[536] PINMUX_WKUP_DETECTOR_EN_1 - 4'b 0001, // index[537] PINMUX_WKUP_DETECTOR_EN_2 - 4'b 0001, // index[538] PINMUX_WKUP_DETECTOR_EN_3 - 4'b 0001, // index[539] PINMUX_WKUP_DETECTOR_EN_4 - 4'b 0001, // index[540] PINMUX_WKUP_DETECTOR_EN_5 - 4'b 0001, // index[541] PINMUX_WKUP_DETECTOR_EN_6 - 4'b 0001, // index[542] PINMUX_WKUP_DETECTOR_EN_7 - 4'b 0001, // index[543] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[544] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[545] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[546] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[547] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[548] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[549] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[550] PINMUX_WKUP_DETECTOR_7 - 4'b 0001, // index[551] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 0001, // index[552] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 0001, // index[553] PINMUX_WKUP_DETECTOR_CNT_TH_2 - 4'b 0001, // index[554] PINMUX_WKUP_DETECTOR_CNT_TH_3 - 4'b 0001, // index[555] PINMUX_WKUP_DETECTOR_CNT_TH_4 - 4'b 0001, // index[556] PINMUX_WKUP_DETECTOR_CNT_TH_5 - 4'b 0001, // index[557] PINMUX_WKUP_DETECTOR_CNT_TH_6 - 4'b 0001, // index[558] PINMUX_WKUP_DETECTOR_CNT_TH_7 - 4'b 0001, // index[559] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0001, // index[560] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001, // index[561] PINMUX_WKUP_DETECTOR_PADSEL_2 - 4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_PADSEL_3 - 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_PADSEL_4 - 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_PADSEL_5 - 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_PADSEL_6 - 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_PADSEL_7 - 4'b 0001 // index[567] PINMUX_WKUP_CAUSE + 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_REGWEN_57 + 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_REGWEN_58 + 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_0 + 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_1 + 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_2 + 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_3 + 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_4 + 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_5 + 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_6 + 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_7 + 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_8 + 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_9 + 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_10 + 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_11 + 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_12 + 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_13 + 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_14 + 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_15 + 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_16 + 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_17 + 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_18 + 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_19 + 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_20 + 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_21 + 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_22 + 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_23 + 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_24 + 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_25 + 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_26 + 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_27 + 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_28 + 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_29 + 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_30 + 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_31 + 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_32 + 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_33 + 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_34 + 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_35 + 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_36 + 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_37 + 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_38 + 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_39 + 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_40 + 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_41 + 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_42 + 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_43 + 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_44 + 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_45 + 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_46 + 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_47 + 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_48 + 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_49 + 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_50 + 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_51 + 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_52 + 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_53 + 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_54 + 4'b 0001, // index[115] PINMUX_MIO_PERIPH_INSEL_55 + 4'b 0001, // index[116] PINMUX_MIO_PERIPH_INSEL_56 + 4'b 0001, // index[117] PINMUX_MIO_PERIPH_INSEL_57 + 4'b 0001, // index[118] PINMUX_MIO_PERIPH_INSEL_58 + 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_0 + 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_1 + 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_2 + 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_3 + 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_4 + 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_5 + 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_6 + 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_7 + 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_8 + 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_9 + 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_10 + 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_11 + 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_12 + 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_13 + 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_14 + 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_15 + 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_16 + 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_17 + 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_18 + 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_19 + 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_20 + 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_21 + 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_22 + 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_23 + 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_24 + 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_25 + 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_26 + 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_27 + 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_28 + 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_29 + 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_30 + 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_31 + 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_32 + 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_33 + 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_34 + 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_35 + 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_36 + 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_37 + 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_38 + 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_39 + 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_40 + 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_41 + 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_42 + 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_REGWEN_43 + 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_REGWEN_44 + 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_REGWEN_45 + 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_REGWEN_46 + 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_0 + 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_1 + 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_2 + 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_3 + 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_4 + 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_5 + 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_6 + 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_7 + 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_8 + 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_9 + 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_10 + 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_11 + 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_12 + 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_13 + 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_14 + 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_15 + 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_16 + 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_17 + 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_18 + 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_19 + 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_20 + 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_21 + 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_22 + 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_23 + 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_24 + 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_25 + 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_26 + 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_27 + 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_28 + 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_29 + 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_30 + 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_31 + 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_32 + 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_33 + 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_34 + 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_35 + 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_36 + 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_37 + 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_38 + 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_39 + 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_40 + 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_41 + 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_42 + 4'b 0001, // index[209] PINMUX_MIO_OUTSEL_43 + 4'b 0001, // index[210] PINMUX_MIO_OUTSEL_44 + 4'b 0001, // index[211] PINMUX_MIO_OUTSEL_45 + 4'b 0001, // index[212] PINMUX_MIO_OUTSEL_46 + 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_42 + 4'b 0001, // index[256] PINMUX_MIO_PAD_ATTR_REGWEN_43 + 4'b 0001, // index[257] PINMUX_MIO_PAD_ATTR_REGWEN_44 + 4'b 0001, // index[258] PINMUX_MIO_PAD_ATTR_REGWEN_45 + 4'b 0001, // index[259] PINMUX_MIO_PAD_ATTR_REGWEN_46 + 4'b 0111, // index[260] PINMUX_MIO_PAD_ATTR_0 + 4'b 0111, // index[261] PINMUX_MIO_PAD_ATTR_1 + 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_2 + 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_3 + 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_4 + 4'b 0111, // index[265] PINMUX_MIO_PAD_ATTR_5 + 4'b 0111, // index[266] PINMUX_MIO_PAD_ATTR_6 + 4'b 0111, // index[267] PINMUX_MIO_PAD_ATTR_7 + 4'b 0111, // index[268] PINMUX_MIO_PAD_ATTR_8 + 4'b 0111, // index[269] PINMUX_MIO_PAD_ATTR_9 + 4'b 0111, // index[270] PINMUX_MIO_PAD_ATTR_10 + 4'b 0111, // index[271] PINMUX_MIO_PAD_ATTR_11 + 4'b 0111, // index[272] PINMUX_MIO_PAD_ATTR_12 + 4'b 0111, // index[273] PINMUX_MIO_PAD_ATTR_13 + 4'b 0111, // index[274] PINMUX_MIO_PAD_ATTR_14 + 4'b 0111, // index[275] PINMUX_MIO_PAD_ATTR_15 + 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_16 + 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_17 + 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_18 + 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_19 + 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_20 + 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_21 + 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_22 + 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_23 + 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_24 + 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_25 + 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_26 + 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_27 + 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_28 + 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_29 + 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_30 + 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_31 + 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_32 + 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_33 + 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_34 + 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_35 + 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_36 + 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_37 + 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_38 + 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_39 + 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_40 + 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_41 + 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_42 + 4'b 0111, // index[303] PINMUX_MIO_PAD_ATTR_43 + 4'b 0111, // index[304] PINMUX_MIO_PAD_ATTR_44 + 4'b 0111, // index[305] PINMUX_MIO_PAD_ATTR_45 + 4'b 0111, // index[306] PINMUX_MIO_PAD_ATTR_46 + 4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[322] PINMUX_DIO_PAD_ATTR_REGWEN_15 + 4'b 0111, // index[323] PINMUX_DIO_PAD_ATTR_0 + 4'b 0111, // index[324] PINMUX_DIO_PAD_ATTR_1 + 4'b 0111, // index[325] PINMUX_DIO_PAD_ATTR_2 + 4'b 0111, // index[326] PINMUX_DIO_PAD_ATTR_3 + 4'b 0111, // index[327] PINMUX_DIO_PAD_ATTR_4 + 4'b 0111, // index[328] PINMUX_DIO_PAD_ATTR_5 + 4'b 0111, // index[329] PINMUX_DIO_PAD_ATTR_6 + 4'b 0111, // index[330] PINMUX_DIO_PAD_ATTR_7 + 4'b 0111, // index[331] PINMUX_DIO_PAD_ATTR_8 + 4'b 0111, // index[332] PINMUX_DIO_PAD_ATTR_9 + 4'b 0111, // index[333] PINMUX_DIO_PAD_ATTR_10 + 4'b 0111, // index[334] PINMUX_DIO_PAD_ATTR_11 + 4'b 0111, // index[335] PINMUX_DIO_PAD_ATTR_12 + 4'b 0111, // index[336] PINMUX_DIO_PAD_ATTR_13 + 4'b 0111, // index[337] PINMUX_DIO_PAD_ATTR_14 + 4'b 0111, // index[338] PINMUX_DIO_PAD_ATTR_15 + 4'b 1111, // index[339] PINMUX_MIO_PAD_SLEEP_STATUS_0 + 4'b 0011, // index[340] PINMUX_MIO_PAD_SLEEP_STATUS_1 + 4'b 0001, // index[341] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[342] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_REGWEN_43 + 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_REGWEN_44 + 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_REGWEN_45 + 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_REGWEN_46 + 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_EN_43 + 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_EN_44 + 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_EN_45 + 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_EN_46 + 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_MODE_43 + 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_MODE_44 + 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_MODE_45 + 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_MODE_46 + 4'b 0011, // index[482] PINMUX_DIO_PAD_SLEEP_STATUS + 4'b 0001, // index[483] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[484] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[485] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[486] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[487] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[488] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[489] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[527] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[528] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[529] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[530] PINMUX_DIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[531] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[532] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[533] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[534] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[535] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[536] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[537] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[538] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[539] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[540] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[541] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[542] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[543] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[544] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[545] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[546] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[547] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[548] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[549] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[550] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[551] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[552] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[553] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[554] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[555] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[556] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[557] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[558] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[559] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[560] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[561] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[567] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[568] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[569] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[570] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[571] PINMUX_WKUP_CAUSE }; endpackage diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv index c958108e156d70..13f921c2cd0c1b 100644 --- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv +++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv @@ -54,9 +54,9 @@ module pinmux_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [567:0] reg_we_check; + logic [571:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(568) + .OneHotWidth(572) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -296,6 +296,12 @@ module pinmux_reg_top ( logic mio_periph_insel_regwen_56_we; logic mio_periph_insel_regwen_56_qs; logic mio_periph_insel_regwen_56_wd; + logic mio_periph_insel_regwen_57_we; + logic mio_periph_insel_regwen_57_qs; + logic mio_periph_insel_regwen_57_wd; + logic mio_periph_insel_regwen_58_we; + logic mio_periph_insel_regwen_58_qs; + logic mio_periph_insel_regwen_58_wd; logic mio_periph_insel_0_we; logic [5:0] mio_periph_insel_0_qs; logic [5:0] mio_periph_insel_0_wd; @@ -467,6 +473,12 @@ module pinmux_reg_top ( logic mio_periph_insel_56_we; logic [5:0] mio_periph_insel_56_qs; logic [5:0] mio_periph_insel_56_wd; + logic mio_periph_insel_57_we; + logic [5:0] mio_periph_insel_57_qs; + logic [5:0] mio_periph_insel_57_wd; + logic mio_periph_insel_58_we; + logic [5:0] mio_periph_insel_58_qs; + logic [5:0] mio_periph_insel_58_wd; logic mio_outsel_regwen_0_we; logic mio_outsel_regwen_0_qs; logic mio_outsel_regwen_0_wd; @@ -5733,6 +5745,64 @@ module pinmux_reg_top ( ); + // Subregister 57 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_57_we), + .wd (mio_periph_insel_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_57_qs) + ); + + + // Subregister 58 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_58_we), + .wd (mio_periph_insel_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_58_qs) + ); + + // Subregister 0 of Multireg mio_periph_insel // R[mio_periph_insel_0]: V(False) // Create REGWEN-gated WE signal @@ -7557,6 +7627,70 @@ module pinmux_reg_top ( ); + // Subregister 57 of Multireg mio_periph_insel + // R[mio_periph_insel_57]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_57_gated_we; + assign mio_periph_insel_57_gated_we = mio_periph_insel_57_we & mio_periph_insel_regwen_57_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_57_gated_we), + .wd (mio_periph_insel_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[57].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_57_qs) + ); + + + // Subregister 58 of Multireg mio_periph_insel + // R[mio_periph_insel_58]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_58_gated_we; + assign mio_periph_insel_58_gated_we = mio_periph_insel_58_we & mio_periph_insel_regwen_58_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_58_gated_we), + .wd (mio_periph_insel_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[58].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_58_qs) + ); + + // Subregister 0 of Multireg mio_outsel_regwen // R[mio_outsel_regwen_0]: V(False) prim_subreg #( @@ -31393,7 +31527,7 @@ module pinmux_reg_top ( - logic [567:0] addr_hit; + logic [571:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET); @@ -31454,516 +31588,520 @@ module pinmux_reg_top ( addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET); addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET); addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET); - addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); - addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); - addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); - addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); - addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); - addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); - addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); - addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); - addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); - addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); - addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); - addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); - addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); - addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); - addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); - addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); - addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); - addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); - addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); - addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); - addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); - addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); - addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); - addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); - addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); - addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); - addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); - addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); - addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); - addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); - addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); - addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); - addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); - addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); - addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); - addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); - addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); - addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); - addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); - addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); - addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); - addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); - addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); - addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); - addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); - addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); - addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); - addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); - addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); - addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); - addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); - addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); - addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); - addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); - addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); - addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); - addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); - addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); - addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); - addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); - addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); - addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); - addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); - addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); - addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); - addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); - addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); - addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); - addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); - addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); - addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); - addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); - addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); - addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); - addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); - addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); - addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); - addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); - addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); - addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); - addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); - addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); - addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); - addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); - addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); - addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); - addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); - addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); - addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); - addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); - addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); - addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); - addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); - addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); - addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); - addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); - addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); - addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); - addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); - addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); - addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); - addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); - addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); - addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); - addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); - addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); - addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); - addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); - addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); - addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); - addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); - addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); - addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); - addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); - addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); - addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); - addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); - addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); - addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); - addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); - addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); - addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); - addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); - addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); - addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); - addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); - addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); - addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); - addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); - addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); - addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); - addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); - addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); - addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); - addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); - addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); - addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); - addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); - addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); - addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); - addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); - addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); - addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); - addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); - addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); - addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); - addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); - addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); - addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); - addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); - addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); - addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); - addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); - addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); - addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); - addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); - addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); - addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); - addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); - addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); - addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); - addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); - addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); - addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); - addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); - addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); - addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); - addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); - addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); - addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); - addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); - addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); - addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); - addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); - addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); - addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); - addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); - addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); - addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); - addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); - addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); - addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); - addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); - addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); - addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); - addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); - addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); - addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); - addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); - addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); - addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); - addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); - addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); - addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); - addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); - addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); - addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); - addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); - addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); - addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); - addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); - addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); - addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); - addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); - addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); - addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); - addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); - addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); - addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); - addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); - addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); - addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); - addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); - addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); - addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); - addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); - addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); - addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); - addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); - addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); - addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); - addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); - addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); - addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); - addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); - addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); - addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); - addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); - addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); - addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); - addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); - addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); - addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); - addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); - addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); - addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); - addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); - addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); - addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); - addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); - addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); - addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); - addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); - addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); - addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); - addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); - addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); - addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); - addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); - addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); - addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); - addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); - addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); - addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); - addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); - addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); - addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); - addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); - addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); - addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); - addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); - addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); - addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); - addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); - addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); - addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); - addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); - addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); - addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); - addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); - addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); - addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); - addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); - addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); - addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); - addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); - addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); - addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); - addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); - addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); - addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); - addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); - addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); - addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); - addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); - addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); - addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); - addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); - addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); - addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); - addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); - addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); - addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); - addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); - addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); - addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); - addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); - addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); - addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); - addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); - addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); - addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); - addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); - addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); - addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); - addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); - addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); - addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); - addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); - addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); - addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); - addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); - addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); - addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); - addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); - addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); - addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); - addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); - addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); - addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); - addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); - addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); - addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); - addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); - addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); - addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); - addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); - addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); - addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); - addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); - addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); - addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); - addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); - addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); - addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); - addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); - addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); - addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); - addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); - addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); - addr_hit[478] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); - addr_hit[479] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[480] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[481] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[482] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[483] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[527] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); - addr_hit[528] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); - addr_hit[529] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); - addr_hit[530] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); - addr_hit[531] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); - addr_hit[532] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); - addr_hit[533] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); - addr_hit[534] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); - addr_hit[535] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); - addr_hit[536] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); - addr_hit[537] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); - addr_hit[538] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); - addr_hit[539] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); - addr_hit[540] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); - addr_hit[541] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); - addr_hit[542] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); - addr_hit[543] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); - addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); - addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); - addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); - addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); - addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); - addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); - addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); - addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); - addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); - addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); - addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); - addr_hit[567] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET); + addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET); + addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); + addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); + addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); + addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); + addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); + addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); + addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); + addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); + addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); + addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); + addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); + addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); + addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); + addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); + addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); + addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); + addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); + addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); + addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); + addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); + addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); + addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); + addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); + addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); + addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); + addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); + addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); + addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); + addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); + addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); + addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); + addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); + addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); + addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); + addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); + addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); + addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); + addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); + addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); + addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); + addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); + addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); + addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); + addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); + addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); + addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); + addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); + addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); + addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); + addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); + addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); + addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); + addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); + addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); + addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); + addr_hit[115] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); + addr_hit[116] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); + addr_hit[117] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_57_OFFSET); + addr_hit[118] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_58_OFFSET); + addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); + addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); + addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); + addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); + addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); + addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); + addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); + addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); + addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); + addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); + addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); + addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); + addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); + addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); + addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); + addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); + addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); + addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); + addr_hit[482] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[483] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[527] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[528] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[529] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[530] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[531] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[532] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[533] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[534] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[535] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[536] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[537] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[538] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[539] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[540] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[541] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[542] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[543] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[567] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[568] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[569] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[570] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[571] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -32538,7 +32676,11 @@ module pinmux_reg_top ( (addr_hit[564] & (|(PINMUX_PERMIT[564] & ~reg_be))) | (addr_hit[565] & (|(PINMUX_PERMIT[565] & ~reg_be))) | (addr_hit[566] & (|(PINMUX_PERMIT[566] & ~reg_be))) | - (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be))))); + (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be))) | + (addr_hit[568] & (|(PINMUX_PERMIT[568] & ~reg_be))) | + (addr_hit[569] & (|(PINMUX_PERMIT[569] & ~reg_be))) | + (addr_hit[570] & (|(PINMUX_PERMIT[570] & ~reg_be))) | + (addr_hit[571] & (|(PINMUX_PERMIT[571] & ~reg_be))))); end // Generate write-enables @@ -32716,602 +32858,614 @@ module pinmux_reg_top ( assign mio_periph_insel_regwen_56_we = addr_hit[57] & reg_we & !reg_error; assign mio_periph_insel_regwen_56_wd = reg_wdata[0]; - assign mio_periph_insel_0_we = addr_hit[58] & reg_we & !reg_error; + assign mio_periph_insel_regwen_57_we = addr_hit[58] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_57_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_58_we = addr_hit[59] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_58_wd = reg_wdata[0]; + assign mio_periph_insel_0_we = addr_hit[60] & reg_we & !reg_error; assign mio_periph_insel_0_wd = reg_wdata[5:0]; - assign mio_periph_insel_1_we = addr_hit[59] & reg_we & !reg_error; + assign mio_periph_insel_1_we = addr_hit[61] & reg_we & !reg_error; assign mio_periph_insel_1_wd = reg_wdata[5:0]; - assign mio_periph_insel_2_we = addr_hit[60] & reg_we & !reg_error; + assign mio_periph_insel_2_we = addr_hit[62] & reg_we & !reg_error; assign mio_periph_insel_2_wd = reg_wdata[5:0]; - assign mio_periph_insel_3_we = addr_hit[61] & reg_we & !reg_error; + assign mio_periph_insel_3_we = addr_hit[63] & reg_we & !reg_error; assign mio_periph_insel_3_wd = reg_wdata[5:0]; - assign mio_periph_insel_4_we = addr_hit[62] & reg_we & !reg_error; + assign mio_periph_insel_4_we = addr_hit[64] & reg_we & !reg_error; assign mio_periph_insel_4_wd = reg_wdata[5:0]; - assign mio_periph_insel_5_we = addr_hit[63] & reg_we & !reg_error; + assign mio_periph_insel_5_we = addr_hit[65] & reg_we & !reg_error; assign mio_periph_insel_5_wd = reg_wdata[5:0]; - assign mio_periph_insel_6_we = addr_hit[64] & reg_we & !reg_error; + assign mio_periph_insel_6_we = addr_hit[66] & reg_we & !reg_error; assign mio_periph_insel_6_wd = reg_wdata[5:0]; - assign mio_periph_insel_7_we = addr_hit[65] & reg_we & !reg_error; + assign mio_periph_insel_7_we = addr_hit[67] & reg_we & !reg_error; assign mio_periph_insel_7_wd = reg_wdata[5:0]; - assign mio_periph_insel_8_we = addr_hit[66] & reg_we & !reg_error; + assign mio_periph_insel_8_we = addr_hit[68] & reg_we & !reg_error; assign mio_periph_insel_8_wd = reg_wdata[5:0]; - assign mio_periph_insel_9_we = addr_hit[67] & reg_we & !reg_error; + assign mio_periph_insel_9_we = addr_hit[69] & reg_we & !reg_error; assign mio_periph_insel_9_wd = reg_wdata[5:0]; - assign mio_periph_insel_10_we = addr_hit[68] & reg_we & !reg_error; + assign mio_periph_insel_10_we = addr_hit[70] & reg_we & !reg_error; assign mio_periph_insel_10_wd = reg_wdata[5:0]; - assign mio_periph_insel_11_we = addr_hit[69] & reg_we & !reg_error; + assign mio_periph_insel_11_we = addr_hit[71] & reg_we & !reg_error; assign mio_periph_insel_11_wd = reg_wdata[5:0]; - assign mio_periph_insel_12_we = addr_hit[70] & reg_we & !reg_error; + assign mio_periph_insel_12_we = addr_hit[72] & reg_we & !reg_error; assign mio_periph_insel_12_wd = reg_wdata[5:0]; - assign mio_periph_insel_13_we = addr_hit[71] & reg_we & !reg_error; + assign mio_periph_insel_13_we = addr_hit[73] & reg_we & !reg_error; assign mio_periph_insel_13_wd = reg_wdata[5:0]; - assign mio_periph_insel_14_we = addr_hit[72] & reg_we & !reg_error; + assign mio_periph_insel_14_we = addr_hit[74] & reg_we & !reg_error; assign mio_periph_insel_14_wd = reg_wdata[5:0]; - assign mio_periph_insel_15_we = addr_hit[73] & reg_we & !reg_error; + assign mio_periph_insel_15_we = addr_hit[75] & reg_we & !reg_error; assign mio_periph_insel_15_wd = reg_wdata[5:0]; - assign mio_periph_insel_16_we = addr_hit[74] & reg_we & !reg_error; + assign mio_periph_insel_16_we = addr_hit[76] & reg_we & !reg_error; assign mio_periph_insel_16_wd = reg_wdata[5:0]; - assign mio_periph_insel_17_we = addr_hit[75] & reg_we & !reg_error; + assign mio_periph_insel_17_we = addr_hit[77] & reg_we & !reg_error; assign mio_periph_insel_17_wd = reg_wdata[5:0]; - assign mio_periph_insel_18_we = addr_hit[76] & reg_we & !reg_error; + assign mio_periph_insel_18_we = addr_hit[78] & reg_we & !reg_error; assign mio_periph_insel_18_wd = reg_wdata[5:0]; - assign mio_periph_insel_19_we = addr_hit[77] & reg_we & !reg_error; + assign mio_periph_insel_19_we = addr_hit[79] & reg_we & !reg_error; assign mio_periph_insel_19_wd = reg_wdata[5:0]; - assign mio_periph_insel_20_we = addr_hit[78] & reg_we & !reg_error; + assign mio_periph_insel_20_we = addr_hit[80] & reg_we & !reg_error; assign mio_periph_insel_20_wd = reg_wdata[5:0]; - assign mio_periph_insel_21_we = addr_hit[79] & reg_we & !reg_error; + assign mio_periph_insel_21_we = addr_hit[81] & reg_we & !reg_error; assign mio_periph_insel_21_wd = reg_wdata[5:0]; - assign mio_periph_insel_22_we = addr_hit[80] & reg_we & !reg_error; + assign mio_periph_insel_22_we = addr_hit[82] & reg_we & !reg_error; assign mio_periph_insel_22_wd = reg_wdata[5:0]; - assign mio_periph_insel_23_we = addr_hit[81] & reg_we & !reg_error; + assign mio_periph_insel_23_we = addr_hit[83] & reg_we & !reg_error; assign mio_periph_insel_23_wd = reg_wdata[5:0]; - assign mio_periph_insel_24_we = addr_hit[82] & reg_we & !reg_error; + assign mio_periph_insel_24_we = addr_hit[84] & reg_we & !reg_error; assign mio_periph_insel_24_wd = reg_wdata[5:0]; - assign mio_periph_insel_25_we = addr_hit[83] & reg_we & !reg_error; + assign mio_periph_insel_25_we = addr_hit[85] & reg_we & !reg_error; assign mio_periph_insel_25_wd = reg_wdata[5:0]; - assign mio_periph_insel_26_we = addr_hit[84] & reg_we & !reg_error; + assign mio_periph_insel_26_we = addr_hit[86] & reg_we & !reg_error; assign mio_periph_insel_26_wd = reg_wdata[5:0]; - assign mio_periph_insel_27_we = addr_hit[85] & reg_we & !reg_error; + assign mio_periph_insel_27_we = addr_hit[87] & reg_we & !reg_error; assign mio_periph_insel_27_wd = reg_wdata[5:0]; - assign mio_periph_insel_28_we = addr_hit[86] & reg_we & !reg_error; + assign mio_periph_insel_28_we = addr_hit[88] & reg_we & !reg_error; assign mio_periph_insel_28_wd = reg_wdata[5:0]; - assign mio_periph_insel_29_we = addr_hit[87] & reg_we & !reg_error; + assign mio_periph_insel_29_we = addr_hit[89] & reg_we & !reg_error; assign mio_periph_insel_29_wd = reg_wdata[5:0]; - assign mio_periph_insel_30_we = addr_hit[88] & reg_we & !reg_error; + assign mio_periph_insel_30_we = addr_hit[90] & reg_we & !reg_error; assign mio_periph_insel_30_wd = reg_wdata[5:0]; - assign mio_periph_insel_31_we = addr_hit[89] & reg_we & !reg_error; + assign mio_periph_insel_31_we = addr_hit[91] & reg_we & !reg_error; assign mio_periph_insel_31_wd = reg_wdata[5:0]; - assign mio_periph_insel_32_we = addr_hit[90] & reg_we & !reg_error; + assign mio_periph_insel_32_we = addr_hit[92] & reg_we & !reg_error; assign mio_periph_insel_32_wd = reg_wdata[5:0]; - assign mio_periph_insel_33_we = addr_hit[91] & reg_we & !reg_error; + assign mio_periph_insel_33_we = addr_hit[93] & reg_we & !reg_error; assign mio_periph_insel_33_wd = reg_wdata[5:0]; - assign mio_periph_insel_34_we = addr_hit[92] & reg_we & !reg_error; + assign mio_periph_insel_34_we = addr_hit[94] & reg_we & !reg_error; assign mio_periph_insel_34_wd = reg_wdata[5:0]; - assign mio_periph_insel_35_we = addr_hit[93] & reg_we & !reg_error; + assign mio_periph_insel_35_we = addr_hit[95] & reg_we & !reg_error; assign mio_periph_insel_35_wd = reg_wdata[5:0]; - assign mio_periph_insel_36_we = addr_hit[94] & reg_we & !reg_error; + assign mio_periph_insel_36_we = addr_hit[96] & reg_we & !reg_error; assign mio_periph_insel_36_wd = reg_wdata[5:0]; - assign mio_periph_insel_37_we = addr_hit[95] & reg_we & !reg_error; + assign mio_periph_insel_37_we = addr_hit[97] & reg_we & !reg_error; assign mio_periph_insel_37_wd = reg_wdata[5:0]; - assign mio_periph_insel_38_we = addr_hit[96] & reg_we & !reg_error; + assign mio_periph_insel_38_we = addr_hit[98] & reg_we & !reg_error; assign mio_periph_insel_38_wd = reg_wdata[5:0]; - assign mio_periph_insel_39_we = addr_hit[97] & reg_we & !reg_error; + assign mio_periph_insel_39_we = addr_hit[99] & reg_we & !reg_error; assign mio_periph_insel_39_wd = reg_wdata[5:0]; - assign mio_periph_insel_40_we = addr_hit[98] & reg_we & !reg_error; + assign mio_periph_insel_40_we = addr_hit[100] & reg_we & !reg_error; assign mio_periph_insel_40_wd = reg_wdata[5:0]; - assign mio_periph_insel_41_we = addr_hit[99] & reg_we & !reg_error; + assign mio_periph_insel_41_we = addr_hit[101] & reg_we & !reg_error; assign mio_periph_insel_41_wd = reg_wdata[5:0]; - assign mio_periph_insel_42_we = addr_hit[100] & reg_we & !reg_error; + assign mio_periph_insel_42_we = addr_hit[102] & reg_we & !reg_error; assign mio_periph_insel_42_wd = reg_wdata[5:0]; - assign mio_periph_insel_43_we = addr_hit[101] & reg_we & !reg_error; + assign mio_periph_insel_43_we = addr_hit[103] & reg_we & !reg_error; assign mio_periph_insel_43_wd = reg_wdata[5:0]; - assign mio_periph_insel_44_we = addr_hit[102] & reg_we & !reg_error; + assign mio_periph_insel_44_we = addr_hit[104] & reg_we & !reg_error; assign mio_periph_insel_44_wd = reg_wdata[5:0]; - assign mio_periph_insel_45_we = addr_hit[103] & reg_we & !reg_error; + assign mio_periph_insel_45_we = addr_hit[105] & reg_we & !reg_error; assign mio_periph_insel_45_wd = reg_wdata[5:0]; - assign mio_periph_insel_46_we = addr_hit[104] & reg_we & !reg_error; + assign mio_periph_insel_46_we = addr_hit[106] & reg_we & !reg_error; assign mio_periph_insel_46_wd = reg_wdata[5:0]; - assign mio_periph_insel_47_we = addr_hit[105] & reg_we & !reg_error; + assign mio_periph_insel_47_we = addr_hit[107] & reg_we & !reg_error; assign mio_periph_insel_47_wd = reg_wdata[5:0]; - assign mio_periph_insel_48_we = addr_hit[106] & reg_we & !reg_error; + assign mio_periph_insel_48_we = addr_hit[108] & reg_we & !reg_error; assign mio_periph_insel_48_wd = reg_wdata[5:0]; - assign mio_periph_insel_49_we = addr_hit[107] & reg_we & !reg_error; + assign mio_periph_insel_49_we = addr_hit[109] & reg_we & !reg_error; assign mio_periph_insel_49_wd = reg_wdata[5:0]; - assign mio_periph_insel_50_we = addr_hit[108] & reg_we & !reg_error; + assign mio_periph_insel_50_we = addr_hit[110] & reg_we & !reg_error; assign mio_periph_insel_50_wd = reg_wdata[5:0]; - assign mio_periph_insel_51_we = addr_hit[109] & reg_we & !reg_error; + assign mio_periph_insel_51_we = addr_hit[111] & reg_we & !reg_error; assign mio_periph_insel_51_wd = reg_wdata[5:0]; - assign mio_periph_insel_52_we = addr_hit[110] & reg_we & !reg_error; + assign mio_periph_insel_52_we = addr_hit[112] & reg_we & !reg_error; assign mio_periph_insel_52_wd = reg_wdata[5:0]; - assign mio_periph_insel_53_we = addr_hit[111] & reg_we & !reg_error; + assign mio_periph_insel_53_we = addr_hit[113] & reg_we & !reg_error; assign mio_periph_insel_53_wd = reg_wdata[5:0]; - assign mio_periph_insel_54_we = addr_hit[112] & reg_we & !reg_error; + assign mio_periph_insel_54_we = addr_hit[114] & reg_we & !reg_error; assign mio_periph_insel_54_wd = reg_wdata[5:0]; - assign mio_periph_insel_55_we = addr_hit[113] & reg_we & !reg_error; + assign mio_periph_insel_55_we = addr_hit[115] & reg_we & !reg_error; assign mio_periph_insel_55_wd = reg_wdata[5:0]; - assign mio_periph_insel_56_we = addr_hit[114] & reg_we & !reg_error; + assign mio_periph_insel_56_we = addr_hit[116] & reg_we & !reg_error; assign mio_periph_insel_56_wd = reg_wdata[5:0]; - assign mio_outsel_regwen_0_we = addr_hit[115] & reg_we & !reg_error; + assign mio_periph_insel_57_we = addr_hit[117] & reg_we & !reg_error; + + assign mio_periph_insel_57_wd = reg_wdata[5:0]; + assign mio_periph_insel_58_we = addr_hit[118] & reg_we & !reg_error; + + assign mio_periph_insel_58_wd = reg_wdata[5:0]; + assign mio_outsel_regwen_0_we = addr_hit[119] & reg_we & !reg_error; assign mio_outsel_regwen_0_wd = reg_wdata[0]; - assign mio_outsel_regwen_1_we = addr_hit[116] & reg_we & !reg_error; + assign mio_outsel_regwen_1_we = addr_hit[120] & reg_we & !reg_error; assign mio_outsel_regwen_1_wd = reg_wdata[0]; - assign mio_outsel_regwen_2_we = addr_hit[117] & reg_we & !reg_error; + assign mio_outsel_regwen_2_we = addr_hit[121] & reg_we & !reg_error; assign mio_outsel_regwen_2_wd = reg_wdata[0]; - assign mio_outsel_regwen_3_we = addr_hit[118] & reg_we & !reg_error; + assign mio_outsel_regwen_3_we = addr_hit[122] & reg_we & !reg_error; assign mio_outsel_regwen_3_wd = reg_wdata[0]; - assign mio_outsel_regwen_4_we = addr_hit[119] & reg_we & !reg_error; + assign mio_outsel_regwen_4_we = addr_hit[123] & reg_we & !reg_error; assign mio_outsel_regwen_4_wd = reg_wdata[0]; - assign mio_outsel_regwen_5_we = addr_hit[120] & reg_we & !reg_error; + assign mio_outsel_regwen_5_we = addr_hit[124] & reg_we & !reg_error; assign mio_outsel_regwen_5_wd = reg_wdata[0]; - assign mio_outsel_regwen_6_we = addr_hit[121] & reg_we & !reg_error; + assign mio_outsel_regwen_6_we = addr_hit[125] & reg_we & !reg_error; assign mio_outsel_regwen_6_wd = reg_wdata[0]; - assign mio_outsel_regwen_7_we = addr_hit[122] & reg_we & !reg_error; + assign mio_outsel_regwen_7_we = addr_hit[126] & reg_we & !reg_error; assign mio_outsel_regwen_7_wd = reg_wdata[0]; - assign mio_outsel_regwen_8_we = addr_hit[123] & reg_we & !reg_error; + assign mio_outsel_regwen_8_we = addr_hit[127] & reg_we & !reg_error; assign mio_outsel_regwen_8_wd = reg_wdata[0]; - assign mio_outsel_regwen_9_we = addr_hit[124] & reg_we & !reg_error; + assign mio_outsel_regwen_9_we = addr_hit[128] & reg_we & !reg_error; assign mio_outsel_regwen_9_wd = reg_wdata[0]; - assign mio_outsel_regwen_10_we = addr_hit[125] & reg_we & !reg_error; + assign mio_outsel_regwen_10_we = addr_hit[129] & reg_we & !reg_error; assign mio_outsel_regwen_10_wd = reg_wdata[0]; - assign mio_outsel_regwen_11_we = addr_hit[126] & reg_we & !reg_error; + assign mio_outsel_regwen_11_we = addr_hit[130] & reg_we & !reg_error; assign mio_outsel_regwen_11_wd = reg_wdata[0]; - assign mio_outsel_regwen_12_we = addr_hit[127] & reg_we & !reg_error; + assign mio_outsel_regwen_12_we = addr_hit[131] & reg_we & !reg_error; assign mio_outsel_regwen_12_wd = reg_wdata[0]; - assign mio_outsel_regwen_13_we = addr_hit[128] & reg_we & !reg_error; + assign mio_outsel_regwen_13_we = addr_hit[132] & reg_we & !reg_error; assign mio_outsel_regwen_13_wd = reg_wdata[0]; - assign mio_outsel_regwen_14_we = addr_hit[129] & reg_we & !reg_error; + assign mio_outsel_regwen_14_we = addr_hit[133] & reg_we & !reg_error; assign mio_outsel_regwen_14_wd = reg_wdata[0]; - assign mio_outsel_regwen_15_we = addr_hit[130] & reg_we & !reg_error; + assign mio_outsel_regwen_15_we = addr_hit[134] & reg_we & !reg_error; assign mio_outsel_regwen_15_wd = reg_wdata[0]; - assign mio_outsel_regwen_16_we = addr_hit[131] & reg_we & !reg_error; + assign mio_outsel_regwen_16_we = addr_hit[135] & reg_we & !reg_error; assign mio_outsel_regwen_16_wd = reg_wdata[0]; - assign mio_outsel_regwen_17_we = addr_hit[132] & reg_we & !reg_error; + assign mio_outsel_regwen_17_we = addr_hit[136] & reg_we & !reg_error; assign mio_outsel_regwen_17_wd = reg_wdata[0]; - assign mio_outsel_regwen_18_we = addr_hit[133] & reg_we & !reg_error; + assign mio_outsel_regwen_18_we = addr_hit[137] & reg_we & !reg_error; assign mio_outsel_regwen_18_wd = reg_wdata[0]; - assign mio_outsel_regwen_19_we = addr_hit[134] & reg_we & !reg_error; + assign mio_outsel_regwen_19_we = addr_hit[138] & reg_we & !reg_error; assign mio_outsel_regwen_19_wd = reg_wdata[0]; - assign mio_outsel_regwen_20_we = addr_hit[135] & reg_we & !reg_error; + assign mio_outsel_regwen_20_we = addr_hit[139] & reg_we & !reg_error; assign mio_outsel_regwen_20_wd = reg_wdata[0]; - assign mio_outsel_regwen_21_we = addr_hit[136] & reg_we & !reg_error; + assign mio_outsel_regwen_21_we = addr_hit[140] & reg_we & !reg_error; assign mio_outsel_regwen_21_wd = reg_wdata[0]; - assign mio_outsel_regwen_22_we = addr_hit[137] & reg_we & !reg_error; + assign mio_outsel_regwen_22_we = addr_hit[141] & reg_we & !reg_error; assign mio_outsel_regwen_22_wd = reg_wdata[0]; - assign mio_outsel_regwen_23_we = addr_hit[138] & reg_we & !reg_error; + assign mio_outsel_regwen_23_we = addr_hit[142] & reg_we & !reg_error; assign mio_outsel_regwen_23_wd = reg_wdata[0]; - assign mio_outsel_regwen_24_we = addr_hit[139] & reg_we & !reg_error; + assign mio_outsel_regwen_24_we = addr_hit[143] & reg_we & !reg_error; assign mio_outsel_regwen_24_wd = reg_wdata[0]; - assign mio_outsel_regwen_25_we = addr_hit[140] & reg_we & !reg_error; + assign mio_outsel_regwen_25_we = addr_hit[144] & reg_we & !reg_error; assign mio_outsel_regwen_25_wd = reg_wdata[0]; - assign mio_outsel_regwen_26_we = addr_hit[141] & reg_we & !reg_error; + assign mio_outsel_regwen_26_we = addr_hit[145] & reg_we & !reg_error; assign mio_outsel_regwen_26_wd = reg_wdata[0]; - assign mio_outsel_regwen_27_we = addr_hit[142] & reg_we & !reg_error; + assign mio_outsel_regwen_27_we = addr_hit[146] & reg_we & !reg_error; assign mio_outsel_regwen_27_wd = reg_wdata[0]; - assign mio_outsel_regwen_28_we = addr_hit[143] & reg_we & !reg_error; + assign mio_outsel_regwen_28_we = addr_hit[147] & reg_we & !reg_error; assign mio_outsel_regwen_28_wd = reg_wdata[0]; - assign mio_outsel_regwen_29_we = addr_hit[144] & reg_we & !reg_error; + assign mio_outsel_regwen_29_we = addr_hit[148] & reg_we & !reg_error; assign mio_outsel_regwen_29_wd = reg_wdata[0]; - assign mio_outsel_regwen_30_we = addr_hit[145] & reg_we & !reg_error; + assign mio_outsel_regwen_30_we = addr_hit[149] & reg_we & !reg_error; assign mio_outsel_regwen_30_wd = reg_wdata[0]; - assign mio_outsel_regwen_31_we = addr_hit[146] & reg_we & !reg_error; + assign mio_outsel_regwen_31_we = addr_hit[150] & reg_we & !reg_error; assign mio_outsel_regwen_31_wd = reg_wdata[0]; - assign mio_outsel_regwen_32_we = addr_hit[147] & reg_we & !reg_error; + assign mio_outsel_regwen_32_we = addr_hit[151] & reg_we & !reg_error; assign mio_outsel_regwen_32_wd = reg_wdata[0]; - assign mio_outsel_regwen_33_we = addr_hit[148] & reg_we & !reg_error; + assign mio_outsel_regwen_33_we = addr_hit[152] & reg_we & !reg_error; assign mio_outsel_regwen_33_wd = reg_wdata[0]; - assign mio_outsel_regwen_34_we = addr_hit[149] & reg_we & !reg_error; + assign mio_outsel_regwen_34_we = addr_hit[153] & reg_we & !reg_error; assign mio_outsel_regwen_34_wd = reg_wdata[0]; - assign mio_outsel_regwen_35_we = addr_hit[150] & reg_we & !reg_error; + assign mio_outsel_regwen_35_we = addr_hit[154] & reg_we & !reg_error; assign mio_outsel_regwen_35_wd = reg_wdata[0]; - assign mio_outsel_regwen_36_we = addr_hit[151] & reg_we & !reg_error; + assign mio_outsel_regwen_36_we = addr_hit[155] & reg_we & !reg_error; assign mio_outsel_regwen_36_wd = reg_wdata[0]; - assign mio_outsel_regwen_37_we = addr_hit[152] & reg_we & !reg_error; + assign mio_outsel_regwen_37_we = addr_hit[156] & reg_we & !reg_error; assign mio_outsel_regwen_37_wd = reg_wdata[0]; - assign mio_outsel_regwen_38_we = addr_hit[153] & reg_we & !reg_error; + assign mio_outsel_regwen_38_we = addr_hit[157] & reg_we & !reg_error; assign mio_outsel_regwen_38_wd = reg_wdata[0]; - assign mio_outsel_regwen_39_we = addr_hit[154] & reg_we & !reg_error; + assign mio_outsel_regwen_39_we = addr_hit[158] & reg_we & !reg_error; assign mio_outsel_regwen_39_wd = reg_wdata[0]; - assign mio_outsel_regwen_40_we = addr_hit[155] & reg_we & !reg_error; + assign mio_outsel_regwen_40_we = addr_hit[159] & reg_we & !reg_error; assign mio_outsel_regwen_40_wd = reg_wdata[0]; - assign mio_outsel_regwen_41_we = addr_hit[156] & reg_we & !reg_error; + assign mio_outsel_regwen_41_we = addr_hit[160] & reg_we & !reg_error; assign mio_outsel_regwen_41_wd = reg_wdata[0]; - assign mio_outsel_regwen_42_we = addr_hit[157] & reg_we & !reg_error; + assign mio_outsel_regwen_42_we = addr_hit[161] & reg_we & !reg_error; assign mio_outsel_regwen_42_wd = reg_wdata[0]; - assign mio_outsel_regwen_43_we = addr_hit[158] & reg_we & !reg_error; + assign mio_outsel_regwen_43_we = addr_hit[162] & reg_we & !reg_error; assign mio_outsel_regwen_43_wd = reg_wdata[0]; - assign mio_outsel_regwen_44_we = addr_hit[159] & reg_we & !reg_error; + assign mio_outsel_regwen_44_we = addr_hit[163] & reg_we & !reg_error; assign mio_outsel_regwen_44_wd = reg_wdata[0]; - assign mio_outsel_regwen_45_we = addr_hit[160] & reg_we & !reg_error; + assign mio_outsel_regwen_45_we = addr_hit[164] & reg_we & !reg_error; assign mio_outsel_regwen_45_wd = reg_wdata[0]; - assign mio_outsel_regwen_46_we = addr_hit[161] & reg_we & !reg_error; + assign mio_outsel_regwen_46_we = addr_hit[165] & reg_we & !reg_error; assign mio_outsel_regwen_46_wd = reg_wdata[0]; - assign mio_outsel_0_we = addr_hit[162] & reg_we & !reg_error; + assign mio_outsel_0_we = addr_hit[166] & reg_we & !reg_error; assign mio_outsel_0_wd = reg_wdata[6:0]; - assign mio_outsel_1_we = addr_hit[163] & reg_we & !reg_error; + assign mio_outsel_1_we = addr_hit[167] & reg_we & !reg_error; assign mio_outsel_1_wd = reg_wdata[6:0]; - assign mio_outsel_2_we = addr_hit[164] & reg_we & !reg_error; + assign mio_outsel_2_we = addr_hit[168] & reg_we & !reg_error; assign mio_outsel_2_wd = reg_wdata[6:0]; - assign mio_outsel_3_we = addr_hit[165] & reg_we & !reg_error; + assign mio_outsel_3_we = addr_hit[169] & reg_we & !reg_error; assign mio_outsel_3_wd = reg_wdata[6:0]; - assign mio_outsel_4_we = addr_hit[166] & reg_we & !reg_error; + assign mio_outsel_4_we = addr_hit[170] & reg_we & !reg_error; assign mio_outsel_4_wd = reg_wdata[6:0]; - assign mio_outsel_5_we = addr_hit[167] & reg_we & !reg_error; + assign mio_outsel_5_we = addr_hit[171] & reg_we & !reg_error; assign mio_outsel_5_wd = reg_wdata[6:0]; - assign mio_outsel_6_we = addr_hit[168] & reg_we & !reg_error; + assign mio_outsel_6_we = addr_hit[172] & reg_we & !reg_error; assign mio_outsel_6_wd = reg_wdata[6:0]; - assign mio_outsel_7_we = addr_hit[169] & reg_we & !reg_error; + assign mio_outsel_7_we = addr_hit[173] & reg_we & !reg_error; assign mio_outsel_7_wd = reg_wdata[6:0]; - assign mio_outsel_8_we = addr_hit[170] & reg_we & !reg_error; + assign mio_outsel_8_we = addr_hit[174] & reg_we & !reg_error; assign mio_outsel_8_wd = reg_wdata[6:0]; - assign mio_outsel_9_we = addr_hit[171] & reg_we & !reg_error; + assign mio_outsel_9_we = addr_hit[175] & reg_we & !reg_error; assign mio_outsel_9_wd = reg_wdata[6:0]; - assign mio_outsel_10_we = addr_hit[172] & reg_we & !reg_error; + assign mio_outsel_10_we = addr_hit[176] & reg_we & !reg_error; assign mio_outsel_10_wd = reg_wdata[6:0]; - assign mio_outsel_11_we = addr_hit[173] & reg_we & !reg_error; + assign mio_outsel_11_we = addr_hit[177] & reg_we & !reg_error; assign mio_outsel_11_wd = reg_wdata[6:0]; - assign mio_outsel_12_we = addr_hit[174] & reg_we & !reg_error; + assign mio_outsel_12_we = addr_hit[178] & reg_we & !reg_error; assign mio_outsel_12_wd = reg_wdata[6:0]; - assign mio_outsel_13_we = addr_hit[175] & reg_we & !reg_error; + assign mio_outsel_13_we = addr_hit[179] & reg_we & !reg_error; assign mio_outsel_13_wd = reg_wdata[6:0]; - assign mio_outsel_14_we = addr_hit[176] & reg_we & !reg_error; + assign mio_outsel_14_we = addr_hit[180] & reg_we & !reg_error; assign mio_outsel_14_wd = reg_wdata[6:0]; - assign mio_outsel_15_we = addr_hit[177] & reg_we & !reg_error; + assign mio_outsel_15_we = addr_hit[181] & reg_we & !reg_error; assign mio_outsel_15_wd = reg_wdata[6:0]; - assign mio_outsel_16_we = addr_hit[178] & reg_we & !reg_error; + assign mio_outsel_16_we = addr_hit[182] & reg_we & !reg_error; assign mio_outsel_16_wd = reg_wdata[6:0]; - assign mio_outsel_17_we = addr_hit[179] & reg_we & !reg_error; + assign mio_outsel_17_we = addr_hit[183] & reg_we & !reg_error; assign mio_outsel_17_wd = reg_wdata[6:0]; - assign mio_outsel_18_we = addr_hit[180] & reg_we & !reg_error; + assign mio_outsel_18_we = addr_hit[184] & reg_we & !reg_error; assign mio_outsel_18_wd = reg_wdata[6:0]; - assign mio_outsel_19_we = addr_hit[181] & reg_we & !reg_error; + assign mio_outsel_19_we = addr_hit[185] & reg_we & !reg_error; assign mio_outsel_19_wd = reg_wdata[6:0]; - assign mio_outsel_20_we = addr_hit[182] & reg_we & !reg_error; + assign mio_outsel_20_we = addr_hit[186] & reg_we & !reg_error; assign mio_outsel_20_wd = reg_wdata[6:0]; - assign mio_outsel_21_we = addr_hit[183] & reg_we & !reg_error; + assign mio_outsel_21_we = addr_hit[187] & reg_we & !reg_error; assign mio_outsel_21_wd = reg_wdata[6:0]; - assign mio_outsel_22_we = addr_hit[184] & reg_we & !reg_error; + assign mio_outsel_22_we = addr_hit[188] & reg_we & !reg_error; assign mio_outsel_22_wd = reg_wdata[6:0]; - assign mio_outsel_23_we = addr_hit[185] & reg_we & !reg_error; + assign mio_outsel_23_we = addr_hit[189] & reg_we & !reg_error; assign mio_outsel_23_wd = reg_wdata[6:0]; - assign mio_outsel_24_we = addr_hit[186] & reg_we & !reg_error; + assign mio_outsel_24_we = addr_hit[190] & reg_we & !reg_error; assign mio_outsel_24_wd = reg_wdata[6:0]; - assign mio_outsel_25_we = addr_hit[187] & reg_we & !reg_error; + assign mio_outsel_25_we = addr_hit[191] & reg_we & !reg_error; assign mio_outsel_25_wd = reg_wdata[6:0]; - assign mio_outsel_26_we = addr_hit[188] & reg_we & !reg_error; + assign mio_outsel_26_we = addr_hit[192] & reg_we & !reg_error; assign mio_outsel_26_wd = reg_wdata[6:0]; - assign mio_outsel_27_we = addr_hit[189] & reg_we & !reg_error; + assign mio_outsel_27_we = addr_hit[193] & reg_we & !reg_error; assign mio_outsel_27_wd = reg_wdata[6:0]; - assign mio_outsel_28_we = addr_hit[190] & reg_we & !reg_error; + assign mio_outsel_28_we = addr_hit[194] & reg_we & !reg_error; assign mio_outsel_28_wd = reg_wdata[6:0]; - assign mio_outsel_29_we = addr_hit[191] & reg_we & !reg_error; + assign mio_outsel_29_we = addr_hit[195] & reg_we & !reg_error; assign mio_outsel_29_wd = reg_wdata[6:0]; - assign mio_outsel_30_we = addr_hit[192] & reg_we & !reg_error; + assign mio_outsel_30_we = addr_hit[196] & reg_we & !reg_error; assign mio_outsel_30_wd = reg_wdata[6:0]; - assign mio_outsel_31_we = addr_hit[193] & reg_we & !reg_error; + assign mio_outsel_31_we = addr_hit[197] & reg_we & !reg_error; assign mio_outsel_31_wd = reg_wdata[6:0]; - assign mio_outsel_32_we = addr_hit[194] & reg_we & !reg_error; + assign mio_outsel_32_we = addr_hit[198] & reg_we & !reg_error; assign mio_outsel_32_wd = reg_wdata[6:0]; - assign mio_outsel_33_we = addr_hit[195] & reg_we & !reg_error; + assign mio_outsel_33_we = addr_hit[199] & reg_we & !reg_error; assign mio_outsel_33_wd = reg_wdata[6:0]; - assign mio_outsel_34_we = addr_hit[196] & reg_we & !reg_error; + assign mio_outsel_34_we = addr_hit[200] & reg_we & !reg_error; assign mio_outsel_34_wd = reg_wdata[6:0]; - assign mio_outsel_35_we = addr_hit[197] & reg_we & !reg_error; + assign mio_outsel_35_we = addr_hit[201] & reg_we & !reg_error; assign mio_outsel_35_wd = reg_wdata[6:0]; - assign mio_outsel_36_we = addr_hit[198] & reg_we & !reg_error; + assign mio_outsel_36_we = addr_hit[202] & reg_we & !reg_error; assign mio_outsel_36_wd = reg_wdata[6:0]; - assign mio_outsel_37_we = addr_hit[199] & reg_we & !reg_error; + assign mio_outsel_37_we = addr_hit[203] & reg_we & !reg_error; assign mio_outsel_37_wd = reg_wdata[6:0]; - assign mio_outsel_38_we = addr_hit[200] & reg_we & !reg_error; + assign mio_outsel_38_we = addr_hit[204] & reg_we & !reg_error; assign mio_outsel_38_wd = reg_wdata[6:0]; - assign mio_outsel_39_we = addr_hit[201] & reg_we & !reg_error; + assign mio_outsel_39_we = addr_hit[205] & reg_we & !reg_error; assign mio_outsel_39_wd = reg_wdata[6:0]; - assign mio_outsel_40_we = addr_hit[202] & reg_we & !reg_error; + assign mio_outsel_40_we = addr_hit[206] & reg_we & !reg_error; assign mio_outsel_40_wd = reg_wdata[6:0]; - assign mio_outsel_41_we = addr_hit[203] & reg_we & !reg_error; + assign mio_outsel_41_we = addr_hit[207] & reg_we & !reg_error; assign mio_outsel_41_wd = reg_wdata[6:0]; - assign mio_outsel_42_we = addr_hit[204] & reg_we & !reg_error; + assign mio_outsel_42_we = addr_hit[208] & reg_we & !reg_error; assign mio_outsel_42_wd = reg_wdata[6:0]; - assign mio_outsel_43_we = addr_hit[205] & reg_we & !reg_error; + assign mio_outsel_43_we = addr_hit[209] & reg_we & !reg_error; assign mio_outsel_43_wd = reg_wdata[6:0]; - assign mio_outsel_44_we = addr_hit[206] & reg_we & !reg_error; + assign mio_outsel_44_we = addr_hit[210] & reg_we & !reg_error; assign mio_outsel_44_wd = reg_wdata[6:0]; - assign mio_outsel_45_we = addr_hit[207] & reg_we & !reg_error; + assign mio_outsel_45_we = addr_hit[211] & reg_we & !reg_error; assign mio_outsel_45_wd = reg_wdata[6:0]; - assign mio_outsel_46_we = addr_hit[208] & reg_we & !reg_error; + assign mio_outsel_46_we = addr_hit[212] & reg_we & !reg_error; assign mio_outsel_46_wd = reg_wdata[6:0]; - assign mio_pad_attr_regwen_0_we = addr_hit[209] & reg_we & !reg_error; + assign mio_pad_attr_regwen_0_we = addr_hit[213] & reg_we & !reg_error; assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_1_we = addr_hit[210] & reg_we & !reg_error; + assign mio_pad_attr_regwen_1_we = addr_hit[214] & reg_we & !reg_error; assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_2_we = addr_hit[211] & reg_we & !reg_error; + assign mio_pad_attr_regwen_2_we = addr_hit[215] & reg_we & !reg_error; assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_3_we = addr_hit[212] & reg_we & !reg_error; + assign mio_pad_attr_regwen_3_we = addr_hit[216] & reg_we & !reg_error; assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_4_we = addr_hit[213] & reg_we & !reg_error; + assign mio_pad_attr_regwen_4_we = addr_hit[217] & reg_we & !reg_error; assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_5_we = addr_hit[214] & reg_we & !reg_error; + assign mio_pad_attr_regwen_5_we = addr_hit[218] & reg_we & !reg_error; assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_6_we = addr_hit[215] & reg_we & !reg_error; + assign mio_pad_attr_regwen_6_we = addr_hit[219] & reg_we & !reg_error; assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_7_we = addr_hit[216] & reg_we & !reg_error; + assign mio_pad_attr_regwen_7_we = addr_hit[220] & reg_we & !reg_error; assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_8_we = addr_hit[217] & reg_we & !reg_error; + assign mio_pad_attr_regwen_8_we = addr_hit[221] & reg_we & !reg_error; assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_9_we = addr_hit[218] & reg_we & !reg_error; + assign mio_pad_attr_regwen_9_we = addr_hit[222] & reg_we & !reg_error; assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_10_we = addr_hit[219] & reg_we & !reg_error; + assign mio_pad_attr_regwen_10_we = addr_hit[223] & reg_we & !reg_error; assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_11_we = addr_hit[220] & reg_we & !reg_error; + assign mio_pad_attr_regwen_11_we = addr_hit[224] & reg_we & !reg_error; assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_12_we = addr_hit[221] & reg_we & !reg_error; + assign mio_pad_attr_regwen_12_we = addr_hit[225] & reg_we & !reg_error; assign mio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_13_we = addr_hit[222] & reg_we & !reg_error; + assign mio_pad_attr_regwen_13_we = addr_hit[226] & reg_we & !reg_error; assign mio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_14_we = addr_hit[223] & reg_we & !reg_error; + assign mio_pad_attr_regwen_14_we = addr_hit[227] & reg_we & !reg_error; assign mio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_15_we = addr_hit[224] & reg_we & !reg_error; + assign mio_pad_attr_regwen_15_we = addr_hit[228] & reg_we & !reg_error; assign mio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_16_we = addr_hit[225] & reg_we & !reg_error; + assign mio_pad_attr_regwen_16_we = addr_hit[229] & reg_we & !reg_error; assign mio_pad_attr_regwen_16_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_17_we = addr_hit[226] & reg_we & !reg_error; + assign mio_pad_attr_regwen_17_we = addr_hit[230] & reg_we & !reg_error; assign mio_pad_attr_regwen_17_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_18_we = addr_hit[227] & reg_we & !reg_error; + assign mio_pad_attr_regwen_18_we = addr_hit[231] & reg_we & !reg_error; assign mio_pad_attr_regwen_18_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_19_we = addr_hit[228] & reg_we & !reg_error; + assign mio_pad_attr_regwen_19_we = addr_hit[232] & reg_we & !reg_error; assign mio_pad_attr_regwen_19_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_20_we = addr_hit[229] & reg_we & !reg_error; + assign mio_pad_attr_regwen_20_we = addr_hit[233] & reg_we & !reg_error; assign mio_pad_attr_regwen_20_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_21_we = addr_hit[230] & reg_we & !reg_error; + assign mio_pad_attr_regwen_21_we = addr_hit[234] & reg_we & !reg_error; assign mio_pad_attr_regwen_21_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_22_we = addr_hit[231] & reg_we & !reg_error; + assign mio_pad_attr_regwen_22_we = addr_hit[235] & reg_we & !reg_error; assign mio_pad_attr_regwen_22_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_23_we = addr_hit[232] & reg_we & !reg_error; + assign mio_pad_attr_regwen_23_we = addr_hit[236] & reg_we & !reg_error; assign mio_pad_attr_regwen_23_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_24_we = addr_hit[233] & reg_we & !reg_error; + assign mio_pad_attr_regwen_24_we = addr_hit[237] & reg_we & !reg_error; assign mio_pad_attr_regwen_24_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_25_we = addr_hit[234] & reg_we & !reg_error; + assign mio_pad_attr_regwen_25_we = addr_hit[238] & reg_we & !reg_error; assign mio_pad_attr_regwen_25_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_26_we = addr_hit[235] & reg_we & !reg_error; + assign mio_pad_attr_regwen_26_we = addr_hit[239] & reg_we & !reg_error; assign mio_pad_attr_regwen_26_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_27_we = addr_hit[236] & reg_we & !reg_error; + assign mio_pad_attr_regwen_27_we = addr_hit[240] & reg_we & !reg_error; assign mio_pad_attr_regwen_27_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_28_we = addr_hit[237] & reg_we & !reg_error; + assign mio_pad_attr_regwen_28_we = addr_hit[241] & reg_we & !reg_error; assign mio_pad_attr_regwen_28_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_29_we = addr_hit[238] & reg_we & !reg_error; + assign mio_pad_attr_regwen_29_we = addr_hit[242] & reg_we & !reg_error; assign mio_pad_attr_regwen_29_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_30_we = addr_hit[239] & reg_we & !reg_error; + assign mio_pad_attr_regwen_30_we = addr_hit[243] & reg_we & !reg_error; assign mio_pad_attr_regwen_30_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_31_we = addr_hit[240] & reg_we & !reg_error; + assign mio_pad_attr_regwen_31_we = addr_hit[244] & reg_we & !reg_error; assign mio_pad_attr_regwen_31_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_32_we = addr_hit[241] & reg_we & !reg_error; + assign mio_pad_attr_regwen_32_we = addr_hit[245] & reg_we & !reg_error; assign mio_pad_attr_regwen_32_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_33_we = addr_hit[242] & reg_we & !reg_error; + assign mio_pad_attr_regwen_33_we = addr_hit[246] & reg_we & !reg_error; assign mio_pad_attr_regwen_33_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_34_we = addr_hit[243] & reg_we & !reg_error; + assign mio_pad_attr_regwen_34_we = addr_hit[247] & reg_we & !reg_error; assign mio_pad_attr_regwen_34_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_35_we = addr_hit[244] & reg_we & !reg_error; + assign mio_pad_attr_regwen_35_we = addr_hit[248] & reg_we & !reg_error; assign mio_pad_attr_regwen_35_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_36_we = addr_hit[245] & reg_we & !reg_error; + assign mio_pad_attr_regwen_36_we = addr_hit[249] & reg_we & !reg_error; assign mio_pad_attr_regwen_36_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_37_we = addr_hit[246] & reg_we & !reg_error; + assign mio_pad_attr_regwen_37_we = addr_hit[250] & reg_we & !reg_error; assign mio_pad_attr_regwen_37_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_38_we = addr_hit[247] & reg_we & !reg_error; + assign mio_pad_attr_regwen_38_we = addr_hit[251] & reg_we & !reg_error; assign mio_pad_attr_regwen_38_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_39_we = addr_hit[248] & reg_we & !reg_error; + assign mio_pad_attr_regwen_39_we = addr_hit[252] & reg_we & !reg_error; assign mio_pad_attr_regwen_39_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_40_we = addr_hit[249] & reg_we & !reg_error; + assign mio_pad_attr_regwen_40_we = addr_hit[253] & reg_we & !reg_error; assign mio_pad_attr_regwen_40_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_41_we = addr_hit[250] & reg_we & !reg_error; + assign mio_pad_attr_regwen_41_we = addr_hit[254] & reg_we & !reg_error; assign mio_pad_attr_regwen_41_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_42_we = addr_hit[251] & reg_we & !reg_error; + assign mio_pad_attr_regwen_42_we = addr_hit[255] & reg_we & !reg_error; assign mio_pad_attr_regwen_42_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_43_we = addr_hit[252] & reg_we & !reg_error; + assign mio_pad_attr_regwen_43_we = addr_hit[256] & reg_we & !reg_error; assign mio_pad_attr_regwen_43_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_44_we = addr_hit[253] & reg_we & !reg_error; + assign mio_pad_attr_regwen_44_we = addr_hit[257] & reg_we & !reg_error; assign mio_pad_attr_regwen_44_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_45_we = addr_hit[254] & reg_we & !reg_error; + assign mio_pad_attr_regwen_45_we = addr_hit[258] & reg_we & !reg_error; assign mio_pad_attr_regwen_45_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_46_we = addr_hit[255] & reg_we & !reg_error; + assign mio_pad_attr_regwen_46_we = addr_hit[259] & reg_we & !reg_error; assign mio_pad_attr_regwen_46_wd = reg_wdata[0]; - assign mio_pad_attr_0_re = addr_hit[256] & reg_re & !reg_error; - assign mio_pad_attr_0_we = addr_hit[256] & reg_we & !reg_error; + assign mio_pad_attr_0_re = addr_hit[260] & reg_re & !reg_error; + assign mio_pad_attr_0_we = addr_hit[260] & reg_we & !reg_error; assign mio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -33330,8 +33484,8 @@ module pinmux_reg_top ( assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign mio_pad_attr_1_re = addr_hit[257] & reg_re & !reg_error; - assign mio_pad_attr_1_we = addr_hit[257] & reg_we & !reg_error; + assign mio_pad_attr_1_re = addr_hit[261] & reg_re & !reg_error; + assign mio_pad_attr_1_we = addr_hit[261] & reg_we & !reg_error; assign mio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -33350,8 +33504,8 @@ module pinmux_reg_top ( assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign mio_pad_attr_2_re = addr_hit[258] & reg_re & !reg_error; - assign mio_pad_attr_2_we = addr_hit[258] & reg_we & !reg_error; + assign mio_pad_attr_2_re = addr_hit[262] & reg_re & !reg_error; + assign mio_pad_attr_2_we = addr_hit[262] & reg_we & !reg_error; assign mio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -33370,8 +33524,8 @@ module pinmux_reg_top ( assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign mio_pad_attr_3_re = addr_hit[259] & reg_re & !reg_error; - assign mio_pad_attr_3_we = addr_hit[259] & reg_we & !reg_error; + assign mio_pad_attr_3_re = addr_hit[263] & reg_re & !reg_error; + assign mio_pad_attr_3_we = addr_hit[263] & reg_we & !reg_error; assign mio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -33390,8 +33544,8 @@ module pinmux_reg_top ( assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign mio_pad_attr_4_re = addr_hit[260] & reg_re & !reg_error; - assign mio_pad_attr_4_we = addr_hit[260] & reg_we & !reg_error; + assign mio_pad_attr_4_re = addr_hit[264] & reg_re & !reg_error; + assign mio_pad_attr_4_we = addr_hit[264] & reg_we & !reg_error; assign mio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -33410,8 +33564,8 @@ module pinmux_reg_top ( assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign mio_pad_attr_5_re = addr_hit[261] & reg_re & !reg_error; - assign mio_pad_attr_5_we = addr_hit[261] & reg_we & !reg_error; + assign mio_pad_attr_5_re = addr_hit[265] & reg_re & !reg_error; + assign mio_pad_attr_5_we = addr_hit[265] & reg_we & !reg_error; assign mio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -33430,8 +33584,8 @@ module pinmux_reg_top ( assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign mio_pad_attr_6_re = addr_hit[262] & reg_re & !reg_error; - assign mio_pad_attr_6_we = addr_hit[262] & reg_we & !reg_error; + assign mio_pad_attr_6_re = addr_hit[266] & reg_re & !reg_error; + assign mio_pad_attr_6_we = addr_hit[266] & reg_we & !reg_error; assign mio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -33450,8 +33604,8 @@ module pinmux_reg_top ( assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign mio_pad_attr_7_re = addr_hit[263] & reg_re & !reg_error; - assign mio_pad_attr_7_we = addr_hit[263] & reg_we & !reg_error; + assign mio_pad_attr_7_re = addr_hit[267] & reg_re & !reg_error; + assign mio_pad_attr_7_we = addr_hit[267] & reg_we & !reg_error; assign mio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -33470,8 +33624,8 @@ module pinmux_reg_top ( assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign mio_pad_attr_8_re = addr_hit[264] & reg_re & !reg_error; - assign mio_pad_attr_8_we = addr_hit[264] & reg_we & !reg_error; + assign mio_pad_attr_8_re = addr_hit[268] & reg_re & !reg_error; + assign mio_pad_attr_8_we = addr_hit[268] & reg_we & !reg_error; assign mio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -33490,8 +33644,8 @@ module pinmux_reg_top ( assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign mio_pad_attr_9_re = addr_hit[265] & reg_re & !reg_error; - assign mio_pad_attr_9_we = addr_hit[265] & reg_we & !reg_error; + assign mio_pad_attr_9_re = addr_hit[269] & reg_re & !reg_error; + assign mio_pad_attr_9_we = addr_hit[269] & reg_we & !reg_error; assign mio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -33510,8 +33664,8 @@ module pinmux_reg_top ( assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign mio_pad_attr_10_re = addr_hit[266] & reg_re & !reg_error; - assign mio_pad_attr_10_we = addr_hit[266] & reg_we & !reg_error; + assign mio_pad_attr_10_re = addr_hit[270] & reg_re & !reg_error; + assign mio_pad_attr_10_we = addr_hit[270] & reg_we & !reg_error; assign mio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -33530,8 +33684,8 @@ module pinmux_reg_top ( assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign mio_pad_attr_11_re = addr_hit[267] & reg_re & !reg_error; - assign mio_pad_attr_11_we = addr_hit[267] & reg_we & !reg_error; + assign mio_pad_attr_11_re = addr_hit[271] & reg_re & !reg_error; + assign mio_pad_attr_11_we = addr_hit[271] & reg_we & !reg_error; assign mio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -33550,8 +33704,8 @@ module pinmux_reg_top ( assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign mio_pad_attr_12_re = addr_hit[268] & reg_re & !reg_error; - assign mio_pad_attr_12_we = addr_hit[268] & reg_we & !reg_error; + assign mio_pad_attr_12_re = addr_hit[272] & reg_re & !reg_error; + assign mio_pad_attr_12_we = addr_hit[272] & reg_we & !reg_error; assign mio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -33570,8 +33724,8 @@ module pinmux_reg_top ( assign mio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign mio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign mio_pad_attr_13_re = addr_hit[269] & reg_re & !reg_error; - assign mio_pad_attr_13_we = addr_hit[269] & reg_we & !reg_error; + assign mio_pad_attr_13_re = addr_hit[273] & reg_re & !reg_error; + assign mio_pad_attr_13_we = addr_hit[273] & reg_we & !reg_error; assign mio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -33590,8 +33744,8 @@ module pinmux_reg_top ( assign mio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign mio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign mio_pad_attr_14_re = addr_hit[270] & reg_re & !reg_error; - assign mio_pad_attr_14_we = addr_hit[270] & reg_we & !reg_error; + assign mio_pad_attr_14_re = addr_hit[274] & reg_re & !reg_error; + assign mio_pad_attr_14_we = addr_hit[274] & reg_we & !reg_error; assign mio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -33610,8 +33764,8 @@ module pinmux_reg_top ( assign mio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign mio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign mio_pad_attr_15_re = addr_hit[271] & reg_re & !reg_error; - assign mio_pad_attr_15_we = addr_hit[271] & reg_we & !reg_error; + assign mio_pad_attr_15_re = addr_hit[275] & reg_re & !reg_error; + assign mio_pad_attr_15_we = addr_hit[275] & reg_we & !reg_error; assign mio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -33630,8 +33784,8 @@ module pinmux_reg_top ( assign mio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign mio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_attr_16_re = addr_hit[272] & reg_re & !reg_error; - assign mio_pad_attr_16_we = addr_hit[272] & reg_we & !reg_error; + assign mio_pad_attr_16_re = addr_hit[276] & reg_re & !reg_error; + assign mio_pad_attr_16_we = addr_hit[276] & reg_we & !reg_error; assign mio_pad_attr_16_invert_16_wd = reg_wdata[0]; @@ -33650,8 +33804,8 @@ module pinmux_reg_top ( assign mio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; assign mio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; - assign mio_pad_attr_17_re = addr_hit[273] & reg_re & !reg_error; - assign mio_pad_attr_17_we = addr_hit[273] & reg_we & !reg_error; + assign mio_pad_attr_17_re = addr_hit[277] & reg_re & !reg_error; + assign mio_pad_attr_17_we = addr_hit[277] & reg_we & !reg_error; assign mio_pad_attr_17_invert_17_wd = reg_wdata[0]; @@ -33670,8 +33824,8 @@ module pinmux_reg_top ( assign mio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; assign mio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; - assign mio_pad_attr_18_re = addr_hit[274] & reg_re & !reg_error; - assign mio_pad_attr_18_we = addr_hit[274] & reg_we & !reg_error; + assign mio_pad_attr_18_re = addr_hit[278] & reg_re & !reg_error; + assign mio_pad_attr_18_we = addr_hit[278] & reg_we & !reg_error; assign mio_pad_attr_18_invert_18_wd = reg_wdata[0]; @@ -33690,8 +33844,8 @@ module pinmux_reg_top ( assign mio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; assign mio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; - assign mio_pad_attr_19_re = addr_hit[275] & reg_re & !reg_error; - assign mio_pad_attr_19_we = addr_hit[275] & reg_we & !reg_error; + assign mio_pad_attr_19_re = addr_hit[279] & reg_re & !reg_error; + assign mio_pad_attr_19_we = addr_hit[279] & reg_we & !reg_error; assign mio_pad_attr_19_invert_19_wd = reg_wdata[0]; @@ -33710,8 +33864,8 @@ module pinmux_reg_top ( assign mio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; assign mio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; - assign mio_pad_attr_20_re = addr_hit[276] & reg_re & !reg_error; - assign mio_pad_attr_20_we = addr_hit[276] & reg_we & !reg_error; + assign mio_pad_attr_20_re = addr_hit[280] & reg_re & !reg_error; + assign mio_pad_attr_20_we = addr_hit[280] & reg_we & !reg_error; assign mio_pad_attr_20_invert_20_wd = reg_wdata[0]; @@ -33730,8 +33884,8 @@ module pinmux_reg_top ( assign mio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; assign mio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; - assign mio_pad_attr_21_re = addr_hit[277] & reg_re & !reg_error; - assign mio_pad_attr_21_we = addr_hit[277] & reg_we & !reg_error; + assign mio_pad_attr_21_re = addr_hit[281] & reg_re & !reg_error; + assign mio_pad_attr_21_we = addr_hit[281] & reg_we & !reg_error; assign mio_pad_attr_21_invert_21_wd = reg_wdata[0]; @@ -33750,8 +33904,8 @@ module pinmux_reg_top ( assign mio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; assign mio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; - assign mio_pad_attr_22_re = addr_hit[278] & reg_re & !reg_error; - assign mio_pad_attr_22_we = addr_hit[278] & reg_we & !reg_error; + assign mio_pad_attr_22_re = addr_hit[282] & reg_re & !reg_error; + assign mio_pad_attr_22_we = addr_hit[282] & reg_we & !reg_error; assign mio_pad_attr_22_invert_22_wd = reg_wdata[0]; @@ -33770,8 +33924,8 @@ module pinmux_reg_top ( assign mio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; assign mio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; - assign mio_pad_attr_23_re = addr_hit[279] & reg_re & !reg_error; - assign mio_pad_attr_23_we = addr_hit[279] & reg_we & !reg_error; + assign mio_pad_attr_23_re = addr_hit[283] & reg_re & !reg_error; + assign mio_pad_attr_23_we = addr_hit[283] & reg_we & !reg_error; assign mio_pad_attr_23_invert_23_wd = reg_wdata[0]; @@ -33790,8 +33944,8 @@ module pinmux_reg_top ( assign mio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; assign mio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; - assign mio_pad_attr_24_re = addr_hit[280] & reg_re & !reg_error; - assign mio_pad_attr_24_we = addr_hit[280] & reg_we & !reg_error; + assign mio_pad_attr_24_re = addr_hit[284] & reg_re & !reg_error; + assign mio_pad_attr_24_we = addr_hit[284] & reg_we & !reg_error; assign mio_pad_attr_24_invert_24_wd = reg_wdata[0]; @@ -33810,8 +33964,8 @@ module pinmux_reg_top ( assign mio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; assign mio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; - assign mio_pad_attr_25_re = addr_hit[281] & reg_re & !reg_error; - assign mio_pad_attr_25_we = addr_hit[281] & reg_we & !reg_error; + assign mio_pad_attr_25_re = addr_hit[285] & reg_re & !reg_error; + assign mio_pad_attr_25_we = addr_hit[285] & reg_we & !reg_error; assign mio_pad_attr_25_invert_25_wd = reg_wdata[0]; @@ -33830,8 +33984,8 @@ module pinmux_reg_top ( assign mio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; assign mio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; - assign mio_pad_attr_26_re = addr_hit[282] & reg_re & !reg_error; - assign mio_pad_attr_26_we = addr_hit[282] & reg_we & !reg_error; + assign mio_pad_attr_26_re = addr_hit[286] & reg_re & !reg_error; + assign mio_pad_attr_26_we = addr_hit[286] & reg_we & !reg_error; assign mio_pad_attr_26_invert_26_wd = reg_wdata[0]; @@ -33850,8 +34004,8 @@ module pinmux_reg_top ( assign mio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; assign mio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; - assign mio_pad_attr_27_re = addr_hit[283] & reg_re & !reg_error; - assign mio_pad_attr_27_we = addr_hit[283] & reg_we & !reg_error; + assign mio_pad_attr_27_re = addr_hit[287] & reg_re & !reg_error; + assign mio_pad_attr_27_we = addr_hit[287] & reg_we & !reg_error; assign mio_pad_attr_27_invert_27_wd = reg_wdata[0]; @@ -33870,8 +34024,8 @@ module pinmux_reg_top ( assign mio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; assign mio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; - assign mio_pad_attr_28_re = addr_hit[284] & reg_re & !reg_error; - assign mio_pad_attr_28_we = addr_hit[284] & reg_we & !reg_error; + assign mio_pad_attr_28_re = addr_hit[288] & reg_re & !reg_error; + assign mio_pad_attr_28_we = addr_hit[288] & reg_we & !reg_error; assign mio_pad_attr_28_invert_28_wd = reg_wdata[0]; @@ -33890,8 +34044,8 @@ module pinmux_reg_top ( assign mio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; assign mio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; - assign mio_pad_attr_29_re = addr_hit[285] & reg_re & !reg_error; - assign mio_pad_attr_29_we = addr_hit[285] & reg_we & !reg_error; + assign mio_pad_attr_29_re = addr_hit[289] & reg_re & !reg_error; + assign mio_pad_attr_29_we = addr_hit[289] & reg_we & !reg_error; assign mio_pad_attr_29_invert_29_wd = reg_wdata[0]; @@ -33910,8 +34064,8 @@ module pinmux_reg_top ( assign mio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; assign mio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; - assign mio_pad_attr_30_re = addr_hit[286] & reg_re & !reg_error; - assign mio_pad_attr_30_we = addr_hit[286] & reg_we & !reg_error; + assign mio_pad_attr_30_re = addr_hit[290] & reg_re & !reg_error; + assign mio_pad_attr_30_we = addr_hit[290] & reg_we & !reg_error; assign mio_pad_attr_30_invert_30_wd = reg_wdata[0]; @@ -33930,8 +34084,8 @@ module pinmux_reg_top ( assign mio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; assign mio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; - assign mio_pad_attr_31_re = addr_hit[287] & reg_re & !reg_error; - assign mio_pad_attr_31_we = addr_hit[287] & reg_we & !reg_error; + assign mio_pad_attr_31_re = addr_hit[291] & reg_re & !reg_error; + assign mio_pad_attr_31_we = addr_hit[291] & reg_we & !reg_error; assign mio_pad_attr_31_invert_31_wd = reg_wdata[0]; @@ -33950,8 +34104,8 @@ module pinmux_reg_top ( assign mio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; assign mio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; - assign mio_pad_attr_32_re = addr_hit[288] & reg_re & !reg_error; - assign mio_pad_attr_32_we = addr_hit[288] & reg_we & !reg_error; + assign mio_pad_attr_32_re = addr_hit[292] & reg_re & !reg_error; + assign mio_pad_attr_32_we = addr_hit[292] & reg_we & !reg_error; assign mio_pad_attr_32_invert_32_wd = reg_wdata[0]; @@ -33970,8 +34124,8 @@ module pinmux_reg_top ( assign mio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; assign mio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; - assign mio_pad_attr_33_re = addr_hit[289] & reg_re & !reg_error; - assign mio_pad_attr_33_we = addr_hit[289] & reg_we & !reg_error; + assign mio_pad_attr_33_re = addr_hit[293] & reg_re & !reg_error; + assign mio_pad_attr_33_we = addr_hit[293] & reg_we & !reg_error; assign mio_pad_attr_33_invert_33_wd = reg_wdata[0]; @@ -33990,8 +34144,8 @@ module pinmux_reg_top ( assign mio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; assign mio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; - assign mio_pad_attr_34_re = addr_hit[290] & reg_re & !reg_error; - assign mio_pad_attr_34_we = addr_hit[290] & reg_we & !reg_error; + assign mio_pad_attr_34_re = addr_hit[294] & reg_re & !reg_error; + assign mio_pad_attr_34_we = addr_hit[294] & reg_we & !reg_error; assign mio_pad_attr_34_invert_34_wd = reg_wdata[0]; @@ -34010,8 +34164,8 @@ module pinmux_reg_top ( assign mio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; assign mio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; - assign mio_pad_attr_35_re = addr_hit[291] & reg_re & !reg_error; - assign mio_pad_attr_35_we = addr_hit[291] & reg_we & !reg_error; + assign mio_pad_attr_35_re = addr_hit[295] & reg_re & !reg_error; + assign mio_pad_attr_35_we = addr_hit[295] & reg_we & !reg_error; assign mio_pad_attr_35_invert_35_wd = reg_wdata[0]; @@ -34030,8 +34184,8 @@ module pinmux_reg_top ( assign mio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; assign mio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; - assign mio_pad_attr_36_re = addr_hit[292] & reg_re & !reg_error; - assign mio_pad_attr_36_we = addr_hit[292] & reg_we & !reg_error; + assign mio_pad_attr_36_re = addr_hit[296] & reg_re & !reg_error; + assign mio_pad_attr_36_we = addr_hit[296] & reg_we & !reg_error; assign mio_pad_attr_36_invert_36_wd = reg_wdata[0]; @@ -34050,8 +34204,8 @@ module pinmux_reg_top ( assign mio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; assign mio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; - assign mio_pad_attr_37_re = addr_hit[293] & reg_re & !reg_error; - assign mio_pad_attr_37_we = addr_hit[293] & reg_we & !reg_error; + assign mio_pad_attr_37_re = addr_hit[297] & reg_re & !reg_error; + assign mio_pad_attr_37_we = addr_hit[297] & reg_we & !reg_error; assign mio_pad_attr_37_invert_37_wd = reg_wdata[0]; @@ -34070,8 +34224,8 @@ module pinmux_reg_top ( assign mio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; assign mio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; - assign mio_pad_attr_38_re = addr_hit[294] & reg_re & !reg_error; - assign mio_pad_attr_38_we = addr_hit[294] & reg_we & !reg_error; + assign mio_pad_attr_38_re = addr_hit[298] & reg_re & !reg_error; + assign mio_pad_attr_38_we = addr_hit[298] & reg_we & !reg_error; assign mio_pad_attr_38_invert_38_wd = reg_wdata[0]; @@ -34090,8 +34244,8 @@ module pinmux_reg_top ( assign mio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; assign mio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; - assign mio_pad_attr_39_re = addr_hit[295] & reg_re & !reg_error; - assign mio_pad_attr_39_we = addr_hit[295] & reg_we & !reg_error; + assign mio_pad_attr_39_re = addr_hit[299] & reg_re & !reg_error; + assign mio_pad_attr_39_we = addr_hit[299] & reg_we & !reg_error; assign mio_pad_attr_39_invert_39_wd = reg_wdata[0]; @@ -34110,8 +34264,8 @@ module pinmux_reg_top ( assign mio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; assign mio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; - assign mio_pad_attr_40_re = addr_hit[296] & reg_re & !reg_error; - assign mio_pad_attr_40_we = addr_hit[296] & reg_we & !reg_error; + assign mio_pad_attr_40_re = addr_hit[300] & reg_re & !reg_error; + assign mio_pad_attr_40_we = addr_hit[300] & reg_we & !reg_error; assign mio_pad_attr_40_invert_40_wd = reg_wdata[0]; @@ -34130,8 +34284,8 @@ module pinmux_reg_top ( assign mio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; assign mio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; - assign mio_pad_attr_41_re = addr_hit[297] & reg_re & !reg_error; - assign mio_pad_attr_41_we = addr_hit[297] & reg_we & !reg_error; + assign mio_pad_attr_41_re = addr_hit[301] & reg_re & !reg_error; + assign mio_pad_attr_41_we = addr_hit[301] & reg_we & !reg_error; assign mio_pad_attr_41_invert_41_wd = reg_wdata[0]; @@ -34150,8 +34304,8 @@ module pinmux_reg_top ( assign mio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; assign mio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; - assign mio_pad_attr_42_re = addr_hit[298] & reg_re & !reg_error; - assign mio_pad_attr_42_we = addr_hit[298] & reg_we & !reg_error; + assign mio_pad_attr_42_re = addr_hit[302] & reg_re & !reg_error; + assign mio_pad_attr_42_we = addr_hit[302] & reg_we & !reg_error; assign mio_pad_attr_42_invert_42_wd = reg_wdata[0]; @@ -34170,8 +34324,8 @@ module pinmux_reg_top ( assign mio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; assign mio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; - assign mio_pad_attr_43_re = addr_hit[299] & reg_re & !reg_error; - assign mio_pad_attr_43_we = addr_hit[299] & reg_we & !reg_error; + assign mio_pad_attr_43_re = addr_hit[303] & reg_re & !reg_error; + assign mio_pad_attr_43_we = addr_hit[303] & reg_we & !reg_error; assign mio_pad_attr_43_invert_43_wd = reg_wdata[0]; @@ -34190,8 +34344,8 @@ module pinmux_reg_top ( assign mio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16]; assign mio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20]; - assign mio_pad_attr_44_re = addr_hit[300] & reg_re & !reg_error; - assign mio_pad_attr_44_we = addr_hit[300] & reg_we & !reg_error; + assign mio_pad_attr_44_re = addr_hit[304] & reg_re & !reg_error; + assign mio_pad_attr_44_we = addr_hit[304] & reg_we & !reg_error; assign mio_pad_attr_44_invert_44_wd = reg_wdata[0]; @@ -34210,8 +34364,8 @@ module pinmux_reg_top ( assign mio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16]; assign mio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20]; - assign mio_pad_attr_45_re = addr_hit[301] & reg_re & !reg_error; - assign mio_pad_attr_45_we = addr_hit[301] & reg_we & !reg_error; + assign mio_pad_attr_45_re = addr_hit[305] & reg_re & !reg_error; + assign mio_pad_attr_45_we = addr_hit[305] & reg_we & !reg_error; assign mio_pad_attr_45_invert_45_wd = reg_wdata[0]; @@ -34230,8 +34384,8 @@ module pinmux_reg_top ( assign mio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16]; assign mio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20]; - assign mio_pad_attr_46_re = addr_hit[302] & reg_re & !reg_error; - assign mio_pad_attr_46_we = addr_hit[302] & reg_we & !reg_error; + assign mio_pad_attr_46_re = addr_hit[306] & reg_re & !reg_error; + assign mio_pad_attr_46_we = addr_hit[306] & reg_we & !reg_error; assign mio_pad_attr_46_invert_46_wd = reg_wdata[0]; @@ -34250,56 +34404,56 @@ module pinmux_reg_top ( assign mio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16]; assign mio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20]; - assign dio_pad_attr_regwen_0_we = addr_hit[303] & reg_we & !reg_error; + assign dio_pad_attr_regwen_0_we = addr_hit[307] & reg_we & !reg_error; assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_1_we = addr_hit[304] & reg_we & !reg_error; + assign dio_pad_attr_regwen_1_we = addr_hit[308] & reg_we & !reg_error; assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_2_we = addr_hit[305] & reg_we & !reg_error; + assign dio_pad_attr_regwen_2_we = addr_hit[309] & reg_we & !reg_error; assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_3_we = addr_hit[306] & reg_we & !reg_error; + assign dio_pad_attr_regwen_3_we = addr_hit[310] & reg_we & !reg_error; assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_4_we = addr_hit[307] & reg_we & !reg_error; + assign dio_pad_attr_regwen_4_we = addr_hit[311] & reg_we & !reg_error; assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_5_we = addr_hit[308] & reg_we & !reg_error; + assign dio_pad_attr_regwen_5_we = addr_hit[312] & reg_we & !reg_error; assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_6_we = addr_hit[309] & reg_we & !reg_error; + assign dio_pad_attr_regwen_6_we = addr_hit[313] & reg_we & !reg_error; assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_7_we = addr_hit[310] & reg_we & !reg_error; + assign dio_pad_attr_regwen_7_we = addr_hit[314] & reg_we & !reg_error; assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_8_we = addr_hit[311] & reg_we & !reg_error; + assign dio_pad_attr_regwen_8_we = addr_hit[315] & reg_we & !reg_error; assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_9_we = addr_hit[312] & reg_we & !reg_error; + assign dio_pad_attr_regwen_9_we = addr_hit[316] & reg_we & !reg_error; assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_10_we = addr_hit[313] & reg_we & !reg_error; + assign dio_pad_attr_regwen_10_we = addr_hit[317] & reg_we & !reg_error; assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_11_we = addr_hit[314] & reg_we & !reg_error; + assign dio_pad_attr_regwen_11_we = addr_hit[318] & reg_we & !reg_error; assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_12_we = addr_hit[315] & reg_we & !reg_error; + assign dio_pad_attr_regwen_12_we = addr_hit[319] & reg_we & !reg_error; assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_13_we = addr_hit[316] & reg_we & !reg_error; + assign dio_pad_attr_regwen_13_we = addr_hit[320] & reg_we & !reg_error; assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_14_we = addr_hit[317] & reg_we & !reg_error; + assign dio_pad_attr_regwen_14_we = addr_hit[321] & reg_we & !reg_error; assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_15_we = addr_hit[318] & reg_we & !reg_error; + assign dio_pad_attr_regwen_15_we = addr_hit[322] & reg_we & !reg_error; assign dio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign dio_pad_attr_0_re = addr_hit[319] & reg_re & !reg_error; - assign dio_pad_attr_0_we = addr_hit[319] & reg_we & !reg_error; + assign dio_pad_attr_0_re = addr_hit[323] & reg_re & !reg_error; + assign dio_pad_attr_0_we = addr_hit[323] & reg_we & !reg_error; assign dio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -34318,8 +34472,8 @@ module pinmux_reg_top ( assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign dio_pad_attr_1_re = addr_hit[320] & reg_re & !reg_error; - assign dio_pad_attr_1_we = addr_hit[320] & reg_we & !reg_error; + assign dio_pad_attr_1_re = addr_hit[324] & reg_re & !reg_error; + assign dio_pad_attr_1_we = addr_hit[324] & reg_we & !reg_error; assign dio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -34338,8 +34492,8 @@ module pinmux_reg_top ( assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign dio_pad_attr_2_re = addr_hit[321] & reg_re & !reg_error; - assign dio_pad_attr_2_we = addr_hit[321] & reg_we & !reg_error; + assign dio_pad_attr_2_re = addr_hit[325] & reg_re & !reg_error; + assign dio_pad_attr_2_we = addr_hit[325] & reg_we & !reg_error; assign dio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -34358,8 +34512,8 @@ module pinmux_reg_top ( assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign dio_pad_attr_3_re = addr_hit[322] & reg_re & !reg_error; - assign dio_pad_attr_3_we = addr_hit[322] & reg_we & !reg_error; + assign dio_pad_attr_3_re = addr_hit[326] & reg_re & !reg_error; + assign dio_pad_attr_3_we = addr_hit[326] & reg_we & !reg_error; assign dio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -34378,8 +34532,8 @@ module pinmux_reg_top ( assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign dio_pad_attr_4_re = addr_hit[323] & reg_re & !reg_error; - assign dio_pad_attr_4_we = addr_hit[323] & reg_we & !reg_error; + assign dio_pad_attr_4_re = addr_hit[327] & reg_re & !reg_error; + assign dio_pad_attr_4_we = addr_hit[327] & reg_we & !reg_error; assign dio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -34398,8 +34552,8 @@ module pinmux_reg_top ( assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign dio_pad_attr_5_re = addr_hit[324] & reg_re & !reg_error; - assign dio_pad_attr_5_we = addr_hit[324] & reg_we & !reg_error; + assign dio_pad_attr_5_re = addr_hit[328] & reg_re & !reg_error; + assign dio_pad_attr_5_we = addr_hit[328] & reg_we & !reg_error; assign dio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -34418,8 +34572,8 @@ module pinmux_reg_top ( assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign dio_pad_attr_6_re = addr_hit[325] & reg_re & !reg_error; - assign dio_pad_attr_6_we = addr_hit[325] & reg_we & !reg_error; + assign dio_pad_attr_6_re = addr_hit[329] & reg_re & !reg_error; + assign dio_pad_attr_6_we = addr_hit[329] & reg_we & !reg_error; assign dio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -34438,8 +34592,8 @@ module pinmux_reg_top ( assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign dio_pad_attr_7_re = addr_hit[326] & reg_re & !reg_error; - assign dio_pad_attr_7_we = addr_hit[326] & reg_we & !reg_error; + assign dio_pad_attr_7_re = addr_hit[330] & reg_re & !reg_error; + assign dio_pad_attr_7_we = addr_hit[330] & reg_we & !reg_error; assign dio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -34458,8 +34612,8 @@ module pinmux_reg_top ( assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign dio_pad_attr_8_re = addr_hit[327] & reg_re & !reg_error; - assign dio_pad_attr_8_we = addr_hit[327] & reg_we & !reg_error; + assign dio_pad_attr_8_re = addr_hit[331] & reg_re & !reg_error; + assign dio_pad_attr_8_we = addr_hit[331] & reg_we & !reg_error; assign dio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -34478,8 +34632,8 @@ module pinmux_reg_top ( assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign dio_pad_attr_9_re = addr_hit[328] & reg_re & !reg_error; - assign dio_pad_attr_9_we = addr_hit[328] & reg_we & !reg_error; + assign dio_pad_attr_9_re = addr_hit[332] & reg_re & !reg_error; + assign dio_pad_attr_9_we = addr_hit[332] & reg_we & !reg_error; assign dio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -34498,8 +34652,8 @@ module pinmux_reg_top ( assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign dio_pad_attr_10_re = addr_hit[329] & reg_re & !reg_error; - assign dio_pad_attr_10_we = addr_hit[329] & reg_we & !reg_error; + assign dio_pad_attr_10_re = addr_hit[333] & reg_re & !reg_error; + assign dio_pad_attr_10_we = addr_hit[333] & reg_we & !reg_error; assign dio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -34518,8 +34672,8 @@ module pinmux_reg_top ( assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign dio_pad_attr_11_re = addr_hit[330] & reg_re & !reg_error; - assign dio_pad_attr_11_we = addr_hit[330] & reg_we & !reg_error; + assign dio_pad_attr_11_re = addr_hit[334] & reg_re & !reg_error; + assign dio_pad_attr_11_we = addr_hit[334] & reg_we & !reg_error; assign dio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -34538,8 +34692,8 @@ module pinmux_reg_top ( assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign dio_pad_attr_12_re = addr_hit[331] & reg_re & !reg_error; - assign dio_pad_attr_12_we = addr_hit[331] & reg_we & !reg_error; + assign dio_pad_attr_12_re = addr_hit[335] & reg_re & !reg_error; + assign dio_pad_attr_12_we = addr_hit[335] & reg_we & !reg_error; assign dio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -34558,8 +34712,8 @@ module pinmux_reg_top ( assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign dio_pad_attr_13_re = addr_hit[332] & reg_re & !reg_error; - assign dio_pad_attr_13_we = addr_hit[332] & reg_we & !reg_error; + assign dio_pad_attr_13_re = addr_hit[336] & reg_re & !reg_error; + assign dio_pad_attr_13_we = addr_hit[336] & reg_we & !reg_error; assign dio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -34578,8 +34732,8 @@ module pinmux_reg_top ( assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign dio_pad_attr_14_re = addr_hit[333] & reg_re & !reg_error; - assign dio_pad_attr_14_we = addr_hit[333] & reg_we & !reg_error; + assign dio_pad_attr_14_re = addr_hit[337] & reg_re & !reg_error; + assign dio_pad_attr_14_we = addr_hit[337] & reg_we & !reg_error; assign dio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -34598,8 +34752,8 @@ module pinmux_reg_top ( assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign dio_pad_attr_15_re = addr_hit[334] & reg_re & !reg_error; - assign dio_pad_attr_15_we = addr_hit[334] & reg_we & !reg_error; + assign dio_pad_attr_15_re = addr_hit[338] & reg_re & !reg_error; + assign dio_pad_attr_15_we = addr_hit[338] & reg_we & !reg_error; assign dio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -34618,7 +34772,7 @@ module pinmux_reg_top ( assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_sleep_status_0_we = addr_hit[335] & reg_we & !reg_error; + assign mio_pad_sleep_status_0_we = addr_hit[339] & reg_we & !reg_error; assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; @@ -34683,7 +34837,7 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; - assign mio_pad_sleep_status_1_we = addr_hit[336] & reg_we & !reg_error; + assign mio_pad_sleep_status_1_we = addr_hit[340] & reg_we & !reg_error; assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; @@ -34714,430 +34868,430 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13]; assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14]; - assign mio_pad_sleep_regwen_0_we = addr_hit[337] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_0_we = addr_hit[341] & reg_we & !reg_error; assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_1_we = addr_hit[338] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_1_we = addr_hit[342] & reg_we & !reg_error; assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_2_we = addr_hit[339] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_2_we = addr_hit[343] & reg_we & !reg_error; assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_3_we = addr_hit[340] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_3_we = addr_hit[344] & reg_we & !reg_error; assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_4_we = addr_hit[341] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_4_we = addr_hit[345] & reg_we & !reg_error; assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_5_we = addr_hit[342] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_5_we = addr_hit[346] & reg_we & !reg_error; assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_6_we = addr_hit[343] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_6_we = addr_hit[347] & reg_we & !reg_error; assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_7_we = addr_hit[344] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_7_we = addr_hit[348] & reg_we & !reg_error; assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_8_we = addr_hit[345] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_8_we = addr_hit[349] & reg_we & !reg_error; assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_9_we = addr_hit[346] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_9_we = addr_hit[350] & reg_we & !reg_error; assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_10_we = addr_hit[347] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_10_we = addr_hit[351] & reg_we & !reg_error; assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_11_we = addr_hit[348] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_11_we = addr_hit[352] & reg_we & !reg_error; assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_12_we = addr_hit[349] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_12_we = addr_hit[353] & reg_we & !reg_error; assign mio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_13_we = addr_hit[350] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_13_we = addr_hit[354] & reg_we & !reg_error; assign mio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_14_we = addr_hit[351] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_14_we = addr_hit[355] & reg_we & !reg_error; assign mio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_15_we = addr_hit[352] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_15_we = addr_hit[356] & reg_we & !reg_error; assign mio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_16_we = addr_hit[353] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_16_we = addr_hit[357] & reg_we & !reg_error; assign mio_pad_sleep_regwen_16_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_17_we = addr_hit[354] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_17_we = addr_hit[358] & reg_we & !reg_error; assign mio_pad_sleep_regwen_17_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_18_we = addr_hit[355] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_18_we = addr_hit[359] & reg_we & !reg_error; assign mio_pad_sleep_regwen_18_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_19_we = addr_hit[356] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_19_we = addr_hit[360] & reg_we & !reg_error; assign mio_pad_sleep_regwen_19_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_20_we = addr_hit[357] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_20_we = addr_hit[361] & reg_we & !reg_error; assign mio_pad_sleep_regwen_20_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_21_we = addr_hit[358] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_21_we = addr_hit[362] & reg_we & !reg_error; assign mio_pad_sleep_regwen_21_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_22_we = addr_hit[359] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_22_we = addr_hit[363] & reg_we & !reg_error; assign mio_pad_sleep_regwen_22_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_23_we = addr_hit[360] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_23_we = addr_hit[364] & reg_we & !reg_error; assign mio_pad_sleep_regwen_23_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_24_we = addr_hit[361] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_24_we = addr_hit[365] & reg_we & !reg_error; assign mio_pad_sleep_regwen_24_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_25_we = addr_hit[362] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_25_we = addr_hit[366] & reg_we & !reg_error; assign mio_pad_sleep_regwen_25_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_26_we = addr_hit[363] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_26_we = addr_hit[367] & reg_we & !reg_error; assign mio_pad_sleep_regwen_26_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_27_we = addr_hit[364] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_27_we = addr_hit[368] & reg_we & !reg_error; assign mio_pad_sleep_regwen_27_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_28_we = addr_hit[365] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_28_we = addr_hit[369] & reg_we & !reg_error; assign mio_pad_sleep_regwen_28_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_29_we = addr_hit[366] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_29_we = addr_hit[370] & reg_we & !reg_error; assign mio_pad_sleep_regwen_29_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_30_we = addr_hit[367] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_30_we = addr_hit[371] & reg_we & !reg_error; assign mio_pad_sleep_regwen_30_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_31_we = addr_hit[368] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_31_we = addr_hit[372] & reg_we & !reg_error; assign mio_pad_sleep_regwen_31_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_32_we = addr_hit[369] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_32_we = addr_hit[373] & reg_we & !reg_error; assign mio_pad_sleep_regwen_32_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_33_we = addr_hit[370] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_33_we = addr_hit[374] & reg_we & !reg_error; assign mio_pad_sleep_regwen_33_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_34_we = addr_hit[371] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_34_we = addr_hit[375] & reg_we & !reg_error; assign mio_pad_sleep_regwen_34_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_35_we = addr_hit[372] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_35_we = addr_hit[376] & reg_we & !reg_error; assign mio_pad_sleep_regwen_35_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_36_we = addr_hit[373] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_36_we = addr_hit[377] & reg_we & !reg_error; assign mio_pad_sleep_regwen_36_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_37_we = addr_hit[374] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_37_we = addr_hit[378] & reg_we & !reg_error; assign mio_pad_sleep_regwen_37_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_38_we = addr_hit[375] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_38_we = addr_hit[379] & reg_we & !reg_error; assign mio_pad_sleep_regwen_38_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_39_we = addr_hit[376] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_39_we = addr_hit[380] & reg_we & !reg_error; assign mio_pad_sleep_regwen_39_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_40_we = addr_hit[377] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_40_we = addr_hit[381] & reg_we & !reg_error; assign mio_pad_sleep_regwen_40_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_41_we = addr_hit[378] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_41_we = addr_hit[382] & reg_we & !reg_error; assign mio_pad_sleep_regwen_41_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_42_we = addr_hit[379] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_42_we = addr_hit[383] & reg_we & !reg_error; assign mio_pad_sleep_regwen_42_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_43_we = addr_hit[380] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_43_we = addr_hit[384] & reg_we & !reg_error; assign mio_pad_sleep_regwen_43_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_44_we = addr_hit[381] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_44_we = addr_hit[385] & reg_we & !reg_error; assign mio_pad_sleep_regwen_44_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_45_we = addr_hit[382] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_45_we = addr_hit[386] & reg_we & !reg_error; assign mio_pad_sleep_regwen_45_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_46_we = addr_hit[383] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_46_we = addr_hit[387] & reg_we & !reg_error; assign mio_pad_sleep_regwen_46_wd = reg_wdata[0]; - assign mio_pad_sleep_en_0_we = addr_hit[384] & reg_we & !reg_error; + assign mio_pad_sleep_en_0_we = addr_hit[388] & reg_we & !reg_error; assign mio_pad_sleep_en_0_wd = reg_wdata[0]; - assign mio_pad_sleep_en_1_we = addr_hit[385] & reg_we & !reg_error; + assign mio_pad_sleep_en_1_we = addr_hit[389] & reg_we & !reg_error; assign mio_pad_sleep_en_1_wd = reg_wdata[0]; - assign mio_pad_sleep_en_2_we = addr_hit[386] & reg_we & !reg_error; + assign mio_pad_sleep_en_2_we = addr_hit[390] & reg_we & !reg_error; assign mio_pad_sleep_en_2_wd = reg_wdata[0]; - assign mio_pad_sleep_en_3_we = addr_hit[387] & reg_we & !reg_error; + assign mio_pad_sleep_en_3_we = addr_hit[391] & reg_we & !reg_error; assign mio_pad_sleep_en_3_wd = reg_wdata[0]; - assign mio_pad_sleep_en_4_we = addr_hit[388] & reg_we & !reg_error; + assign mio_pad_sleep_en_4_we = addr_hit[392] & reg_we & !reg_error; assign mio_pad_sleep_en_4_wd = reg_wdata[0]; - assign mio_pad_sleep_en_5_we = addr_hit[389] & reg_we & !reg_error; + assign mio_pad_sleep_en_5_we = addr_hit[393] & reg_we & !reg_error; assign mio_pad_sleep_en_5_wd = reg_wdata[0]; - assign mio_pad_sleep_en_6_we = addr_hit[390] & reg_we & !reg_error; + assign mio_pad_sleep_en_6_we = addr_hit[394] & reg_we & !reg_error; assign mio_pad_sleep_en_6_wd = reg_wdata[0]; - assign mio_pad_sleep_en_7_we = addr_hit[391] & reg_we & !reg_error; + assign mio_pad_sleep_en_7_we = addr_hit[395] & reg_we & !reg_error; assign mio_pad_sleep_en_7_wd = reg_wdata[0]; - assign mio_pad_sleep_en_8_we = addr_hit[392] & reg_we & !reg_error; + assign mio_pad_sleep_en_8_we = addr_hit[396] & reg_we & !reg_error; assign mio_pad_sleep_en_8_wd = reg_wdata[0]; - assign mio_pad_sleep_en_9_we = addr_hit[393] & reg_we & !reg_error; + assign mio_pad_sleep_en_9_we = addr_hit[397] & reg_we & !reg_error; assign mio_pad_sleep_en_9_wd = reg_wdata[0]; - assign mio_pad_sleep_en_10_we = addr_hit[394] & reg_we & !reg_error; + assign mio_pad_sleep_en_10_we = addr_hit[398] & reg_we & !reg_error; assign mio_pad_sleep_en_10_wd = reg_wdata[0]; - assign mio_pad_sleep_en_11_we = addr_hit[395] & reg_we & !reg_error; + assign mio_pad_sleep_en_11_we = addr_hit[399] & reg_we & !reg_error; assign mio_pad_sleep_en_11_wd = reg_wdata[0]; - assign mio_pad_sleep_en_12_we = addr_hit[396] & reg_we & !reg_error; + assign mio_pad_sleep_en_12_we = addr_hit[400] & reg_we & !reg_error; assign mio_pad_sleep_en_12_wd = reg_wdata[0]; - assign mio_pad_sleep_en_13_we = addr_hit[397] & reg_we & !reg_error; + assign mio_pad_sleep_en_13_we = addr_hit[401] & reg_we & !reg_error; assign mio_pad_sleep_en_13_wd = reg_wdata[0]; - assign mio_pad_sleep_en_14_we = addr_hit[398] & reg_we & !reg_error; + assign mio_pad_sleep_en_14_we = addr_hit[402] & reg_we & !reg_error; assign mio_pad_sleep_en_14_wd = reg_wdata[0]; - assign mio_pad_sleep_en_15_we = addr_hit[399] & reg_we & !reg_error; + assign mio_pad_sleep_en_15_we = addr_hit[403] & reg_we & !reg_error; assign mio_pad_sleep_en_15_wd = reg_wdata[0]; - assign mio_pad_sleep_en_16_we = addr_hit[400] & reg_we & !reg_error; + assign mio_pad_sleep_en_16_we = addr_hit[404] & reg_we & !reg_error; assign mio_pad_sleep_en_16_wd = reg_wdata[0]; - assign mio_pad_sleep_en_17_we = addr_hit[401] & reg_we & !reg_error; + assign mio_pad_sleep_en_17_we = addr_hit[405] & reg_we & !reg_error; assign mio_pad_sleep_en_17_wd = reg_wdata[0]; - assign mio_pad_sleep_en_18_we = addr_hit[402] & reg_we & !reg_error; + assign mio_pad_sleep_en_18_we = addr_hit[406] & reg_we & !reg_error; assign mio_pad_sleep_en_18_wd = reg_wdata[0]; - assign mio_pad_sleep_en_19_we = addr_hit[403] & reg_we & !reg_error; + assign mio_pad_sleep_en_19_we = addr_hit[407] & reg_we & !reg_error; assign mio_pad_sleep_en_19_wd = reg_wdata[0]; - assign mio_pad_sleep_en_20_we = addr_hit[404] & reg_we & !reg_error; + assign mio_pad_sleep_en_20_we = addr_hit[408] & reg_we & !reg_error; assign mio_pad_sleep_en_20_wd = reg_wdata[0]; - assign mio_pad_sleep_en_21_we = addr_hit[405] & reg_we & !reg_error; + assign mio_pad_sleep_en_21_we = addr_hit[409] & reg_we & !reg_error; assign mio_pad_sleep_en_21_wd = reg_wdata[0]; - assign mio_pad_sleep_en_22_we = addr_hit[406] & reg_we & !reg_error; + assign mio_pad_sleep_en_22_we = addr_hit[410] & reg_we & !reg_error; assign mio_pad_sleep_en_22_wd = reg_wdata[0]; - assign mio_pad_sleep_en_23_we = addr_hit[407] & reg_we & !reg_error; + assign mio_pad_sleep_en_23_we = addr_hit[411] & reg_we & !reg_error; assign mio_pad_sleep_en_23_wd = reg_wdata[0]; - assign mio_pad_sleep_en_24_we = addr_hit[408] & reg_we & !reg_error; + assign mio_pad_sleep_en_24_we = addr_hit[412] & reg_we & !reg_error; assign mio_pad_sleep_en_24_wd = reg_wdata[0]; - assign mio_pad_sleep_en_25_we = addr_hit[409] & reg_we & !reg_error; + assign mio_pad_sleep_en_25_we = addr_hit[413] & reg_we & !reg_error; assign mio_pad_sleep_en_25_wd = reg_wdata[0]; - assign mio_pad_sleep_en_26_we = addr_hit[410] & reg_we & !reg_error; + assign mio_pad_sleep_en_26_we = addr_hit[414] & reg_we & !reg_error; assign mio_pad_sleep_en_26_wd = reg_wdata[0]; - assign mio_pad_sleep_en_27_we = addr_hit[411] & reg_we & !reg_error; + assign mio_pad_sleep_en_27_we = addr_hit[415] & reg_we & !reg_error; assign mio_pad_sleep_en_27_wd = reg_wdata[0]; - assign mio_pad_sleep_en_28_we = addr_hit[412] & reg_we & !reg_error; + assign mio_pad_sleep_en_28_we = addr_hit[416] & reg_we & !reg_error; assign mio_pad_sleep_en_28_wd = reg_wdata[0]; - assign mio_pad_sleep_en_29_we = addr_hit[413] & reg_we & !reg_error; + assign mio_pad_sleep_en_29_we = addr_hit[417] & reg_we & !reg_error; assign mio_pad_sleep_en_29_wd = reg_wdata[0]; - assign mio_pad_sleep_en_30_we = addr_hit[414] & reg_we & !reg_error; + assign mio_pad_sleep_en_30_we = addr_hit[418] & reg_we & !reg_error; assign mio_pad_sleep_en_30_wd = reg_wdata[0]; - assign mio_pad_sleep_en_31_we = addr_hit[415] & reg_we & !reg_error; + assign mio_pad_sleep_en_31_we = addr_hit[419] & reg_we & !reg_error; assign mio_pad_sleep_en_31_wd = reg_wdata[0]; - assign mio_pad_sleep_en_32_we = addr_hit[416] & reg_we & !reg_error; + assign mio_pad_sleep_en_32_we = addr_hit[420] & reg_we & !reg_error; assign mio_pad_sleep_en_32_wd = reg_wdata[0]; - assign mio_pad_sleep_en_33_we = addr_hit[417] & reg_we & !reg_error; + assign mio_pad_sleep_en_33_we = addr_hit[421] & reg_we & !reg_error; assign mio_pad_sleep_en_33_wd = reg_wdata[0]; - assign mio_pad_sleep_en_34_we = addr_hit[418] & reg_we & !reg_error; + assign mio_pad_sleep_en_34_we = addr_hit[422] & reg_we & !reg_error; assign mio_pad_sleep_en_34_wd = reg_wdata[0]; - assign mio_pad_sleep_en_35_we = addr_hit[419] & reg_we & !reg_error; + assign mio_pad_sleep_en_35_we = addr_hit[423] & reg_we & !reg_error; assign mio_pad_sleep_en_35_wd = reg_wdata[0]; - assign mio_pad_sleep_en_36_we = addr_hit[420] & reg_we & !reg_error; + assign mio_pad_sleep_en_36_we = addr_hit[424] & reg_we & !reg_error; assign mio_pad_sleep_en_36_wd = reg_wdata[0]; - assign mio_pad_sleep_en_37_we = addr_hit[421] & reg_we & !reg_error; + assign mio_pad_sleep_en_37_we = addr_hit[425] & reg_we & !reg_error; assign mio_pad_sleep_en_37_wd = reg_wdata[0]; - assign mio_pad_sleep_en_38_we = addr_hit[422] & reg_we & !reg_error; + assign mio_pad_sleep_en_38_we = addr_hit[426] & reg_we & !reg_error; assign mio_pad_sleep_en_38_wd = reg_wdata[0]; - assign mio_pad_sleep_en_39_we = addr_hit[423] & reg_we & !reg_error; + assign mio_pad_sleep_en_39_we = addr_hit[427] & reg_we & !reg_error; assign mio_pad_sleep_en_39_wd = reg_wdata[0]; - assign mio_pad_sleep_en_40_we = addr_hit[424] & reg_we & !reg_error; + assign mio_pad_sleep_en_40_we = addr_hit[428] & reg_we & !reg_error; assign mio_pad_sleep_en_40_wd = reg_wdata[0]; - assign mio_pad_sleep_en_41_we = addr_hit[425] & reg_we & !reg_error; + assign mio_pad_sleep_en_41_we = addr_hit[429] & reg_we & !reg_error; assign mio_pad_sleep_en_41_wd = reg_wdata[0]; - assign mio_pad_sleep_en_42_we = addr_hit[426] & reg_we & !reg_error; + assign mio_pad_sleep_en_42_we = addr_hit[430] & reg_we & !reg_error; assign mio_pad_sleep_en_42_wd = reg_wdata[0]; - assign mio_pad_sleep_en_43_we = addr_hit[427] & reg_we & !reg_error; + assign mio_pad_sleep_en_43_we = addr_hit[431] & reg_we & !reg_error; assign mio_pad_sleep_en_43_wd = reg_wdata[0]; - assign mio_pad_sleep_en_44_we = addr_hit[428] & reg_we & !reg_error; + assign mio_pad_sleep_en_44_we = addr_hit[432] & reg_we & !reg_error; assign mio_pad_sleep_en_44_wd = reg_wdata[0]; - assign mio_pad_sleep_en_45_we = addr_hit[429] & reg_we & !reg_error; + assign mio_pad_sleep_en_45_we = addr_hit[433] & reg_we & !reg_error; assign mio_pad_sleep_en_45_wd = reg_wdata[0]; - assign mio_pad_sleep_en_46_we = addr_hit[430] & reg_we & !reg_error; + assign mio_pad_sleep_en_46_we = addr_hit[434] & reg_we & !reg_error; assign mio_pad_sleep_en_46_wd = reg_wdata[0]; - assign mio_pad_sleep_mode_0_we = addr_hit[431] & reg_we & !reg_error; + assign mio_pad_sleep_mode_0_we = addr_hit[435] & reg_we & !reg_error; assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_1_we = addr_hit[432] & reg_we & !reg_error; + assign mio_pad_sleep_mode_1_we = addr_hit[436] & reg_we & !reg_error; assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_2_we = addr_hit[433] & reg_we & !reg_error; + assign mio_pad_sleep_mode_2_we = addr_hit[437] & reg_we & !reg_error; assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_3_we = addr_hit[434] & reg_we & !reg_error; + assign mio_pad_sleep_mode_3_we = addr_hit[438] & reg_we & !reg_error; assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_4_we = addr_hit[435] & reg_we & !reg_error; + assign mio_pad_sleep_mode_4_we = addr_hit[439] & reg_we & !reg_error; assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_5_we = addr_hit[436] & reg_we & !reg_error; + assign mio_pad_sleep_mode_5_we = addr_hit[440] & reg_we & !reg_error; assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_6_we = addr_hit[437] & reg_we & !reg_error; + assign mio_pad_sleep_mode_6_we = addr_hit[441] & reg_we & !reg_error; assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_7_we = addr_hit[438] & reg_we & !reg_error; + assign mio_pad_sleep_mode_7_we = addr_hit[442] & reg_we & !reg_error; assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_8_we = addr_hit[439] & reg_we & !reg_error; + assign mio_pad_sleep_mode_8_we = addr_hit[443] & reg_we & !reg_error; assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_9_we = addr_hit[440] & reg_we & !reg_error; + assign mio_pad_sleep_mode_9_we = addr_hit[444] & reg_we & !reg_error; assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_10_we = addr_hit[441] & reg_we & !reg_error; + assign mio_pad_sleep_mode_10_we = addr_hit[445] & reg_we & !reg_error; assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_11_we = addr_hit[442] & reg_we & !reg_error; + assign mio_pad_sleep_mode_11_we = addr_hit[446] & reg_we & !reg_error; assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_12_we = addr_hit[443] & reg_we & !reg_error; + assign mio_pad_sleep_mode_12_we = addr_hit[447] & reg_we & !reg_error; assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_13_we = addr_hit[444] & reg_we & !reg_error; + assign mio_pad_sleep_mode_13_we = addr_hit[448] & reg_we & !reg_error; assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_14_we = addr_hit[445] & reg_we & !reg_error; + assign mio_pad_sleep_mode_14_we = addr_hit[449] & reg_we & !reg_error; assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_15_we = addr_hit[446] & reg_we & !reg_error; + assign mio_pad_sleep_mode_15_we = addr_hit[450] & reg_we & !reg_error; assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_16_we = addr_hit[447] & reg_we & !reg_error; + assign mio_pad_sleep_mode_16_we = addr_hit[451] & reg_we & !reg_error; assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_17_we = addr_hit[448] & reg_we & !reg_error; + assign mio_pad_sleep_mode_17_we = addr_hit[452] & reg_we & !reg_error; assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_18_we = addr_hit[449] & reg_we & !reg_error; + assign mio_pad_sleep_mode_18_we = addr_hit[453] & reg_we & !reg_error; assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_19_we = addr_hit[450] & reg_we & !reg_error; + assign mio_pad_sleep_mode_19_we = addr_hit[454] & reg_we & !reg_error; assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_20_we = addr_hit[451] & reg_we & !reg_error; + assign mio_pad_sleep_mode_20_we = addr_hit[455] & reg_we & !reg_error; assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_21_we = addr_hit[452] & reg_we & !reg_error; + assign mio_pad_sleep_mode_21_we = addr_hit[456] & reg_we & !reg_error; assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_22_we = addr_hit[453] & reg_we & !reg_error; + assign mio_pad_sleep_mode_22_we = addr_hit[457] & reg_we & !reg_error; assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_23_we = addr_hit[454] & reg_we & !reg_error; + assign mio_pad_sleep_mode_23_we = addr_hit[458] & reg_we & !reg_error; assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_24_we = addr_hit[455] & reg_we & !reg_error; + assign mio_pad_sleep_mode_24_we = addr_hit[459] & reg_we & !reg_error; assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_25_we = addr_hit[456] & reg_we & !reg_error; + assign mio_pad_sleep_mode_25_we = addr_hit[460] & reg_we & !reg_error; assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_26_we = addr_hit[457] & reg_we & !reg_error; + assign mio_pad_sleep_mode_26_we = addr_hit[461] & reg_we & !reg_error; assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_27_we = addr_hit[458] & reg_we & !reg_error; + assign mio_pad_sleep_mode_27_we = addr_hit[462] & reg_we & !reg_error; assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_28_we = addr_hit[459] & reg_we & !reg_error; + assign mio_pad_sleep_mode_28_we = addr_hit[463] & reg_we & !reg_error; assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_29_we = addr_hit[460] & reg_we & !reg_error; + assign mio_pad_sleep_mode_29_we = addr_hit[464] & reg_we & !reg_error; assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_30_we = addr_hit[461] & reg_we & !reg_error; + assign mio_pad_sleep_mode_30_we = addr_hit[465] & reg_we & !reg_error; assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_31_we = addr_hit[462] & reg_we & !reg_error; + assign mio_pad_sleep_mode_31_we = addr_hit[466] & reg_we & !reg_error; assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_32_we = addr_hit[463] & reg_we & !reg_error; + assign mio_pad_sleep_mode_32_we = addr_hit[467] & reg_we & !reg_error; assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_33_we = addr_hit[464] & reg_we & !reg_error; + assign mio_pad_sleep_mode_33_we = addr_hit[468] & reg_we & !reg_error; assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_34_we = addr_hit[465] & reg_we & !reg_error; + assign mio_pad_sleep_mode_34_we = addr_hit[469] & reg_we & !reg_error; assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_35_we = addr_hit[466] & reg_we & !reg_error; + assign mio_pad_sleep_mode_35_we = addr_hit[470] & reg_we & !reg_error; assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_36_we = addr_hit[467] & reg_we & !reg_error; + assign mio_pad_sleep_mode_36_we = addr_hit[471] & reg_we & !reg_error; assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_37_we = addr_hit[468] & reg_we & !reg_error; + assign mio_pad_sleep_mode_37_we = addr_hit[472] & reg_we & !reg_error; assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_38_we = addr_hit[469] & reg_we & !reg_error; + assign mio_pad_sleep_mode_38_we = addr_hit[473] & reg_we & !reg_error; assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_39_we = addr_hit[470] & reg_we & !reg_error; + assign mio_pad_sleep_mode_39_we = addr_hit[474] & reg_we & !reg_error; assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_40_we = addr_hit[471] & reg_we & !reg_error; + assign mio_pad_sleep_mode_40_we = addr_hit[475] & reg_we & !reg_error; assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_41_we = addr_hit[472] & reg_we & !reg_error; + assign mio_pad_sleep_mode_41_we = addr_hit[476] & reg_we & !reg_error; assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_42_we = addr_hit[473] & reg_we & !reg_error; + assign mio_pad_sleep_mode_42_we = addr_hit[477] & reg_we & !reg_error; assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_43_we = addr_hit[474] & reg_we & !reg_error; + assign mio_pad_sleep_mode_43_we = addr_hit[478] & reg_we & !reg_error; assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_44_we = addr_hit[475] & reg_we & !reg_error; + assign mio_pad_sleep_mode_44_we = addr_hit[479] & reg_we & !reg_error; assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_45_we = addr_hit[476] & reg_we & !reg_error; + assign mio_pad_sleep_mode_45_we = addr_hit[480] & reg_we & !reg_error; assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_46_we = addr_hit[477] & reg_we & !reg_error; + assign mio_pad_sleep_mode_46_we = addr_hit[481] & reg_we & !reg_error; assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0]; - assign dio_pad_sleep_status_we = addr_hit[478] & reg_we & !reg_error; + assign dio_pad_sleep_status_we = addr_hit[482] & reg_we & !reg_error; assign dio_pad_sleep_status_en_0_wd = reg_wdata[0]; @@ -35170,263 +35324,263 @@ module pinmux_reg_top ( assign dio_pad_sleep_status_en_14_wd = reg_wdata[14]; assign dio_pad_sleep_status_en_15_wd = reg_wdata[15]; - assign dio_pad_sleep_regwen_0_we = addr_hit[479] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_0_we = addr_hit[483] & reg_we & !reg_error; assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_1_we = addr_hit[480] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_1_we = addr_hit[484] & reg_we & !reg_error; assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_2_we = addr_hit[481] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_2_we = addr_hit[485] & reg_we & !reg_error; assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_3_we = addr_hit[482] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_3_we = addr_hit[486] & reg_we & !reg_error; assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_4_we = addr_hit[483] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_4_we = addr_hit[487] & reg_we & !reg_error; assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_5_we = addr_hit[484] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_5_we = addr_hit[488] & reg_we & !reg_error; assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_6_we = addr_hit[485] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_6_we = addr_hit[489] & reg_we & !reg_error; assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_7_we = addr_hit[486] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_7_we = addr_hit[490] & reg_we & !reg_error; assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_8_we = addr_hit[487] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_8_we = addr_hit[491] & reg_we & !reg_error; assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_9_we = addr_hit[488] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_9_we = addr_hit[492] & reg_we & !reg_error; assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_10_we = addr_hit[489] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_10_we = addr_hit[493] & reg_we & !reg_error; assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_11_we = addr_hit[490] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_11_we = addr_hit[494] & reg_we & !reg_error; assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_12_we = addr_hit[491] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_12_we = addr_hit[495] & reg_we & !reg_error; assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_13_we = addr_hit[492] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_13_we = addr_hit[496] & reg_we & !reg_error; assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_14_we = addr_hit[493] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_14_we = addr_hit[497] & reg_we & !reg_error; assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_15_we = addr_hit[494] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_15_we = addr_hit[498] & reg_we & !reg_error; assign dio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign dio_pad_sleep_en_0_we = addr_hit[495] & reg_we & !reg_error; + assign dio_pad_sleep_en_0_we = addr_hit[499] & reg_we & !reg_error; assign dio_pad_sleep_en_0_wd = reg_wdata[0]; - assign dio_pad_sleep_en_1_we = addr_hit[496] & reg_we & !reg_error; + assign dio_pad_sleep_en_1_we = addr_hit[500] & reg_we & !reg_error; assign dio_pad_sleep_en_1_wd = reg_wdata[0]; - assign dio_pad_sleep_en_2_we = addr_hit[497] & reg_we & !reg_error; + assign dio_pad_sleep_en_2_we = addr_hit[501] & reg_we & !reg_error; assign dio_pad_sleep_en_2_wd = reg_wdata[0]; - assign dio_pad_sleep_en_3_we = addr_hit[498] & reg_we & !reg_error; + assign dio_pad_sleep_en_3_we = addr_hit[502] & reg_we & !reg_error; assign dio_pad_sleep_en_3_wd = reg_wdata[0]; - assign dio_pad_sleep_en_4_we = addr_hit[499] & reg_we & !reg_error; + assign dio_pad_sleep_en_4_we = addr_hit[503] & reg_we & !reg_error; assign dio_pad_sleep_en_4_wd = reg_wdata[0]; - assign dio_pad_sleep_en_5_we = addr_hit[500] & reg_we & !reg_error; + assign dio_pad_sleep_en_5_we = addr_hit[504] & reg_we & !reg_error; assign dio_pad_sleep_en_5_wd = reg_wdata[0]; - assign dio_pad_sleep_en_6_we = addr_hit[501] & reg_we & !reg_error; + assign dio_pad_sleep_en_6_we = addr_hit[505] & reg_we & !reg_error; assign dio_pad_sleep_en_6_wd = reg_wdata[0]; - assign dio_pad_sleep_en_7_we = addr_hit[502] & reg_we & !reg_error; + assign dio_pad_sleep_en_7_we = addr_hit[506] & reg_we & !reg_error; assign dio_pad_sleep_en_7_wd = reg_wdata[0]; - assign dio_pad_sleep_en_8_we = addr_hit[503] & reg_we & !reg_error; + assign dio_pad_sleep_en_8_we = addr_hit[507] & reg_we & !reg_error; assign dio_pad_sleep_en_8_wd = reg_wdata[0]; - assign dio_pad_sleep_en_9_we = addr_hit[504] & reg_we & !reg_error; + assign dio_pad_sleep_en_9_we = addr_hit[508] & reg_we & !reg_error; assign dio_pad_sleep_en_9_wd = reg_wdata[0]; - assign dio_pad_sleep_en_10_we = addr_hit[505] & reg_we & !reg_error; + assign dio_pad_sleep_en_10_we = addr_hit[509] & reg_we & !reg_error; assign dio_pad_sleep_en_10_wd = reg_wdata[0]; - assign dio_pad_sleep_en_11_we = addr_hit[506] & reg_we & !reg_error; + assign dio_pad_sleep_en_11_we = addr_hit[510] & reg_we & !reg_error; assign dio_pad_sleep_en_11_wd = reg_wdata[0]; - assign dio_pad_sleep_en_12_we = addr_hit[507] & reg_we & !reg_error; + assign dio_pad_sleep_en_12_we = addr_hit[511] & reg_we & !reg_error; assign dio_pad_sleep_en_12_wd = reg_wdata[0]; - assign dio_pad_sleep_en_13_we = addr_hit[508] & reg_we & !reg_error; + assign dio_pad_sleep_en_13_we = addr_hit[512] & reg_we & !reg_error; assign dio_pad_sleep_en_13_wd = reg_wdata[0]; - assign dio_pad_sleep_en_14_we = addr_hit[509] & reg_we & !reg_error; + assign dio_pad_sleep_en_14_we = addr_hit[513] & reg_we & !reg_error; assign dio_pad_sleep_en_14_wd = reg_wdata[0]; - assign dio_pad_sleep_en_15_we = addr_hit[510] & reg_we & !reg_error; + assign dio_pad_sleep_en_15_we = addr_hit[514] & reg_we & !reg_error; assign dio_pad_sleep_en_15_wd = reg_wdata[0]; - assign dio_pad_sleep_mode_0_we = addr_hit[511] & reg_we & !reg_error; + assign dio_pad_sleep_mode_0_we = addr_hit[515] & reg_we & !reg_error; assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_1_we = addr_hit[512] & reg_we & !reg_error; + assign dio_pad_sleep_mode_1_we = addr_hit[516] & reg_we & !reg_error; assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_2_we = addr_hit[513] & reg_we & !reg_error; + assign dio_pad_sleep_mode_2_we = addr_hit[517] & reg_we & !reg_error; assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_3_we = addr_hit[514] & reg_we & !reg_error; + assign dio_pad_sleep_mode_3_we = addr_hit[518] & reg_we & !reg_error; assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_4_we = addr_hit[515] & reg_we & !reg_error; + assign dio_pad_sleep_mode_4_we = addr_hit[519] & reg_we & !reg_error; assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_5_we = addr_hit[516] & reg_we & !reg_error; + assign dio_pad_sleep_mode_5_we = addr_hit[520] & reg_we & !reg_error; assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_6_we = addr_hit[517] & reg_we & !reg_error; + assign dio_pad_sleep_mode_6_we = addr_hit[521] & reg_we & !reg_error; assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_7_we = addr_hit[518] & reg_we & !reg_error; + assign dio_pad_sleep_mode_7_we = addr_hit[522] & reg_we & !reg_error; assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_8_we = addr_hit[519] & reg_we & !reg_error; + assign dio_pad_sleep_mode_8_we = addr_hit[523] & reg_we & !reg_error; assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_9_we = addr_hit[520] & reg_we & !reg_error; + assign dio_pad_sleep_mode_9_we = addr_hit[524] & reg_we & !reg_error; assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_10_we = addr_hit[521] & reg_we & !reg_error; + assign dio_pad_sleep_mode_10_we = addr_hit[525] & reg_we & !reg_error; assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_11_we = addr_hit[522] & reg_we & !reg_error; + assign dio_pad_sleep_mode_11_we = addr_hit[526] & reg_we & !reg_error; assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_12_we = addr_hit[523] & reg_we & !reg_error; + assign dio_pad_sleep_mode_12_we = addr_hit[527] & reg_we & !reg_error; assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_13_we = addr_hit[524] & reg_we & !reg_error; + assign dio_pad_sleep_mode_13_we = addr_hit[528] & reg_we & !reg_error; assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_14_we = addr_hit[525] & reg_we & !reg_error; + assign dio_pad_sleep_mode_14_we = addr_hit[529] & reg_we & !reg_error; assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_15_we = addr_hit[526] & reg_we & !reg_error; + assign dio_pad_sleep_mode_15_we = addr_hit[530] & reg_we & !reg_error; assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign wkup_detector_regwen_0_we = addr_hit[527] & reg_we & !reg_error; + assign wkup_detector_regwen_0_we = addr_hit[531] & reg_we & !reg_error; assign wkup_detector_regwen_0_wd = reg_wdata[0]; - assign wkup_detector_regwen_1_we = addr_hit[528] & reg_we & !reg_error; + assign wkup_detector_regwen_1_we = addr_hit[532] & reg_we & !reg_error; assign wkup_detector_regwen_1_wd = reg_wdata[0]; - assign wkup_detector_regwen_2_we = addr_hit[529] & reg_we & !reg_error; + assign wkup_detector_regwen_2_we = addr_hit[533] & reg_we & !reg_error; assign wkup_detector_regwen_2_wd = reg_wdata[0]; - assign wkup_detector_regwen_3_we = addr_hit[530] & reg_we & !reg_error; + assign wkup_detector_regwen_3_we = addr_hit[534] & reg_we & !reg_error; assign wkup_detector_regwen_3_wd = reg_wdata[0]; - assign wkup_detector_regwen_4_we = addr_hit[531] & reg_we & !reg_error; + assign wkup_detector_regwen_4_we = addr_hit[535] & reg_we & !reg_error; assign wkup_detector_regwen_4_wd = reg_wdata[0]; - assign wkup_detector_regwen_5_we = addr_hit[532] & reg_we & !reg_error; + assign wkup_detector_regwen_5_we = addr_hit[536] & reg_we & !reg_error; assign wkup_detector_regwen_5_wd = reg_wdata[0]; - assign wkup_detector_regwen_6_we = addr_hit[533] & reg_we & !reg_error; + assign wkup_detector_regwen_6_we = addr_hit[537] & reg_we & !reg_error; assign wkup_detector_regwen_6_wd = reg_wdata[0]; - assign wkup_detector_regwen_7_we = addr_hit[534] & reg_we & !reg_error; + assign wkup_detector_regwen_7_we = addr_hit[538] & reg_we & !reg_error; assign wkup_detector_regwen_7_wd = reg_wdata[0]; - assign wkup_detector_en_0_we = addr_hit[535] & reg_we & !reg_error; + assign wkup_detector_en_0_we = addr_hit[539] & reg_we & !reg_error; - assign wkup_detector_en_1_we = addr_hit[536] & reg_we & !reg_error; + assign wkup_detector_en_1_we = addr_hit[540] & reg_we & !reg_error; - assign wkup_detector_en_2_we = addr_hit[537] & reg_we & !reg_error; + assign wkup_detector_en_2_we = addr_hit[541] & reg_we & !reg_error; - assign wkup_detector_en_3_we = addr_hit[538] & reg_we & !reg_error; + assign wkup_detector_en_3_we = addr_hit[542] & reg_we & !reg_error; - assign wkup_detector_en_4_we = addr_hit[539] & reg_we & !reg_error; + assign wkup_detector_en_4_we = addr_hit[543] & reg_we & !reg_error; - assign wkup_detector_en_5_we = addr_hit[540] & reg_we & !reg_error; + assign wkup_detector_en_5_we = addr_hit[544] & reg_we & !reg_error; - assign wkup_detector_en_6_we = addr_hit[541] & reg_we & !reg_error; + assign wkup_detector_en_6_we = addr_hit[545] & reg_we & !reg_error; - assign wkup_detector_en_7_we = addr_hit[542] & reg_we & !reg_error; + assign wkup_detector_en_7_we = addr_hit[546] & reg_we & !reg_error; - assign wkup_detector_0_we = addr_hit[543] & reg_we & !reg_error; + assign wkup_detector_0_we = addr_hit[547] & reg_we & !reg_error; - assign wkup_detector_1_we = addr_hit[544] & reg_we & !reg_error; + assign wkup_detector_1_we = addr_hit[548] & reg_we & !reg_error; - assign wkup_detector_2_we = addr_hit[545] & reg_we & !reg_error; + assign wkup_detector_2_we = addr_hit[549] & reg_we & !reg_error; - assign wkup_detector_3_we = addr_hit[546] & reg_we & !reg_error; + assign wkup_detector_3_we = addr_hit[550] & reg_we & !reg_error; - assign wkup_detector_4_we = addr_hit[547] & reg_we & !reg_error; + assign wkup_detector_4_we = addr_hit[551] & reg_we & !reg_error; - assign wkup_detector_5_we = addr_hit[548] & reg_we & !reg_error; + assign wkup_detector_5_we = addr_hit[552] & reg_we & !reg_error; - assign wkup_detector_6_we = addr_hit[549] & reg_we & !reg_error; + assign wkup_detector_6_we = addr_hit[553] & reg_we & !reg_error; - assign wkup_detector_7_we = addr_hit[550] & reg_we & !reg_error; + assign wkup_detector_7_we = addr_hit[554] & reg_we & !reg_error; - assign wkup_detector_cnt_th_0_we = addr_hit[551] & reg_we & !reg_error; + assign wkup_detector_cnt_th_0_we = addr_hit[555] & reg_we & !reg_error; - assign wkup_detector_cnt_th_1_we = addr_hit[552] & reg_we & !reg_error; + assign wkup_detector_cnt_th_1_we = addr_hit[556] & reg_we & !reg_error; - assign wkup_detector_cnt_th_2_we = addr_hit[553] & reg_we & !reg_error; + assign wkup_detector_cnt_th_2_we = addr_hit[557] & reg_we & !reg_error; - assign wkup_detector_cnt_th_3_we = addr_hit[554] & reg_we & !reg_error; + assign wkup_detector_cnt_th_3_we = addr_hit[558] & reg_we & !reg_error; - assign wkup_detector_cnt_th_4_we = addr_hit[555] & reg_we & !reg_error; + assign wkup_detector_cnt_th_4_we = addr_hit[559] & reg_we & !reg_error; - assign wkup_detector_cnt_th_5_we = addr_hit[556] & reg_we & !reg_error; + assign wkup_detector_cnt_th_5_we = addr_hit[560] & reg_we & !reg_error; - assign wkup_detector_cnt_th_6_we = addr_hit[557] & reg_we & !reg_error; + assign wkup_detector_cnt_th_6_we = addr_hit[561] & reg_we & !reg_error; - assign wkup_detector_cnt_th_7_we = addr_hit[558] & reg_we & !reg_error; + assign wkup_detector_cnt_th_7_we = addr_hit[562] & reg_we & !reg_error; - assign wkup_detector_padsel_0_we = addr_hit[559] & reg_we & !reg_error; + assign wkup_detector_padsel_0_we = addr_hit[563] & reg_we & !reg_error; assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_1_we = addr_hit[560] & reg_we & !reg_error; + assign wkup_detector_padsel_1_we = addr_hit[564] & reg_we & !reg_error; assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_2_we = addr_hit[561] & reg_we & !reg_error; + assign wkup_detector_padsel_2_we = addr_hit[565] & reg_we & !reg_error; assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_3_we = addr_hit[562] & reg_we & !reg_error; + assign wkup_detector_padsel_3_we = addr_hit[566] & reg_we & !reg_error; assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_4_we = addr_hit[563] & reg_we & !reg_error; + assign wkup_detector_padsel_4_we = addr_hit[567] & reg_we & !reg_error; assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_5_we = addr_hit[564] & reg_we & !reg_error; + assign wkup_detector_padsel_5_we = addr_hit[568] & reg_we & !reg_error; assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_6_we = addr_hit[565] & reg_we & !reg_error; + assign wkup_detector_padsel_6_we = addr_hit[569] & reg_we & !reg_error; assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_7_we = addr_hit[566] & reg_we & !reg_error; + assign wkup_detector_padsel_7_we = addr_hit[570] & reg_we & !reg_error; assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; - assign wkup_cause_we = addr_hit[567] & reg_we & !reg_error; + assign wkup_cause_we = addr_hit[571] & reg_we & !reg_error; @@ -35497,516 +35651,520 @@ module pinmux_reg_top ( reg_we_check[55] = mio_periph_insel_regwen_54_we; reg_we_check[56] = mio_periph_insel_regwen_55_we; reg_we_check[57] = mio_periph_insel_regwen_56_we; - reg_we_check[58] = mio_periph_insel_0_gated_we; - reg_we_check[59] = mio_periph_insel_1_gated_we; - reg_we_check[60] = mio_periph_insel_2_gated_we; - reg_we_check[61] = mio_periph_insel_3_gated_we; - reg_we_check[62] = mio_periph_insel_4_gated_we; - reg_we_check[63] = mio_periph_insel_5_gated_we; - reg_we_check[64] = mio_periph_insel_6_gated_we; - reg_we_check[65] = mio_periph_insel_7_gated_we; - reg_we_check[66] = mio_periph_insel_8_gated_we; - reg_we_check[67] = mio_periph_insel_9_gated_we; - reg_we_check[68] = mio_periph_insel_10_gated_we; - reg_we_check[69] = mio_periph_insel_11_gated_we; - reg_we_check[70] = mio_periph_insel_12_gated_we; - reg_we_check[71] = mio_periph_insel_13_gated_we; - reg_we_check[72] = mio_periph_insel_14_gated_we; - reg_we_check[73] = mio_periph_insel_15_gated_we; - reg_we_check[74] = mio_periph_insel_16_gated_we; - reg_we_check[75] = mio_periph_insel_17_gated_we; - reg_we_check[76] = mio_periph_insel_18_gated_we; - reg_we_check[77] = mio_periph_insel_19_gated_we; - reg_we_check[78] = mio_periph_insel_20_gated_we; - reg_we_check[79] = mio_periph_insel_21_gated_we; - reg_we_check[80] = mio_periph_insel_22_gated_we; - reg_we_check[81] = mio_periph_insel_23_gated_we; - reg_we_check[82] = mio_periph_insel_24_gated_we; - reg_we_check[83] = mio_periph_insel_25_gated_we; - reg_we_check[84] = mio_periph_insel_26_gated_we; - reg_we_check[85] = mio_periph_insel_27_gated_we; - reg_we_check[86] = mio_periph_insel_28_gated_we; - reg_we_check[87] = mio_periph_insel_29_gated_we; - reg_we_check[88] = mio_periph_insel_30_gated_we; - reg_we_check[89] = mio_periph_insel_31_gated_we; - reg_we_check[90] = mio_periph_insel_32_gated_we; - reg_we_check[91] = mio_periph_insel_33_gated_we; - reg_we_check[92] = mio_periph_insel_34_gated_we; - reg_we_check[93] = mio_periph_insel_35_gated_we; - reg_we_check[94] = mio_periph_insel_36_gated_we; - reg_we_check[95] = mio_periph_insel_37_gated_we; - reg_we_check[96] = mio_periph_insel_38_gated_we; - reg_we_check[97] = mio_periph_insel_39_gated_we; - reg_we_check[98] = mio_periph_insel_40_gated_we; - reg_we_check[99] = mio_periph_insel_41_gated_we; - reg_we_check[100] = mio_periph_insel_42_gated_we; - reg_we_check[101] = mio_periph_insel_43_gated_we; - reg_we_check[102] = mio_periph_insel_44_gated_we; - reg_we_check[103] = mio_periph_insel_45_gated_we; - reg_we_check[104] = mio_periph_insel_46_gated_we; - reg_we_check[105] = mio_periph_insel_47_gated_we; - reg_we_check[106] = mio_periph_insel_48_gated_we; - reg_we_check[107] = mio_periph_insel_49_gated_we; - reg_we_check[108] = mio_periph_insel_50_gated_we; - reg_we_check[109] = mio_periph_insel_51_gated_we; - reg_we_check[110] = mio_periph_insel_52_gated_we; - reg_we_check[111] = mio_periph_insel_53_gated_we; - reg_we_check[112] = mio_periph_insel_54_gated_we; - reg_we_check[113] = mio_periph_insel_55_gated_we; - reg_we_check[114] = mio_periph_insel_56_gated_we; - reg_we_check[115] = mio_outsel_regwen_0_we; - reg_we_check[116] = mio_outsel_regwen_1_we; - reg_we_check[117] = mio_outsel_regwen_2_we; - reg_we_check[118] = mio_outsel_regwen_3_we; - reg_we_check[119] = mio_outsel_regwen_4_we; - reg_we_check[120] = mio_outsel_regwen_5_we; - reg_we_check[121] = mio_outsel_regwen_6_we; - reg_we_check[122] = mio_outsel_regwen_7_we; - reg_we_check[123] = mio_outsel_regwen_8_we; - reg_we_check[124] = mio_outsel_regwen_9_we; - reg_we_check[125] = mio_outsel_regwen_10_we; - reg_we_check[126] = mio_outsel_regwen_11_we; - reg_we_check[127] = mio_outsel_regwen_12_we; - reg_we_check[128] = mio_outsel_regwen_13_we; - reg_we_check[129] = mio_outsel_regwen_14_we; - reg_we_check[130] = mio_outsel_regwen_15_we; - reg_we_check[131] = mio_outsel_regwen_16_we; - reg_we_check[132] = mio_outsel_regwen_17_we; - reg_we_check[133] = mio_outsel_regwen_18_we; - reg_we_check[134] = mio_outsel_regwen_19_we; - reg_we_check[135] = mio_outsel_regwen_20_we; - reg_we_check[136] = mio_outsel_regwen_21_we; - reg_we_check[137] = mio_outsel_regwen_22_we; - reg_we_check[138] = mio_outsel_regwen_23_we; - reg_we_check[139] = mio_outsel_regwen_24_we; - reg_we_check[140] = mio_outsel_regwen_25_we; - reg_we_check[141] = mio_outsel_regwen_26_we; - reg_we_check[142] = mio_outsel_regwen_27_we; - reg_we_check[143] = mio_outsel_regwen_28_we; - reg_we_check[144] = mio_outsel_regwen_29_we; - reg_we_check[145] = mio_outsel_regwen_30_we; - reg_we_check[146] = mio_outsel_regwen_31_we; - reg_we_check[147] = mio_outsel_regwen_32_we; - reg_we_check[148] = mio_outsel_regwen_33_we; - reg_we_check[149] = mio_outsel_regwen_34_we; - reg_we_check[150] = mio_outsel_regwen_35_we; - reg_we_check[151] = mio_outsel_regwen_36_we; - reg_we_check[152] = mio_outsel_regwen_37_we; - reg_we_check[153] = mio_outsel_regwen_38_we; - reg_we_check[154] = mio_outsel_regwen_39_we; - reg_we_check[155] = mio_outsel_regwen_40_we; - reg_we_check[156] = mio_outsel_regwen_41_we; - reg_we_check[157] = mio_outsel_regwen_42_we; - reg_we_check[158] = mio_outsel_regwen_43_we; - reg_we_check[159] = mio_outsel_regwen_44_we; - reg_we_check[160] = mio_outsel_regwen_45_we; - reg_we_check[161] = mio_outsel_regwen_46_we; - reg_we_check[162] = mio_outsel_0_gated_we; - reg_we_check[163] = mio_outsel_1_gated_we; - reg_we_check[164] = mio_outsel_2_gated_we; - reg_we_check[165] = mio_outsel_3_gated_we; - reg_we_check[166] = mio_outsel_4_gated_we; - reg_we_check[167] = mio_outsel_5_gated_we; - reg_we_check[168] = mio_outsel_6_gated_we; - reg_we_check[169] = mio_outsel_7_gated_we; - reg_we_check[170] = mio_outsel_8_gated_we; - reg_we_check[171] = mio_outsel_9_gated_we; - reg_we_check[172] = mio_outsel_10_gated_we; - reg_we_check[173] = mio_outsel_11_gated_we; - reg_we_check[174] = mio_outsel_12_gated_we; - reg_we_check[175] = mio_outsel_13_gated_we; - reg_we_check[176] = mio_outsel_14_gated_we; - reg_we_check[177] = mio_outsel_15_gated_we; - reg_we_check[178] = mio_outsel_16_gated_we; - reg_we_check[179] = mio_outsel_17_gated_we; - reg_we_check[180] = mio_outsel_18_gated_we; - reg_we_check[181] = mio_outsel_19_gated_we; - reg_we_check[182] = mio_outsel_20_gated_we; - reg_we_check[183] = mio_outsel_21_gated_we; - reg_we_check[184] = mio_outsel_22_gated_we; - reg_we_check[185] = mio_outsel_23_gated_we; - reg_we_check[186] = mio_outsel_24_gated_we; - reg_we_check[187] = mio_outsel_25_gated_we; - reg_we_check[188] = mio_outsel_26_gated_we; - reg_we_check[189] = mio_outsel_27_gated_we; - reg_we_check[190] = mio_outsel_28_gated_we; - reg_we_check[191] = mio_outsel_29_gated_we; - reg_we_check[192] = mio_outsel_30_gated_we; - reg_we_check[193] = mio_outsel_31_gated_we; - reg_we_check[194] = mio_outsel_32_gated_we; - reg_we_check[195] = mio_outsel_33_gated_we; - reg_we_check[196] = mio_outsel_34_gated_we; - reg_we_check[197] = mio_outsel_35_gated_we; - reg_we_check[198] = mio_outsel_36_gated_we; - reg_we_check[199] = mio_outsel_37_gated_we; - reg_we_check[200] = mio_outsel_38_gated_we; - reg_we_check[201] = mio_outsel_39_gated_we; - reg_we_check[202] = mio_outsel_40_gated_we; - reg_we_check[203] = mio_outsel_41_gated_we; - reg_we_check[204] = mio_outsel_42_gated_we; - reg_we_check[205] = mio_outsel_43_gated_we; - reg_we_check[206] = mio_outsel_44_gated_we; - reg_we_check[207] = mio_outsel_45_gated_we; - reg_we_check[208] = mio_outsel_46_gated_we; - reg_we_check[209] = mio_pad_attr_regwen_0_we; - reg_we_check[210] = mio_pad_attr_regwen_1_we; - reg_we_check[211] = mio_pad_attr_regwen_2_we; - reg_we_check[212] = mio_pad_attr_regwen_3_we; - reg_we_check[213] = mio_pad_attr_regwen_4_we; - reg_we_check[214] = mio_pad_attr_regwen_5_we; - reg_we_check[215] = mio_pad_attr_regwen_6_we; - reg_we_check[216] = mio_pad_attr_regwen_7_we; - reg_we_check[217] = mio_pad_attr_regwen_8_we; - reg_we_check[218] = mio_pad_attr_regwen_9_we; - reg_we_check[219] = mio_pad_attr_regwen_10_we; - reg_we_check[220] = mio_pad_attr_regwen_11_we; - reg_we_check[221] = mio_pad_attr_regwen_12_we; - reg_we_check[222] = mio_pad_attr_regwen_13_we; - reg_we_check[223] = mio_pad_attr_regwen_14_we; - reg_we_check[224] = mio_pad_attr_regwen_15_we; - reg_we_check[225] = mio_pad_attr_regwen_16_we; - reg_we_check[226] = mio_pad_attr_regwen_17_we; - reg_we_check[227] = mio_pad_attr_regwen_18_we; - reg_we_check[228] = mio_pad_attr_regwen_19_we; - reg_we_check[229] = mio_pad_attr_regwen_20_we; - reg_we_check[230] = mio_pad_attr_regwen_21_we; - reg_we_check[231] = mio_pad_attr_regwen_22_we; - reg_we_check[232] = mio_pad_attr_regwen_23_we; - reg_we_check[233] = mio_pad_attr_regwen_24_we; - reg_we_check[234] = mio_pad_attr_regwen_25_we; - reg_we_check[235] = mio_pad_attr_regwen_26_we; - reg_we_check[236] = mio_pad_attr_regwen_27_we; - reg_we_check[237] = mio_pad_attr_regwen_28_we; - reg_we_check[238] = mio_pad_attr_regwen_29_we; - reg_we_check[239] = mio_pad_attr_regwen_30_we; - reg_we_check[240] = mio_pad_attr_regwen_31_we; - reg_we_check[241] = mio_pad_attr_regwen_32_we; - reg_we_check[242] = mio_pad_attr_regwen_33_we; - reg_we_check[243] = mio_pad_attr_regwen_34_we; - reg_we_check[244] = mio_pad_attr_regwen_35_we; - reg_we_check[245] = mio_pad_attr_regwen_36_we; - reg_we_check[246] = mio_pad_attr_regwen_37_we; - reg_we_check[247] = mio_pad_attr_regwen_38_we; - reg_we_check[248] = mio_pad_attr_regwen_39_we; - reg_we_check[249] = mio_pad_attr_regwen_40_we; - reg_we_check[250] = mio_pad_attr_regwen_41_we; - reg_we_check[251] = mio_pad_attr_regwen_42_we; - reg_we_check[252] = mio_pad_attr_regwen_43_we; - reg_we_check[253] = mio_pad_attr_regwen_44_we; - reg_we_check[254] = mio_pad_attr_regwen_45_we; - reg_we_check[255] = mio_pad_attr_regwen_46_we; - reg_we_check[256] = mio_pad_attr_0_gated_we; - reg_we_check[257] = mio_pad_attr_1_gated_we; - reg_we_check[258] = mio_pad_attr_2_gated_we; - reg_we_check[259] = mio_pad_attr_3_gated_we; - reg_we_check[260] = mio_pad_attr_4_gated_we; - reg_we_check[261] = mio_pad_attr_5_gated_we; - reg_we_check[262] = mio_pad_attr_6_gated_we; - reg_we_check[263] = mio_pad_attr_7_gated_we; - reg_we_check[264] = mio_pad_attr_8_gated_we; - reg_we_check[265] = mio_pad_attr_9_gated_we; - reg_we_check[266] = mio_pad_attr_10_gated_we; - reg_we_check[267] = mio_pad_attr_11_gated_we; - reg_we_check[268] = mio_pad_attr_12_gated_we; - reg_we_check[269] = mio_pad_attr_13_gated_we; - reg_we_check[270] = mio_pad_attr_14_gated_we; - reg_we_check[271] = mio_pad_attr_15_gated_we; - reg_we_check[272] = mio_pad_attr_16_gated_we; - reg_we_check[273] = mio_pad_attr_17_gated_we; - reg_we_check[274] = mio_pad_attr_18_gated_we; - reg_we_check[275] = mio_pad_attr_19_gated_we; - reg_we_check[276] = mio_pad_attr_20_gated_we; - reg_we_check[277] = mio_pad_attr_21_gated_we; - reg_we_check[278] = mio_pad_attr_22_gated_we; - reg_we_check[279] = mio_pad_attr_23_gated_we; - reg_we_check[280] = mio_pad_attr_24_gated_we; - reg_we_check[281] = mio_pad_attr_25_gated_we; - reg_we_check[282] = mio_pad_attr_26_gated_we; - reg_we_check[283] = mio_pad_attr_27_gated_we; - reg_we_check[284] = mio_pad_attr_28_gated_we; - reg_we_check[285] = mio_pad_attr_29_gated_we; - reg_we_check[286] = mio_pad_attr_30_gated_we; - reg_we_check[287] = mio_pad_attr_31_gated_we; - reg_we_check[288] = mio_pad_attr_32_gated_we; - reg_we_check[289] = mio_pad_attr_33_gated_we; - reg_we_check[290] = mio_pad_attr_34_gated_we; - reg_we_check[291] = mio_pad_attr_35_gated_we; - reg_we_check[292] = mio_pad_attr_36_gated_we; - reg_we_check[293] = mio_pad_attr_37_gated_we; - reg_we_check[294] = mio_pad_attr_38_gated_we; - reg_we_check[295] = mio_pad_attr_39_gated_we; - reg_we_check[296] = mio_pad_attr_40_gated_we; - reg_we_check[297] = mio_pad_attr_41_gated_we; - reg_we_check[298] = mio_pad_attr_42_gated_we; - reg_we_check[299] = mio_pad_attr_43_gated_we; - reg_we_check[300] = mio_pad_attr_44_gated_we; - reg_we_check[301] = mio_pad_attr_45_gated_we; - reg_we_check[302] = mio_pad_attr_46_gated_we; - reg_we_check[303] = dio_pad_attr_regwen_0_we; - reg_we_check[304] = dio_pad_attr_regwen_1_we; - reg_we_check[305] = dio_pad_attr_regwen_2_we; - reg_we_check[306] = dio_pad_attr_regwen_3_we; - reg_we_check[307] = dio_pad_attr_regwen_4_we; - reg_we_check[308] = dio_pad_attr_regwen_5_we; - reg_we_check[309] = dio_pad_attr_regwen_6_we; - reg_we_check[310] = dio_pad_attr_regwen_7_we; - reg_we_check[311] = dio_pad_attr_regwen_8_we; - reg_we_check[312] = dio_pad_attr_regwen_9_we; - reg_we_check[313] = dio_pad_attr_regwen_10_we; - reg_we_check[314] = dio_pad_attr_regwen_11_we; - reg_we_check[315] = dio_pad_attr_regwen_12_we; - reg_we_check[316] = dio_pad_attr_regwen_13_we; - reg_we_check[317] = dio_pad_attr_regwen_14_we; - reg_we_check[318] = dio_pad_attr_regwen_15_we; - reg_we_check[319] = dio_pad_attr_0_gated_we; - reg_we_check[320] = dio_pad_attr_1_gated_we; - reg_we_check[321] = dio_pad_attr_2_gated_we; - reg_we_check[322] = dio_pad_attr_3_gated_we; - reg_we_check[323] = dio_pad_attr_4_gated_we; - reg_we_check[324] = dio_pad_attr_5_gated_we; - reg_we_check[325] = dio_pad_attr_6_gated_we; - reg_we_check[326] = dio_pad_attr_7_gated_we; - reg_we_check[327] = dio_pad_attr_8_gated_we; - reg_we_check[328] = dio_pad_attr_9_gated_we; - reg_we_check[329] = dio_pad_attr_10_gated_we; - reg_we_check[330] = dio_pad_attr_11_gated_we; - reg_we_check[331] = dio_pad_attr_12_gated_we; - reg_we_check[332] = dio_pad_attr_13_gated_we; - reg_we_check[333] = dio_pad_attr_14_gated_we; - reg_we_check[334] = dio_pad_attr_15_gated_we; - reg_we_check[335] = mio_pad_sleep_status_0_we; - reg_we_check[336] = mio_pad_sleep_status_1_we; - reg_we_check[337] = mio_pad_sleep_regwen_0_we; - reg_we_check[338] = mio_pad_sleep_regwen_1_we; - reg_we_check[339] = mio_pad_sleep_regwen_2_we; - reg_we_check[340] = mio_pad_sleep_regwen_3_we; - reg_we_check[341] = mio_pad_sleep_regwen_4_we; - reg_we_check[342] = mio_pad_sleep_regwen_5_we; - reg_we_check[343] = mio_pad_sleep_regwen_6_we; - reg_we_check[344] = mio_pad_sleep_regwen_7_we; - reg_we_check[345] = mio_pad_sleep_regwen_8_we; - reg_we_check[346] = mio_pad_sleep_regwen_9_we; - reg_we_check[347] = mio_pad_sleep_regwen_10_we; - reg_we_check[348] = mio_pad_sleep_regwen_11_we; - reg_we_check[349] = mio_pad_sleep_regwen_12_we; - reg_we_check[350] = mio_pad_sleep_regwen_13_we; - reg_we_check[351] = mio_pad_sleep_regwen_14_we; - reg_we_check[352] = mio_pad_sleep_regwen_15_we; - reg_we_check[353] = mio_pad_sleep_regwen_16_we; - reg_we_check[354] = mio_pad_sleep_regwen_17_we; - reg_we_check[355] = mio_pad_sleep_regwen_18_we; - reg_we_check[356] = mio_pad_sleep_regwen_19_we; - reg_we_check[357] = mio_pad_sleep_regwen_20_we; - reg_we_check[358] = mio_pad_sleep_regwen_21_we; - reg_we_check[359] = mio_pad_sleep_regwen_22_we; - reg_we_check[360] = mio_pad_sleep_regwen_23_we; - reg_we_check[361] = mio_pad_sleep_regwen_24_we; - reg_we_check[362] = mio_pad_sleep_regwen_25_we; - reg_we_check[363] = mio_pad_sleep_regwen_26_we; - reg_we_check[364] = mio_pad_sleep_regwen_27_we; - reg_we_check[365] = mio_pad_sleep_regwen_28_we; - reg_we_check[366] = mio_pad_sleep_regwen_29_we; - reg_we_check[367] = mio_pad_sleep_regwen_30_we; - reg_we_check[368] = mio_pad_sleep_regwen_31_we; - reg_we_check[369] = mio_pad_sleep_regwen_32_we; - reg_we_check[370] = mio_pad_sleep_regwen_33_we; - reg_we_check[371] = mio_pad_sleep_regwen_34_we; - reg_we_check[372] = mio_pad_sleep_regwen_35_we; - reg_we_check[373] = mio_pad_sleep_regwen_36_we; - reg_we_check[374] = mio_pad_sleep_regwen_37_we; - reg_we_check[375] = mio_pad_sleep_regwen_38_we; - reg_we_check[376] = mio_pad_sleep_regwen_39_we; - reg_we_check[377] = mio_pad_sleep_regwen_40_we; - reg_we_check[378] = mio_pad_sleep_regwen_41_we; - reg_we_check[379] = mio_pad_sleep_regwen_42_we; - reg_we_check[380] = mio_pad_sleep_regwen_43_we; - reg_we_check[381] = mio_pad_sleep_regwen_44_we; - reg_we_check[382] = mio_pad_sleep_regwen_45_we; - reg_we_check[383] = mio_pad_sleep_regwen_46_we; - reg_we_check[384] = mio_pad_sleep_en_0_gated_we; - reg_we_check[385] = mio_pad_sleep_en_1_gated_we; - reg_we_check[386] = mio_pad_sleep_en_2_gated_we; - reg_we_check[387] = mio_pad_sleep_en_3_gated_we; - reg_we_check[388] = mio_pad_sleep_en_4_gated_we; - reg_we_check[389] = mio_pad_sleep_en_5_gated_we; - reg_we_check[390] = mio_pad_sleep_en_6_gated_we; - reg_we_check[391] = mio_pad_sleep_en_7_gated_we; - reg_we_check[392] = mio_pad_sleep_en_8_gated_we; - reg_we_check[393] = mio_pad_sleep_en_9_gated_we; - reg_we_check[394] = mio_pad_sleep_en_10_gated_we; - reg_we_check[395] = mio_pad_sleep_en_11_gated_we; - reg_we_check[396] = mio_pad_sleep_en_12_gated_we; - reg_we_check[397] = mio_pad_sleep_en_13_gated_we; - reg_we_check[398] = mio_pad_sleep_en_14_gated_we; - reg_we_check[399] = mio_pad_sleep_en_15_gated_we; - reg_we_check[400] = mio_pad_sleep_en_16_gated_we; - reg_we_check[401] = mio_pad_sleep_en_17_gated_we; - reg_we_check[402] = mio_pad_sleep_en_18_gated_we; - reg_we_check[403] = mio_pad_sleep_en_19_gated_we; - reg_we_check[404] = mio_pad_sleep_en_20_gated_we; - reg_we_check[405] = mio_pad_sleep_en_21_gated_we; - reg_we_check[406] = mio_pad_sleep_en_22_gated_we; - reg_we_check[407] = mio_pad_sleep_en_23_gated_we; - reg_we_check[408] = mio_pad_sleep_en_24_gated_we; - reg_we_check[409] = mio_pad_sleep_en_25_gated_we; - reg_we_check[410] = mio_pad_sleep_en_26_gated_we; - reg_we_check[411] = mio_pad_sleep_en_27_gated_we; - reg_we_check[412] = mio_pad_sleep_en_28_gated_we; - reg_we_check[413] = mio_pad_sleep_en_29_gated_we; - reg_we_check[414] = mio_pad_sleep_en_30_gated_we; - reg_we_check[415] = mio_pad_sleep_en_31_gated_we; - reg_we_check[416] = mio_pad_sleep_en_32_gated_we; - reg_we_check[417] = mio_pad_sleep_en_33_gated_we; - reg_we_check[418] = mio_pad_sleep_en_34_gated_we; - reg_we_check[419] = mio_pad_sleep_en_35_gated_we; - reg_we_check[420] = mio_pad_sleep_en_36_gated_we; - reg_we_check[421] = mio_pad_sleep_en_37_gated_we; - reg_we_check[422] = mio_pad_sleep_en_38_gated_we; - reg_we_check[423] = mio_pad_sleep_en_39_gated_we; - reg_we_check[424] = mio_pad_sleep_en_40_gated_we; - reg_we_check[425] = mio_pad_sleep_en_41_gated_we; - reg_we_check[426] = mio_pad_sleep_en_42_gated_we; - reg_we_check[427] = mio_pad_sleep_en_43_gated_we; - reg_we_check[428] = mio_pad_sleep_en_44_gated_we; - reg_we_check[429] = mio_pad_sleep_en_45_gated_we; - reg_we_check[430] = mio_pad_sleep_en_46_gated_we; - reg_we_check[431] = mio_pad_sleep_mode_0_gated_we; - reg_we_check[432] = mio_pad_sleep_mode_1_gated_we; - reg_we_check[433] = mio_pad_sleep_mode_2_gated_we; - reg_we_check[434] = mio_pad_sleep_mode_3_gated_we; - reg_we_check[435] = mio_pad_sleep_mode_4_gated_we; - reg_we_check[436] = mio_pad_sleep_mode_5_gated_we; - reg_we_check[437] = mio_pad_sleep_mode_6_gated_we; - reg_we_check[438] = mio_pad_sleep_mode_7_gated_we; - reg_we_check[439] = mio_pad_sleep_mode_8_gated_we; - reg_we_check[440] = mio_pad_sleep_mode_9_gated_we; - reg_we_check[441] = mio_pad_sleep_mode_10_gated_we; - reg_we_check[442] = mio_pad_sleep_mode_11_gated_we; - reg_we_check[443] = mio_pad_sleep_mode_12_gated_we; - reg_we_check[444] = mio_pad_sleep_mode_13_gated_we; - reg_we_check[445] = mio_pad_sleep_mode_14_gated_we; - reg_we_check[446] = mio_pad_sleep_mode_15_gated_we; - reg_we_check[447] = mio_pad_sleep_mode_16_gated_we; - reg_we_check[448] = mio_pad_sleep_mode_17_gated_we; - reg_we_check[449] = mio_pad_sleep_mode_18_gated_we; - reg_we_check[450] = mio_pad_sleep_mode_19_gated_we; - reg_we_check[451] = mio_pad_sleep_mode_20_gated_we; - reg_we_check[452] = mio_pad_sleep_mode_21_gated_we; - reg_we_check[453] = mio_pad_sleep_mode_22_gated_we; - reg_we_check[454] = mio_pad_sleep_mode_23_gated_we; - reg_we_check[455] = mio_pad_sleep_mode_24_gated_we; - reg_we_check[456] = mio_pad_sleep_mode_25_gated_we; - reg_we_check[457] = mio_pad_sleep_mode_26_gated_we; - reg_we_check[458] = mio_pad_sleep_mode_27_gated_we; - reg_we_check[459] = mio_pad_sleep_mode_28_gated_we; - reg_we_check[460] = mio_pad_sleep_mode_29_gated_we; - reg_we_check[461] = mio_pad_sleep_mode_30_gated_we; - reg_we_check[462] = mio_pad_sleep_mode_31_gated_we; - reg_we_check[463] = mio_pad_sleep_mode_32_gated_we; - reg_we_check[464] = mio_pad_sleep_mode_33_gated_we; - reg_we_check[465] = mio_pad_sleep_mode_34_gated_we; - reg_we_check[466] = mio_pad_sleep_mode_35_gated_we; - reg_we_check[467] = mio_pad_sleep_mode_36_gated_we; - reg_we_check[468] = mio_pad_sleep_mode_37_gated_we; - reg_we_check[469] = mio_pad_sleep_mode_38_gated_we; - reg_we_check[470] = mio_pad_sleep_mode_39_gated_we; - reg_we_check[471] = mio_pad_sleep_mode_40_gated_we; - reg_we_check[472] = mio_pad_sleep_mode_41_gated_we; - reg_we_check[473] = mio_pad_sleep_mode_42_gated_we; - reg_we_check[474] = mio_pad_sleep_mode_43_gated_we; - reg_we_check[475] = mio_pad_sleep_mode_44_gated_we; - reg_we_check[476] = mio_pad_sleep_mode_45_gated_we; - reg_we_check[477] = mio_pad_sleep_mode_46_gated_we; - reg_we_check[478] = dio_pad_sleep_status_we; - reg_we_check[479] = dio_pad_sleep_regwen_0_we; - reg_we_check[480] = dio_pad_sleep_regwen_1_we; - reg_we_check[481] = dio_pad_sleep_regwen_2_we; - reg_we_check[482] = dio_pad_sleep_regwen_3_we; - reg_we_check[483] = dio_pad_sleep_regwen_4_we; - reg_we_check[484] = dio_pad_sleep_regwen_5_we; - reg_we_check[485] = dio_pad_sleep_regwen_6_we; - reg_we_check[486] = dio_pad_sleep_regwen_7_we; - reg_we_check[487] = dio_pad_sleep_regwen_8_we; - reg_we_check[488] = dio_pad_sleep_regwen_9_we; - reg_we_check[489] = dio_pad_sleep_regwen_10_we; - reg_we_check[490] = dio_pad_sleep_regwen_11_we; - reg_we_check[491] = dio_pad_sleep_regwen_12_we; - reg_we_check[492] = dio_pad_sleep_regwen_13_we; - reg_we_check[493] = dio_pad_sleep_regwen_14_we; - reg_we_check[494] = dio_pad_sleep_regwen_15_we; - reg_we_check[495] = dio_pad_sleep_en_0_gated_we; - reg_we_check[496] = dio_pad_sleep_en_1_gated_we; - reg_we_check[497] = dio_pad_sleep_en_2_gated_we; - reg_we_check[498] = dio_pad_sleep_en_3_gated_we; - reg_we_check[499] = dio_pad_sleep_en_4_gated_we; - reg_we_check[500] = dio_pad_sleep_en_5_gated_we; - reg_we_check[501] = dio_pad_sleep_en_6_gated_we; - reg_we_check[502] = dio_pad_sleep_en_7_gated_we; - reg_we_check[503] = dio_pad_sleep_en_8_gated_we; - reg_we_check[504] = dio_pad_sleep_en_9_gated_we; - reg_we_check[505] = dio_pad_sleep_en_10_gated_we; - reg_we_check[506] = dio_pad_sleep_en_11_gated_we; - reg_we_check[507] = dio_pad_sleep_en_12_gated_we; - reg_we_check[508] = dio_pad_sleep_en_13_gated_we; - reg_we_check[509] = dio_pad_sleep_en_14_gated_we; - reg_we_check[510] = dio_pad_sleep_en_15_gated_we; - reg_we_check[511] = dio_pad_sleep_mode_0_gated_we; - reg_we_check[512] = dio_pad_sleep_mode_1_gated_we; - reg_we_check[513] = dio_pad_sleep_mode_2_gated_we; - reg_we_check[514] = dio_pad_sleep_mode_3_gated_we; - reg_we_check[515] = dio_pad_sleep_mode_4_gated_we; - reg_we_check[516] = dio_pad_sleep_mode_5_gated_we; - reg_we_check[517] = dio_pad_sleep_mode_6_gated_we; - reg_we_check[518] = dio_pad_sleep_mode_7_gated_we; - reg_we_check[519] = dio_pad_sleep_mode_8_gated_we; - reg_we_check[520] = dio_pad_sleep_mode_9_gated_we; - reg_we_check[521] = dio_pad_sleep_mode_10_gated_we; - reg_we_check[522] = dio_pad_sleep_mode_11_gated_we; - reg_we_check[523] = dio_pad_sleep_mode_12_gated_we; - reg_we_check[524] = dio_pad_sleep_mode_13_gated_we; - reg_we_check[525] = dio_pad_sleep_mode_14_gated_we; - reg_we_check[526] = dio_pad_sleep_mode_15_gated_we; - reg_we_check[527] = wkup_detector_regwen_0_we; - reg_we_check[528] = wkup_detector_regwen_1_we; - reg_we_check[529] = wkup_detector_regwen_2_we; - reg_we_check[530] = wkup_detector_regwen_3_we; - reg_we_check[531] = wkup_detector_regwen_4_we; - reg_we_check[532] = wkup_detector_regwen_5_we; - reg_we_check[533] = wkup_detector_regwen_6_we; - reg_we_check[534] = wkup_detector_regwen_7_we; - reg_we_check[535] = wkup_detector_en_0_we; - reg_we_check[536] = wkup_detector_en_1_we; - reg_we_check[537] = wkup_detector_en_2_we; - reg_we_check[538] = wkup_detector_en_3_we; - reg_we_check[539] = wkup_detector_en_4_we; - reg_we_check[540] = wkup_detector_en_5_we; - reg_we_check[541] = wkup_detector_en_6_we; - reg_we_check[542] = wkup_detector_en_7_we; - reg_we_check[543] = wkup_detector_0_we; - reg_we_check[544] = wkup_detector_1_we; - reg_we_check[545] = wkup_detector_2_we; - reg_we_check[546] = wkup_detector_3_we; - reg_we_check[547] = wkup_detector_4_we; - reg_we_check[548] = wkup_detector_5_we; - reg_we_check[549] = wkup_detector_6_we; - reg_we_check[550] = wkup_detector_7_we; - reg_we_check[551] = wkup_detector_cnt_th_0_we; - reg_we_check[552] = wkup_detector_cnt_th_1_we; - reg_we_check[553] = wkup_detector_cnt_th_2_we; - reg_we_check[554] = wkup_detector_cnt_th_3_we; - reg_we_check[555] = wkup_detector_cnt_th_4_we; - reg_we_check[556] = wkup_detector_cnt_th_5_we; - reg_we_check[557] = wkup_detector_cnt_th_6_we; - reg_we_check[558] = wkup_detector_cnt_th_7_we; - reg_we_check[559] = wkup_detector_padsel_0_gated_we; - reg_we_check[560] = wkup_detector_padsel_1_gated_we; - reg_we_check[561] = wkup_detector_padsel_2_gated_we; - reg_we_check[562] = wkup_detector_padsel_3_gated_we; - reg_we_check[563] = wkup_detector_padsel_4_gated_we; - reg_we_check[564] = wkup_detector_padsel_5_gated_we; - reg_we_check[565] = wkup_detector_padsel_6_gated_we; - reg_we_check[566] = wkup_detector_padsel_7_gated_we; - reg_we_check[567] = wkup_cause_we; + reg_we_check[58] = mio_periph_insel_regwen_57_we; + reg_we_check[59] = mio_periph_insel_regwen_58_we; + reg_we_check[60] = mio_periph_insel_0_gated_we; + reg_we_check[61] = mio_periph_insel_1_gated_we; + reg_we_check[62] = mio_periph_insel_2_gated_we; + reg_we_check[63] = mio_periph_insel_3_gated_we; + reg_we_check[64] = mio_periph_insel_4_gated_we; + reg_we_check[65] = mio_periph_insel_5_gated_we; + reg_we_check[66] = mio_periph_insel_6_gated_we; + reg_we_check[67] = mio_periph_insel_7_gated_we; + reg_we_check[68] = mio_periph_insel_8_gated_we; + reg_we_check[69] = mio_periph_insel_9_gated_we; + reg_we_check[70] = mio_periph_insel_10_gated_we; + reg_we_check[71] = mio_periph_insel_11_gated_we; + reg_we_check[72] = mio_periph_insel_12_gated_we; + reg_we_check[73] = mio_periph_insel_13_gated_we; + reg_we_check[74] = mio_periph_insel_14_gated_we; + reg_we_check[75] = mio_periph_insel_15_gated_we; + reg_we_check[76] = mio_periph_insel_16_gated_we; + reg_we_check[77] = mio_periph_insel_17_gated_we; + reg_we_check[78] = mio_periph_insel_18_gated_we; + reg_we_check[79] = mio_periph_insel_19_gated_we; + reg_we_check[80] = mio_periph_insel_20_gated_we; + reg_we_check[81] = mio_periph_insel_21_gated_we; + reg_we_check[82] = mio_periph_insel_22_gated_we; + reg_we_check[83] = mio_periph_insel_23_gated_we; + reg_we_check[84] = mio_periph_insel_24_gated_we; + reg_we_check[85] = mio_periph_insel_25_gated_we; + reg_we_check[86] = mio_periph_insel_26_gated_we; + reg_we_check[87] = mio_periph_insel_27_gated_we; + reg_we_check[88] = mio_periph_insel_28_gated_we; + reg_we_check[89] = mio_periph_insel_29_gated_we; + reg_we_check[90] = mio_periph_insel_30_gated_we; + reg_we_check[91] = mio_periph_insel_31_gated_we; + reg_we_check[92] = mio_periph_insel_32_gated_we; + reg_we_check[93] = mio_periph_insel_33_gated_we; + reg_we_check[94] = mio_periph_insel_34_gated_we; + reg_we_check[95] = mio_periph_insel_35_gated_we; + reg_we_check[96] = mio_periph_insel_36_gated_we; + reg_we_check[97] = mio_periph_insel_37_gated_we; + reg_we_check[98] = mio_periph_insel_38_gated_we; + reg_we_check[99] = mio_periph_insel_39_gated_we; + reg_we_check[100] = mio_periph_insel_40_gated_we; + reg_we_check[101] = mio_periph_insel_41_gated_we; + reg_we_check[102] = mio_periph_insel_42_gated_we; + reg_we_check[103] = mio_periph_insel_43_gated_we; + reg_we_check[104] = mio_periph_insel_44_gated_we; + reg_we_check[105] = mio_periph_insel_45_gated_we; + reg_we_check[106] = mio_periph_insel_46_gated_we; + reg_we_check[107] = mio_periph_insel_47_gated_we; + reg_we_check[108] = mio_periph_insel_48_gated_we; + reg_we_check[109] = mio_periph_insel_49_gated_we; + reg_we_check[110] = mio_periph_insel_50_gated_we; + reg_we_check[111] = mio_periph_insel_51_gated_we; + reg_we_check[112] = mio_periph_insel_52_gated_we; + reg_we_check[113] = mio_periph_insel_53_gated_we; + reg_we_check[114] = mio_periph_insel_54_gated_we; + reg_we_check[115] = mio_periph_insel_55_gated_we; + reg_we_check[116] = mio_periph_insel_56_gated_we; + reg_we_check[117] = mio_periph_insel_57_gated_we; + reg_we_check[118] = mio_periph_insel_58_gated_we; + reg_we_check[119] = mio_outsel_regwen_0_we; + reg_we_check[120] = mio_outsel_regwen_1_we; + reg_we_check[121] = mio_outsel_regwen_2_we; + reg_we_check[122] = mio_outsel_regwen_3_we; + reg_we_check[123] = mio_outsel_regwen_4_we; + reg_we_check[124] = mio_outsel_regwen_5_we; + reg_we_check[125] = mio_outsel_regwen_6_we; + reg_we_check[126] = mio_outsel_regwen_7_we; + reg_we_check[127] = mio_outsel_regwen_8_we; + reg_we_check[128] = mio_outsel_regwen_9_we; + reg_we_check[129] = mio_outsel_regwen_10_we; + reg_we_check[130] = mio_outsel_regwen_11_we; + reg_we_check[131] = mio_outsel_regwen_12_we; + reg_we_check[132] = mio_outsel_regwen_13_we; + reg_we_check[133] = mio_outsel_regwen_14_we; + reg_we_check[134] = mio_outsel_regwen_15_we; + reg_we_check[135] = mio_outsel_regwen_16_we; + reg_we_check[136] = mio_outsel_regwen_17_we; + reg_we_check[137] = mio_outsel_regwen_18_we; + reg_we_check[138] = mio_outsel_regwen_19_we; + reg_we_check[139] = mio_outsel_regwen_20_we; + reg_we_check[140] = mio_outsel_regwen_21_we; + reg_we_check[141] = mio_outsel_regwen_22_we; + reg_we_check[142] = mio_outsel_regwen_23_we; + reg_we_check[143] = mio_outsel_regwen_24_we; + reg_we_check[144] = mio_outsel_regwen_25_we; + reg_we_check[145] = mio_outsel_regwen_26_we; + reg_we_check[146] = mio_outsel_regwen_27_we; + reg_we_check[147] = mio_outsel_regwen_28_we; + reg_we_check[148] = mio_outsel_regwen_29_we; + reg_we_check[149] = mio_outsel_regwen_30_we; + reg_we_check[150] = mio_outsel_regwen_31_we; + reg_we_check[151] = mio_outsel_regwen_32_we; + reg_we_check[152] = mio_outsel_regwen_33_we; + reg_we_check[153] = mio_outsel_regwen_34_we; + reg_we_check[154] = mio_outsel_regwen_35_we; + reg_we_check[155] = mio_outsel_regwen_36_we; + reg_we_check[156] = mio_outsel_regwen_37_we; + reg_we_check[157] = mio_outsel_regwen_38_we; + reg_we_check[158] = mio_outsel_regwen_39_we; + reg_we_check[159] = mio_outsel_regwen_40_we; + reg_we_check[160] = mio_outsel_regwen_41_we; + reg_we_check[161] = mio_outsel_regwen_42_we; + reg_we_check[162] = mio_outsel_regwen_43_we; + reg_we_check[163] = mio_outsel_regwen_44_we; + reg_we_check[164] = mio_outsel_regwen_45_we; + reg_we_check[165] = mio_outsel_regwen_46_we; + reg_we_check[166] = mio_outsel_0_gated_we; + reg_we_check[167] = mio_outsel_1_gated_we; + reg_we_check[168] = mio_outsel_2_gated_we; + reg_we_check[169] = mio_outsel_3_gated_we; + reg_we_check[170] = mio_outsel_4_gated_we; + reg_we_check[171] = mio_outsel_5_gated_we; + reg_we_check[172] = mio_outsel_6_gated_we; + reg_we_check[173] = mio_outsel_7_gated_we; + reg_we_check[174] = mio_outsel_8_gated_we; + reg_we_check[175] = mio_outsel_9_gated_we; + reg_we_check[176] = mio_outsel_10_gated_we; + reg_we_check[177] = mio_outsel_11_gated_we; + reg_we_check[178] = mio_outsel_12_gated_we; + reg_we_check[179] = mio_outsel_13_gated_we; + reg_we_check[180] = mio_outsel_14_gated_we; + reg_we_check[181] = mio_outsel_15_gated_we; + reg_we_check[182] = mio_outsel_16_gated_we; + reg_we_check[183] = mio_outsel_17_gated_we; + reg_we_check[184] = mio_outsel_18_gated_we; + reg_we_check[185] = mio_outsel_19_gated_we; + reg_we_check[186] = mio_outsel_20_gated_we; + reg_we_check[187] = mio_outsel_21_gated_we; + reg_we_check[188] = mio_outsel_22_gated_we; + reg_we_check[189] = mio_outsel_23_gated_we; + reg_we_check[190] = mio_outsel_24_gated_we; + reg_we_check[191] = mio_outsel_25_gated_we; + reg_we_check[192] = mio_outsel_26_gated_we; + reg_we_check[193] = mio_outsel_27_gated_we; + reg_we_check[194] = mio_outsel_28_gated_we; + reg_we_check[195] = mio_outsel_29_gated_we; + reg_we_check[196] = mio_outsel_30_gated_we; + reg_we_check[197] = mio_outsel_31_gated_we; + reg_we_check[198] = mio_outsel_32_gated_we; + reg_we_check[199] = mio_outsel_33_gated_we; + reg_we_check[200] = mio_outsel_34_gated_we; + reg_we_check[201] = mio_outsel_35_gated_we; + reg_we_check[202] = mio_outsel_36_gated_we; + reg_we_check[203] = mio_outsel_37_gated_we; + reg_we_check[204] = mio_outsel_38_gated_we; + reg_we_check[205] = mio_outsel_39_gated_we; + reg_we_check[206] = mio_outsel_40_gated_we; + reg_we_check[207] = mio_outsel_41_gated_we; + reg_we_check[208] = mio_outsel_42_gated_we; + reg_we_check[209] = mio_outsel_43_gated_we; + reg_we_check[210] = mio_outsel_44_gated_we; + reg_we_check[211] = mio_outsel_45_gated_we; + reg_we_check[212] = mio_outsel_46_gated_we; + reg_we_check[213] = mio_pad_attr_regwen_0_we; + reg_we_check[214] = mio_pad_attr_regwen_1_we; + reg_we_check[215] = mio_pad_attr_regwen_2_we; + reg_we_check[216] = mio_pad_attr_regwen_3_we; + reg_we_check[217] = mio_pad_attr_regwen_4_we; + reg_we_check[218] = mio_pad_attr_regwen_5_we; + reg_we_check[219] = mio_pad_attr_regwen_6_we; + reg_we_check[220] = mio_pad_attr_regwen_7_we; + reg_we_check[221] = mio_pad_attr_regwen_8_we; + reg_we_check[222] = mio_pad_attr_regwen_9_we; + reg_we_check[223] = mio_pad_attr_regwen_10_we; + reg_we_check[224] = mio_pad_attr_regwen_11_we; + reg_we_check[225] = mio_pad_attr_regwen_12_we; + reg_we_check[226] = mio_pad_attr_regwen_13_we; + reg_we_check[227] = mio_pad_attr_regwen_14_we; + reg_we_check[228] = mio_pad_attr_regwen_15_we; + reg_we_check[229] = mio_pad_attr_regwen_16_we; + reg_we_check[230] = mio_pad_attr_regwen_17_we; + reg_we_check[231] = mio_pad_attr_regwen_18_we; + reg_we_check[232] = mio_pad_attr_regwen_19_we; + reg_we_check[233] = mio_pad_attr_regwen_20_we; + reg_we_check[234] = mio_pad_attr_regwen_21_we; + reg_we_check[235] = mio_pad_attr_regwen_22_we; + reg_we_check[236] = mio_pad_attr_regwen_23_we; + reg_we_check[237] = mio_pad_attr_regwen_24_we; + reg_we_check[238] = mio_pad_attr_regwen_25_we; + reg_we_check[239] = mio_pad_attr_regwen_26_we; + reg_we_check[240] = mio_pad_attr_regwen_27_we; + reg_we_check[241] = mio_pad_attr_regwen_28_we; + reg_we_check[242] = mio_pad_attr_regwen_29_we; + reg_we_check[243] = mio_pad_attr_regwen_30_we; + reg_we_check[244] = mio_pad_attr_regwen_31_we; + reg_we_check[245] = mio_pad_attr_regwen_32_we; + reg_we_check[246] = mio_pad_attr_regwen_33_we; + reg_we_check[247] = mio_pad_attr_regwen_34_we; + reg_we_check[248] = mio_pad_attr_regwen_35_we; + reg_we_check[249] = mio_pad_attr_regwen_36_we; + reg_we_check[250] = mio_pad_attr_regwen_37_we; + reg_we_check[251] = mio_pad_attr_regwen_38_we; + reg_we_check[252] = mio_pad_attr_regwen_39_we; + reg_we_check[253] = mio_pad_attr_regwen_40_we; + reg_we_check[254] = mio_pad_attr_regwen_41_we; + reg_we_check[255] = mio_pad_attr_regwen_42_we; + reg_we_check[256] = mio_pad_attr_regwen_43_we; + reg_we_check[257] = mio_pad_attr_regwen_44_we; + reg_we_check[258] = mio_pad_attr_regwen_45_we; + reg_we_check[259] = mio_pad_attr_regwen_46_we; + reg_we_check[260] = mio_pad_attr_0_gated_we; + reg_we_check[261] = mio_pad_attr_1_gated_we; + reg_we_check[262] = mio_pad_attr_2_gated_we; + reg_we_check[263] = mio_pad_attr_3_gated_we; + reg_we_check[264] = mio_pad_attr_4_gated_we; + reg_we_check[265] = mio_pad_attr_5_gated_we; + reg_we_check[266] = mio_pad_attr_6_gated_we; + reg_we_check[267] = mio_pad_attr_7_gated_we; + reg_we_check[268] = mio_pad_attr_8_gated_we; + reg_we_check[269] = mio_pad_attr_9_gated_we; + reg_we_check[270] = mio_pad_attr_10_gated_we; + reg_we_check[271] = mio_pad_attr_11_gated_we; + reg_we_check[272] = mio_pad_attr_12_gated_we; + reg_we_check[273] = mio_pad_attr_13_gated_we; + reg_we_check[274] = mio_pad_attr_14_gated_we; + reg_we_check[275] = mio_pad_attr_15_gated_we; + reg_we_check[276] = mio_pad_attr_16_gated_we; + reg_we_check[277] = mio_pad_attr_17_gated_we; + reg_we_check[278] = mio_pad_attr_18_gated_we; + reg_we_check[279] = mio_pad_attr_19_gated_we; + reg_we_check[280] = mio_pad_attr_20_gated_we; + reg_we_check[281] = mio_pad_attr_21_gated_we; + reg_we_check[282] = mio_pad_attr_22_gated_we; + reg_we_check[283] = mio_pad_attr_23_gated_we; + reg_we_check[284] = mio_pad_attr_24_gated_we; + reg_we_check[285] = mio_pad_attr_25_gated_we; + reg_we_check[286] = mio_pad_attr_26_gated_we; + reg_we_check[287] = mio_pad_attr_27_gated_we; + reg_we_check[288] = mio_pad_attr_28_gated_we; + reg_we_check[289] = mio_pad_attr_29_gated_we; + reg_we_check[290] = mio_pad_attr_30_gated_we; + reg_we_check[291] = mio_pad_attr_31_gated_we; + reg_we_check[292] = mio_pad_attr_32_gated_we; + reg_we_check[293] = mio_pad_attr_33_gated_we; + reg_we_check[294] = mio_pad_attr_34_gated_we; + reg_we_check[295] = mio_pad_attr_35_gated_we; + reg_we_check[296] = mio_pad_attr_36_gated_we; + reg_we_check[297] = mio_pad_attr_37_gated_we; + reg_we_check[298] = mio_pad_attr_38_gated_we; + reg_we_check[299] = mio_pad_attr_39_gated_we; + reg_we_check[300] = mio_pad_attr_40_gated_we; + reg_we_check[301] = mio_pad_attr_41_gated_we; + reg_we_check[302] = mio_pad_attr_42_gated_we; + reg_we_check[303] = mio_pad_attr_43_gated_we; + reg_we_check[304] = mio_pad_attr_44_gated_we; + reg_we_check[305] = mio_pad_attr_45_gated_we; + reg_we_check[306] = mio_pad_attr_46_gated_we; + reg_we_check[307] = dio_pad_attr_regwen_0_we; + reg_we_check[308] = dio_pad_attr_regwen_1_we; + reg_we_check[309] = dio_pad_attr_regwen_2_we; + reg_we_check[310] = dio_pad_attr_regwen_3_we; + reg_we_check[311] = dio_pad_attr_regwen_4_we; + reg_we_check[312] = dio_pad_attr_regwen_5_we; + reg_we_check[313] = dio_pad_attr_regwen_6_we; + reg_we_check[314] = dio_pad_attr_regwen_7_we; + reg_we_check[315] = dio_pad_attr_regwen_8_we; + reg_we_check[316] = dio_pad_attr_regwen_9_we; + reg_we_check[317] = dio_pad_attr_regwen_10_we; + reg_we_check[318] = dio_pad_attr_regwen_11_we; + reg_we_check[319] = dio_pad_attr_regwen_12_we; + reg_we_check[320] = dio_pad_attr_regwen_13_we; + reg_we_check[321] = dio_pad_attr_regwen_14_we; + reg_we_check[322] = dio_pad_attr_regwen_15_we; + reg_we_check[323] = dio_pad_attr_0_gated_we; + reg_we_check[324] = dio_pad_attr_1_gated_we; + reg_we_check[325] = dio_pad_attr_2_gated_we; + reg_we_check[326] = dio_pad_attr_3_gated_we; + reg_we_check[327] = dio_pad_attr_4_gated_we; + reg_we_check[328] = dio_pad_attr_5_gated_we; + reg_we_check[329] = dio_pad_attr_6_gated_we; + reg_we_check[330] = dio_pad_attr_7_gated_we; + reg_we_check[331] = dio_pad_attr_8_gated_we; + reg_we_check[332] = dio_pad_attr_9_gated_we; + reg_we_check[333] = dio_pad_attr_10_gated_we; + reg_we_check[334] = dio_pad_attr_11_gated_we; + reg_we_check[335] = dio_pad_attr_12_gated_we; + reg_we_check[336] = dio_pad_attr_13_gated_we; + reg_we_check[337] = dio_pad_attr_14_gated_we; + reg_we_check[338] = dio_pad_attr_15_gated_we; + reg_we_check[339] = mio_pad_sleep_status_0_we; + reg_we_check[340] = mio_pad_sleep_status_1_we; + reg_we_check[341] = mio_pad_sleep_regwen_0_we; + reg_we_check[342] = mio_pad_sleep_regwen_1_we; + reg_we_check[343] = mio_pad_sleep_regwen_2_we; + reg_we_check[344] = mio_pad_sleep_regwen_3_we; + reg_we_check[345] = mio_pad_sleep_regwen_4_we; + reg_we_check[346] = mio_pad_sleep_regwen_5_we; + reg_we_check[347] = mio_pad_sleep_regwen_6_we; + reg_we_check[348] = mio_pad_sleep_regwen_7_we; + reg_we_check[349] = mio_pad_sleep_regwen_8_we; + reg_we_check[350] = mio_pad_sleep_regwen_9_we; + reg_we_check[351] = mio_pad_sleep_regwen_10_we; + reg_we_check[352] = mio_pad_sleep_regwen_11_we; + reg_we_check[353] = mio_pad_sleep_regwen_12_we; + reg_we_check[354] = mio_pad_sleep_regwen_13_we; + reg_we_check[355] = mio_pad_sleep_regwen_14_we; + reg_we_check[356] = mio_pad_sleep_regwen_15_we; + reg_we_check[357] = mio_pad_sleep_regwen_16_we; + reg_we_check[358] = mio_pad_sleep_regwen_17_we; + reg_we_check[359] = mio_pad_sleep_regwen_18_we; + reg_we_check[360] = mio_pad_sleep_regwen_19_we; + reg_we_check[361] = mio_pad_sleep_regwen_20_we; + reg_we_check[362] = mio_pad_sleep_regwen_21_we; + reg_we_check[363] = mio_pad_sleep_regwen_22_we; + reg_we_check[364] = mio_pad_sleep_regwen_23_we; + reg_we_check[365] = mio_pad_sleep_regwen_24_we; + reg_we_check[366] = mio_pad_sleep_regwen_25_we; + reg_we_check[367] = mio_pad_sleep_regwen_26_we; + reg_we_check[368] = mio_pad_sleep_regwen_27_we; + reg_we_check[369] = mio_pad_sleep_regwen_28_we; + reg_we_check[370] = mio_pad_sleep_regwen_29_we; + reg_we_check[371] = mio_pad_sleep_regwen_30_we; + reg_we_check[372] = mio_pad_sleep_regwen_31_we; + reg_we_check[373] = mio_pad_sleep_regwen_32_we; + reg_we_check[374] = mio_pad_sleep_regwen_33_we; + reg_we_check[375] = mio_pad_sleep_regwen_34_we; + reg_we_check[376] = mio_pad_sleep_regwen_35_we; + reg_we_check[377] = mio_pad_sleep_regwen_36_we; + reg_we_check[378] = mio_pad_sleep_regwen_37_we; + reg_we_check[379] = mio_pad_sleep_regwen_38_we; + reg_we_check[380] = mio_pad_sleep_regwen_39_we; + reg_we_check[381] = mio_pad_sleep_regwen_40_we; + reg_we_check[382] = mio_pad_sleep_regwen_41_we; + reg_we_check[383] = mio_pad_sleep_regwen_42_we; + reg_we_check[384] = mio_pad_sleep_regwen_43_we; + reg_we_check[385] = mio_pad_sleep_regwen_44_we; + reg_we_check[386] = mio_pad_sleep_regwen_45_we; + reg_we_check[387] = mio_pad_sleep_regwen_46_we; + reg_we_check[388] = mio_pad_sleep_en_0_gated_we; + reg_we_check[389] = mio_pad_sleep_en_1_gated_we; + reg_we_check[390] = mio_pad_sleep_en_2_gated_we; + reg_we_check[391] = mio_pad_sleep_en_3_gated_we; + reg_we_check[392] = mio_pad_sleep_en_4_gated_we; + reg_we_check[393] = mio_pad_sleep_en_5_gated_we; + reg_we_check[394] = mio_pad_sleep_en_6_gated_we; + reg_we_check[395] = mio_pad_sleep_en_7_gated_we; + reg_we_check[396] = mio_pad_sleep_en_8_gated_we; + reg_we_check[397] = mio_pad_sleep_en_9_gated_we; + reg_we_check[398] = mio_pad_sleep_en_10_gated_we; + reg_we_check[399] = mio_pad_sleep_en_11_gated_we; + reg_we_check[400] = mio_pad_sleep_en_12_gated_we; + reg_we_check[401] = mio_pad_sleep_en_13_gated_we; + reg_we_check[402] = mio_pad_sleep_en_14_gated_we; + reg_we_check[403] = mio_pad_sleep_en_15_gated_we; + reg_we_check[404] = mio_pad_sleep_en_16_gated_we; + reg_we_check[405] = mio_pad_sleep_en_17_gated_we; + reg_we_check[406] = mio_pad_sleep_en_18_gated_we; + reg_we_check[407] = mio_pad_sleep_en_19_gated_we; + reg_we_check[408] = mio_pad_sleep_en_20_gated_we; + reg_we_check[409] = mio_pad_sleep_en_21_gated_we; + reg_we_check[410] = mio_pad_sleep_en_22_gated_we; + reg_we_check[411] = mio_pad_sleep_en_23_gated_we; + reg_we_check[412] = mio_pad_sleep_en_24_gated_we; + reg_we_check[413] = mio_pad_sleep_en_25_gated_we; + reg_we_check[414] = mio_pad_sleep_en_26_gated_we; + reg_we_check[415] = mio_pad_sleep_en_27_gated_we; + reg_we_check[416] = mio_pad_sleep_en_28_gated_we; + reg_we_check[417] = mio_pad_sleep_en_29_gated_we; + reg_we_check[418] = mio_pad_sleep_en_30_gated_we; + reg_we_check[419] = mio_pad_sleep_en_31_gated_we; + reg_we_check[420] = mio_pad_sleep_en_32_gated_we; + reg_we_check[421] = mio_pad_sleep_en_33_gated_we; + reg_we_check[422] = mio_pad_sleep_en_34_gated_we; + reg_we_check[423] = mio_pad_sleep_en_35_gated_we; + reg_we_check[424] = mio_pad_sleep_en_36_gated_we; + reg_we_check[425] = mio_pad_sleep_en_37_gated_we; + reg_we_check[426] = mio_pad_sleep_en_38_gated_we; + reg_we_check[427] = mio_pad_sleep_en_39_gated_we; + reg_we_check[428] = mio_pad_sleep_en_40_gated_we; + reg_we_check[429] = mio_pad_sleep_en_41_gated_we; + reg_we_check[430] = mio_pad_sleep_en_42_gated_we; + reg_we_check[431] = mio_pad_sleep_en_43_gated_we; + reg_we_check[432] = mio_pad_sleep_en_44_gated_we; + reg_we_check[433] = mio_pad_sleep_en_45_gated_we; + reg_we_check[434] = mio_pad_sleep_en_46_gated_we; + reg_we_check[435] = mio_pad_sleep_mode_0_gated_we; + reg_we_check[436] = mio_pad_sleep_mode_1_gated_we; + reg_we_check[437] = mio_pad_sleep_mode_2_gated_we; + reg_we_check[438] = mio_pad_sleep_mode_3_gated_we; + reg_we_check[439] = mio_pad_sleep_mode_4_gated_we; + reg_we_check[440] = mio_pad_sleep_mode_5_gated_we; + reg_we_check[441] = mio_pad_sleep_mode_6_gated_we; + reg_we_check[442] = mio_pad_sleep_mode_7_gated_we; + reg_we_check[443] = mio_pad_sleep_mode_8_gated_we; + reg_we_check[444] = mio_pad_sleep_mode_9_gated_we; + reg_we_check[445] = mio_pad_sleep_mode_10_gated_we; + reg_we_check[446] = mio_pad_sleep_mode_11_gated_we; + reg_we_check[447] = mio_pad_sleep_mode_12_gated_we; + reg_we_check[448] = mio_pad_sleep_mode_13_gated_we; + reg_we_check[449] = mio_pad_sleep_mode_14_gated_we; + reg_we_check[450] = mio_pad_sleep_mode_15_gated_we; + reg_we_check[451] = mio_pad_sleep_mode_16_gated_we; + reg_we_check[452] = mio_pad_sleep_mode_17_gated_we; + reg_we_check[453] = mio_pad_sleep_mode_18_gated_we; + reg_we_check[454] = mio_pad_sleep_mode_19_gated_we; + reg_we_check[455] = mio_pad_sleep_mode_20_gated_we; + reg_we_check[456] = mio_pad_sleep_mode_21_gated_we; + reg_we_check[457] = mio_pad_sleep_mode_22_gated_we; + reg_we_check[458] = mio_pad_sleep_mode_23_gated_we; + reg_we_check[459] = mio_pad_sleep_mode_24_gated_we; + reg_we_check[460] = mio_pad_sleep_mode_25_gated_we; + reg_we_check[461] = mio_pad_sleep_mode_26_gated_we; + reg_we_check[462] = mio_pad_sleep_mode_27_gated_we; + reg_we_check[463] = mio_pad_sleep_mode_28_gated_we; + reg_we_check[464] = mio_pad_sleep_mode_29_gated_we; + reg_we_check[465] = mio_pad_sleep_mode_30_gated_we; + reg_we_check[466] = mio_pad_sleep_mode_31_gated_we; + reg_we_check[467] = mio_pad_sleep_mode_32_gated_we; + reg_we_check[468] = mio_pad_sleep_mode_33_gated_we; + reg_we_check[469] = mio_pad_sleep_mode_34_gated_we; + reg_we_check[470] = mio_pad_sleep_mode_35_gated_we; + reg_we_check[471] = mio_pad_sleep_mode_36_gated_we; + reg_we_check[472] = mio_pad_sleep_mode_37_gated_we; + reg_we_check[473] = mio_pad_sleep_mode_38_gated_we; + reg_we_check[474] = mio_pad_sleep_mode_39_gated_we; + reg_we_check[475] = mio_pad_sleep_mode_40_gated_we; + reg_we_check[476] = mio_pad_sleep_mode_41_gated_we; + reg_we_check[477] = mio_pad_sleep_mode_42_gated_we; + reg_we_check[478] = mio_pad_sleep_mode_43_gated_we; + reg_we_check[479] = mio_pad_sleep_mode_44_gated_we; + reg_we_check[480] = mio_pad_sleep_mode_45_gated_we; + reg_we_check[481] = mio_pad_sleep_mode_46_gated_we; + reg_we_check[482] = dio_pad_sleep_status_we; + reg_we_check[483] = dio_pad_sleep_regwen_0_we; + reg_we_check[484] = dio_pad_sleep_regwen_1_we; + reg_we_check[485] = dio_pad_sleep_regwen_2_we; + reg_we_check[486] = dio_pad_sleep_regwen_3_we; + reg_we_check[487] = dio_pad_sleep_regwen_4_we; + reg_we_check[488] = dio_pad_sleep_regwen_5_we; + reg_we_check[489] = dio_pad_sleep_regwen_6_we; + reg_we_check[490] = dio_pad_sleep_regwen_7_we; + reg_we_check[491] = dio_pad_sleep_regwen_8_we; + reg_we_check[492] = dio_pad_sleep_regwen_9_we; + reg_we_check[493] = dio_pad_sleep_regwen_10_we; + reg_we_check[494] = dio_pad_sleep_regwen_11_we; + reg_we_check[495] = dio_pad_sleep_regwen_12_we; + reg_we_check[496] = dio_pad_sleep_regwen_13_we; + reg_we_check[497] = dio_pad_sleep_regwen_14_we; + reg_we_check[498] = dio_pad_sleep_regwen_15_we; + reg_we_check[499] = dio_pad_sleep_en_0_gated_we; + reg_we_check[500] = dio_pad_sleep_en_1_gated_we; + reg_we_check[501] = dio_pad_sleep_en_2_gated_we; + reg_we_check[502] = dio_pad_sleep_en_3_gated_we; + reg_we_check[503] = dio_pad_sleep_en_4_gated_we; + reg_we_check[504] = dio_pad_sleep_en_5_gated_we; + reg_we_check[505] = dio_pad_sleep_en_6_gated_we; + reg_we_check[506] = dio_pad_sleep_en_7_gated_we; + reg_we_check[507] = dio_pad_sleep_en_8_gated_we; + reg_we_check[508] = dio_pad_sleep_en_9_gated_we; + reg_we_check[509] = dio_pad_sleep_en_10_gated_we; + reg_we_check[510] = dio_pad_sleep_en_11_gated_we; + reg_we_check[511] = dio_pad_sleep_en_12_gated_we; + reg_we_check[512] = dio_pad_sleep_en_13_gated_we; + reg_we_check[513] = dio_pad_sleep_en_14_gated_we; + reg_we_check[514] = dio_pad_sleep_en_15_gated_we; + reg_we_check[515] = dio_pad_sleep_mode_0_gated_we; + reg_we_check[516] = dio_pad_sleep_mode_1_gated_we; + reg_we_check[517] = dio_pad_sleep_mode_2_gated_we; + reg_we_check[518] = dio_pad_sleep_mode_3_gated_we; + reg_we_check[519] = dio_pad_sleep_mode_4_gated_we; + reg_we_check[520] = dio_pad_sleep_mode_5_gated_we; + reg_we_check[521] = dio_pad_sleep_mode_6_gated_we; + reg_we_check[522] = dio_pad_sleep_mode_7_gated_we; + reg_we_check[523] = dio_pad_sleep_mode_8_gated_we; + reg_we_check[524] = dio_pad_sleep_mode_9_gated_we; + reg_we_check[525] = dio_pad_sleep_mode_10_gated_we; + reg_we_check[526] = dio_pad_sleep_mode_11_gated_we; + reg_we_check[527] = dio_pad_sleep_mode_12_gated_we; + reg_we_check[528] = dio_pad_sleep_mode_13_gated_we; + reg_we_check[529] = dio_pad_sleep_mode_14_gated_we; + reg_we_check[530] = dio_pad_sleep_mode_15_gated_we; + reg_we_check[531] = wkup_detector_regwen_0_we; + reg_we_check[532] = wkup_detector_regwen_1_we; + reg_we_check[533] = wkup_detector_regwen_2_we; + reg_we_check[534] = wkup_detector_regwen_3_we; + reg_we_check[535] = wkup_detector_regwen_4_we; + reg_we_check[536] = wkup_detector_regwen_5_we; + reg_we_check[537] = wkup_detector_regwen_6_we; + reg_we_check[538] = wkup_detector_regwen_7_we; + reg_we_check[539] = wkup_detector_en_0_we; + reg_we_check[540] = wkup_detector_en_1_we; + reg_we_check[541] = wkup_detector_en_2_we; + reg_we_check[542] = wkup_detector_en_3_we; + reg_we_check[543] = wkup_detector_en_4_we; + reg_we_check[544] = wkup_detector_en_5_we; + reg_we_check[545] = wkup_detector_en_6_we; + reg_we_check[546] = wkup_detector_en_7_we; + reg_we_check[547] = wkup_detector_0_we; + reg_we_check[548] = wkup_detector_1_we; + reg_we_check[549] = wkup_detector_2_we; + reg_we_check[550] = wkup_detector_3_we; + reg_we_check[551] = wkup_detector_4_we; + reg_we_check[552] = wkup_detector_5_we; + reg_we_check[553] = wkup_detector_6_we; + reg_we_check[554] = wkup_detector_7_we; + reg_we_check[555] = wkup_detector_cnt_th_0_we; + reg_we_check[556] = wkup_detector_cnt_th_1_we; + reg_we_check[557] = wkup_detector_cnt_th_2_we; + reg_we_check[558] = wkup_detector_cnt_th_3_we; + reg_we_check[559] = wkup_detector_cnt_th_4_we; + reg_we_check[560] = wkup_detector_cnt_th_5_we; + reg_we_check[561] = wkup_detector_cnt_th_6_we; + reg_we_check[562] = wkup_detector_cnt_th_7_we; + reg_we_check[563] = wkup_detector_padsel_0_gated_we; + reg_we_check[564] = wkup_detector_padsel_1_gated_we; + reg_we_check[565] = wkup_detector_padsel_2_gated_we; + reg_we_check[566] = wkup_detector_padsel_3_gated_we; + reg_we_check[567] = wkup_detector_padsel_4_gated_we; + reg_we_check[568] = wkup_detector_padsel_5_gated_we; + reg_we_check[569] = wkup_detector_padsel_6_gated_we; + reg_we_check[570] = wkup_detector_padsel_7_gated_we; + reg_we_check[571] = wkup_cause_we; end // Read data return @@ -36246,798 +36404,814 @@ module pinmux_reg_top ( end addr_hit[58]: begin - reg_rdata_next[5:0] = mio_periph_insel_0_qs; + reg_rdata_next[0] = mio_periph_insel_regwen_57_qs; end addr_hit[59]: begin - reg_rdata_next[5:0] = mio_periph_insel_1_qs; + reg_rdata_next[0] = mio_periph_insel_regwen_58_qs; end addr_hit[60]: begin - reg_rdata_next[5:0] = mio_periph_insel_2_qs; + reg_rdata_next[5:0] = mio_periph_insel_0_qs; end addr_hit[61]: begin - reg_rdata_next[5:0] = mio_periph_insel_3_qs; + reg_rdata_next[5:0] = mio_periph_insel_1_qs; end addr_hit[62]: begin - reg_rdata_next[5:0] = mio_periph_insel_4_qs; + reg_rdata_next[5:0] = mio_periph_insel_2_qs; end addr_hit[63]: begin - reg_rdata_next[5:0] = mio_periph_insel_5_qs; + reg_rdata_next[5:0] = mio_periph_insel_3_qs; end addr_hit[64]: begin - reg_rdata_next[5:0] = mio_periph_insel_6_qs; + reg_rdata_next[5:0] = mio_periph_insel_4_qs; end addr_hit[65]: begin - reg_rdata_next[5:0] = mio_periph_insel_7_qs; + reg_rdata_next[5:0] = mio_periph_insel_5_qs; end addr_hit[66]: begin - reg_rdata_next[5:0] = mio_periph_insel_8_qs; + reg_rdata_next[5:0] = mio_periph_insel_6_qs; end addr_hit[67]: begin - reg_rdata_next[5:0] = mio_periph_insel_9_qs; + reg_rdata_next[5:0] = mio_periph_insel_7_qs; end addr_hit[68]: begin - reg_rdata_next[5:0] = mio_periph_insel_10_qs; + reg_rdata_next[5:0] = mio_periph_insel_8_qs; end addr_hit[69]: begin - reg_rdata_next[5:0] = mio_periph_insel_11_qs; + reg_rdata_next[5:0] = mio_periph_insel_9_qs; end addr_hit[70]: begin - reg_rdata_next[5:0] = mio_periph_insel_12_qs; + reg_rdata_next[5:0] = mio_periph_insel_10_qs; end addr_hit[71]: begin - reg_rdata_next[5:0] = mio_periph_insel_13_qs; + reg_rdata_next[5:0] = mio_periph_insel_11_qs; end addr_hit[72]: begin - reg_rdata_next[5:0] = mio_periph_insel_14_qs; + reg_rdata_next[5:0] = mio_periph_insel_12_qs; end addr_hit[73]: begin - reg_rdata_next[5:0] = mio_periph_insel_15_qs; + reg_rdata_next[5:0] = mio_periph_insel_13_qs; end addr_hit[74]: begin - reg_rdata_next[5:0] = mio_periph_insel_16_qs; + reg_rdata_next[5:0] = mio_periph_insel_14_qs; end addr_hit[75]: begin - reg_rdata_next[5:0] = mio_periph_insel_17_qs; + reg_rdata_next[5:0] = mio_periph_insel_15_qs; end addr_hit[76]: begin - reg_rdata_next[5:0] = mio_periph_insel_18_qs; + reg_rdata_next[5:0] = mio_periph_insel_16_qs; end addr_hit[77]: begin - reg_rdata_next[5:0] = mio_periph_insel_19_qs; + reg_rdata_next[5:0] = mio_periph_insel_17_qs; end addr_hit[78]: begin - reg_rdata_next[5:0] = mio_periph_insel_20_qs; + reg_rdata_next[5:0] = mio_periph_insel_18_qs; end addr_hit[79]: begin - reg_rdata_next[5:0] = mio_periph_insel_21_qs; + reg_rdata_next[5:0] = mio_periph_insel_19_qs; end addr_hit[80]: begin - reg_rdata_next[5:0] = mio_periph_insel_22_qs; + reg_rdata_next[5:0] = mio_periph_insel_20_qs; end addr_hit[81]: begin - reg_rdata_next[5:0] = mio_periph_insel_23_qs; + reg_rdata_next[5:0] = mio_periph_insel_21_qs; end addr_hit[82]: begin - reg_rdata_next[5:0] = mio_periph_insel_24_qs; + reg_rdata_next[5:0] = mio_periph_insel_22_qs; end addr_hit[83]: begin - reg_rdata_next[5:0] = mio_periph_insel_25_qs; + reg_rdata_next[5:0] = mio_periph_insel_23_qs; end addr_hit[84]: begin - reg_rdata_next[5:0] = mio_periph_insel_26_qs; + reg_rdata_next[5:0] = mio_periph_insel_24_qs; end addr_hit[85]: begin - reg_rdata_next[5:0] = mio_periph_insel_27_qs; + reg_rdata_next[5:0] = mio_periph_insel_25_qs; end addr_hit[86]: begin - reg_rdata_next[5:0] = mio_periph_insel_28_qs; + reg_rdata_next[5:0] = mio_periph_insel_26_qs; end addr_hit[87]: begin - reg_rdata_next[5:0] = mio_periph_insel_29_qs; + reg_rdata_next[5:0] = mio_periph_insel_27_qs; end addr_hit[88]: begin - reg_rdata_next[5:0] = mio_periph_insel_30_qs; + reg_rdata_next[5:0] = mio_periph_insel_28_qs; end addr_hit[89]: begin - reg_rdata_next[5:0] = mio_periph_insel_31_qs; + reg_rdata_next[5:0] = mio_periph_insel_29_qs; end addr_hit[90]: begin - reg_rdata_next[5:0] = mio_periph_insel_32_qs; + reg_rdata_next[5:0] = mio_periph_insel_30_qs; end addr_hit[91]: begin - reg_rdata_next[5:0] = mio_periph_insel_33_qs; + reg_rdata_next[5:0] = mio_periph_insel_31_qs; end addr_hit[92]: begin - reg_rdata_next[5:0] = mio_periph_insel_34_qs; + reg_rdata_next[5:0] = mio_periph_insel_32_qs; end addr_hit[93]: begin - reg_rdata_next[5:0] = mio_periph_insel_35_qs; + reg_rdata_next[5:0] = mio_periph_insel_33_qs; end addr_hit[94]: begin - reg_rdata_next[5:0] = mio_periph_insel_36_qs; + reg_rdata_next[5:0] = mio_periph_insel_34_qs; end addr_hit[95]: begin - reg_rdata_next[5:0] = mio_periph_insel_37_qs; + reg_rdata_next[5:0] = mio_periph_insel_35_qs; end addr_hit[96]: begin - reg_rdata_next[5:0] = mio_periph_insel_38_qs; + reg_rdata_next[5:0] = mio_periph_insel_36_qs; end addr_hit[97]: begin - reg_rdata_next[5:0] = mio_periph_insel_39_qs; + reg_rdata_next[5:0] = mio_periph_insel_37_qs; end addr_hit[98]: begin - reg_rdata_next[5:0] = mio_periph_insel_40_qs; + reg_rdata_next[5:0] = mio_periph_insel_38_qs; end addr_hit[99]: begin - reg_rdata_next[5:0] = mio_periph_insel_41_qs; + reg_rdata_next[5:0] = mio_periph_insel_39_qs; end addr_hit[100]: begin - reg_rdata_next[5:0] = mio_periph_insel_42_qs; + reg_rdata_next[5:0] = mio_periph_insel_40_qs; end addr_hit[101]: begin - reg_rdata_next[5:0] = mio_periph_insel_43_qs; + reg_rdata_next[5:0] = mio_periph_insel_41_qs; end addr_hit[102]: begin - reg_rdata_next[5:0] = mio_periph_insel_44_qs; + reg_rdata_next[5:0] = mio_periph_insel_42_qs; end addr_hit[103]: begin - reg_rdata_next[5:0] = mio_periph_insel_45_qs; + reg_rdata_next[5:0] = mio_periph_insel_43_qs; end addr_hit[104]: begin - reg_rdata_next[5:0] = mio_periph_insel_46_qs; + reg_rdata_next[5:0] = mio_periph_insel_44_qs; end addr_hit[105]: begin - reg_rdata_next[5:0] = mio_periph_insel_47_qs; + reg_rdata_next[5:0] = mio_periph_insel_45_qs; end addr_hit[106]: begin - reg_rdata_next[5:0] = mio_periph_insel_48_qs; + reg_rdata_next[5:0] = mio_periph_insel_46_qs; end addr_hit[107]: begin - reg_rdata_next[5:0] = mio_periph_insel_49_qs; + reg_rdata_next[5:0] = mio_periph_insel_47_qs; end addr_hit[108]: begin - reg_rdata_next[5:0] = mio_periph_insel_50_qs; + reg_rdata_next[5:0] = mio_periph_insel_48_qs; end addr_hit[109]: begin - reg_rdata_next[5:0] = mio_periph_insel_51_qs; + reg_rdata_next[5:0] = mio_periph_insel_49_qs; end addr_hit[110]: begin - reg_rdata_next[5:0] = mio_periph_insel_52_qs; + reg_rdata_next[5:0] = mio_periph_insel_50_qs; end addr_hit[111]: begin - reg_rdata_next[5:0] = mio_periph_insel_53_qs; + reg_rdata_next[5:0] = mio_periph_insel_51_qs; end addr_hit[112]: begin - reg_rdata_next[5:0] = mio_periph_insel_54_qs; + reg_rdata_next[5:0] = mio_periph_insel_52_qs; end addr_hit[113]: begin - reg_rdata_next[5:0] = mio_periph_insel_55_qs; + reg_rdata_next[5:0] = mio_periph_insel_53_qs; end addr_hit[114]: begin - reg_rdata_next[5:0] = mio_periph_insel_56_qs; + reg_rdata_next[5:0] = mio_periph_insel_54_qs; end addr_hit[115]: begin - reg_rdata_next[0] = mio_outsel_regwen_0_qs; + reg_rdata_next[5:0] = mio_periph_insel_55_qs; end addr_hit[116]: begin - reg_rdata_next[0] = mio_outsel_regwen_1_qs; + reg_rdata_next[5:0] = mio_periph_insel_56_qs; end addr_hit[117]: begin - reg_rdata_next[0] = mio_outsel_regwen_2_qs; + reg_rdata_next[5:0] = mio_periph_insel_57_qs; end addr_hit[118]: begin - reg_rdata_next[0] = mio_outsel_regwen_3_qs; + reg_rdata_next[5:0] = mio_periph_insel_58_qs; end addr_hit[119]: begin - reg_rdata_next[0] = mio_outsel_regwen_4_qs; + reg_rdata_next[0] = mio_outsel_regwen_0_qs; end addr_hit[120]: begin - reg_rdata_next[0] = mio_outsel_regwen_5_qs; + reg_rdata_next[0] = mio_outsel_regwen_1_qs; end addr_hit[121]: begin - reg_rdata_next[0] = mio_outsel_regwen_6_qs; + reg_rdata_next[0] = mio_outsel_regwen_2_qs; end addr_hit[122]: begin - reg_rdata_next[0] = mio_outsel_regwen_7_qs; + reg_rdata_next[0] = mio_outsel_regwen_3_qs; end addr_hit[123]: begin - reg_rdata_next[0] = mio_outsel_regwen_8_qs; + reg_rdata_next[0] = mio_outsel_regwen_4_qs; end addr_hit[124]: begin - reg_rdata_next[0] = mio_outsel_regwen_9_qs; + reg_rdata_next[0] = mio_outsel_regwen_5_qs; end addr_hit[125]: begin - reg_rdata_next[0] = mio_outsel_regwen_10_qs; + reg_rdata_next[0] = mio_outsel_regwen_6_qs; end addr_hit[126]: begin - reg_rdata_next[0] = mio_outsel_regwen_11_qs; + reg_rdata_next[0] = mio_outsel_regwen_7_qs; end addr_hit[127]: begin - reg_rdata_next[0] = mio_outsel_regwen_12_qs; + reg_rdata_next[0] = mio_outsel_regwen_8_qs; end addr_hit[128]: begin - reg_rdata_next[0] = mio_outsel_regwen_13_qs; + reg_rdata_next[0] = mio_outsel_regwen_9_qs; end addr_hit[129]: begin - reg_rdata_next[0] = mio_outsel_regwen_14_qs; + reg_rdata_next[0] = mio_outsel_regwen_10_qs; end addr_hit[130]: begin - reg_rdata_next[0] = mio_outsel_regwen_15_qs; + reg_rdata_next[0] = mio_outsel_regwen_11_qs; end addr_hit[131]: begin - reg_rdata_next[0] = mio_outsel_regwen_16_qs; + reg_rdata_next[0] = mio_outsel_regwen_12_qs; end addr_hit[132]: begin - reg_rdata_next[0] = mio_outsel_regwen_17_qs; + reg_rdata_next[0] = mio_outsel_regwen_13_qs; end addr_hit[133]: begin - reg_rdata_next[0] = mio_outsel_regwen_18_qs; + reg_rdata_next[0] = mio_outsel_regwen_14_qs; end addr_hit[134]: begin - reg_rdata_next[0] = mio_outsel_regwen_19_qs; + reg_rdata_next[0] = mio_outsel_regwen_15_qs; end addr_hit[135]: begin - reg_rdata_next[0] = mio_outsel_regwen_20_qs; + reg_rdata_next[0] = mio_outsel_regwen_16_qs; end addr_hit[136]: begin - reg_rdata_next[0] = mio_outsel_regwen_21_qs; + reg_rdata_next[0] = mio_outsel_regwen_17_qs; end addr_hit[137]: begin - reg_rdata_next[0] = mio_outsel_regwen_22_qs; + reg_rdata_next[0] = mio_outsel_regwen_18_qs; end addr_hit[138]: begin - reg_rdata_next[0] = mio_outsel_regwen_23_qs; + reg_rdata_next[0] = mio_outsel_regwen_19_qs; end addr_hit[139]: begin - reg_rdata_next[0] = mio_outsel_regwen_24_qs; + reg_rdata_next[0] = mio_outsel_regwen_20_qs; end addr_hit[140]: begin - reg_rdata_next[0] = mio_outsel_regwen_25_qs; + reg_rdata_next[0] = mio_outsel_regwen_21_qs; end addr_hit[141]: begin - reg_rdata_next[0] = mio_outsel_regwen_26_qs; + reg_rdata_next[0] = mio_outsel_regwen_22_qs; end addr_hit[142]: begin - reg_rdata_next[0] = mio_outsel_regwen_27_qs; + reg_rdata_next[0] = mio_outsel_regwen_23_qs; end addr_hit[143]: begin - reg_rdata_next[0] = mio_outsel_regwen_28_qs; + reg_rdata_next[0] = mio_outsel_regwen_24_qs; end addr_hit[144]: begin - reg_rdata_next[0] = mio_outsel_regwen_29_qs; + reg_rdata_next[0] = mio_outsel_regwen_25_qs; end addr_hit[145]: begin - reg_rdata_next[0] = mio_outsel_regwen_30_qs; + reg_rdata_next[0] = mio_outsel_regwen_26_qs; end addr_hit[146]: begin - reg_rdata_next[0] = mio_outsel_regwen_31_qs; + reg_rdata_next[0] = mio_outsel_regwen_27_qs; end addr_hit[147]: begin - reg_rdata_next[0] = mio_outsel_regwen_32_qs; + reg_rdata_next[0] = mio_outsel_regwen_28_qs; end addr_hit[148]: begin - reg_rdata_next[0] = mio_outsel_regwen_33_qs; + reg_rdata_next[0] = mio_outsel_regwen_29_qs; end addr_hit[149]: begin - reg_rdata_next[0] = mio_outsel_regwen_34_qs; + reg_rdata_next[0] = mio_outsel_regwen_30_qs; end addr_hit[150]: begin - reg_rdata_next[0] = mio_outsel_regwen_35_qs; + reg_rdata_next[0] = mio_outsel_regwen_31_qs; end addr_hit[151]: begin - reg_rdata_next[0] = mio_outsel_regwen_36_qs; + reg_rdata_next[0] = mio_outsel_regwen_32_qs; end addr_hit[152]: begin - reg_rdata_next[0] = mio_outsel_regwen_37_qs; + reg_rdata_next[0] = mio_outsel_regwen_33_qs; end addr_hit[153]: begin - reg_rdata_next[0] = mio_outsel_regwen_38_qs; + reg_rdata_next[0] = mio_outsel_regwen_34_qs; end addr_hit[154]: begin - reg_rdata_next[0] = mio_outsel_regwen_39_qs; + reg_rdata_next[0] = mio_outsel_regwen_35_qs; end addr_hit[155]: begin - reg_rdata_next[0] = mio_outsel_regwen_40_qs; + reg_rdata_next[0] = mio_outsel_regwen_36_qs; end addr_hit[156]: begin - reg_rdata_next[0] = mio_outsel_regwen_41_qs; + reg_rdata_next[0] = mio_outsel_regwen_37_qs; end addr_hit[157]: begin - reg_rdata_next[0] = mio_outsel_regwen_42_qs; + reg_rdata_next[0] = mio_outsel_regwen_38_qs; end addr_hit[158]: begin - reg_rdata_next[0] = mio_outsel_regwen_43_qs; + reg_rdata_next[0] = mio_outsel_regwen_39_qs; end addr_hit[159]: begin - reg_rdata_next[0] = mio_outsel_regwen_44_qs; + reg_rdata_next[0] = mio_outsel_regwen_40_qs; end addr_hit[160]: begin - reg_rdata_next[0] = mio_outsel_regwen_45_qs; + reg_rdata_next[0] = mio_outsel_regwen_41_qs; end addr_hit[161]: begin - reg_rdata_next[0] = mio_outsel_regwen_46_qs; + reg_rdata_next[0] = mio_outsel_regwen_42_qs; end addr_hit[162]: begin - reg_rdata_next[6:0] = mio_outsel_0_qs; + reg_rdata_next[0] = mio_outsel_regwen_43_qs; end addr_hit[163]: begin - reg_rdata_next[6:0] = mio_outsel_1_qs; + reg_rdata_next[0] = mio_outsel_regwen_44_qs; end addr_hit[164]: begin - reg_rdata_next[6:0] = mio_outsel_2_qs; + reg_rdata_next[0] = mio_outsel_regwen_45_qs; end addr_hit[165]: begin - reg_rdata_next[6:0] = mio_outsel_3_qs; + reg_rdata_next[0] = mio_outsel_regwen_46_qs; end addr_hit[166]: begin - reg_rdata_next[6:0] = mio_outsel_4_qs; + reg_rdata_next[6:0] = mio_outsel_0_qs; end addr_hit[167]: begin - reg_rdata_next[6:0] = mio_outsel_5_qs; + reg_rdata_next[6:0] = mio_outsel_1_qs; end addr_hit[168]: begin - reg_rdata_next[6:0] = mio_outsel_6_qs; + reg_rdata_next[6:0] = mio_outsel_2_qs; end addr_hit[169]: begin - reg_rdata_next[6:0] = mio_outsel_7_qs; + reg_rdata_next[6:0] = mio_outsel_3_qs; end addr_hit[170]: begin - reg_rdata_next[6:0] = mio_outsel_8_qs; + reg_rdata_next[6:0] = mio_outsel_4_qs; end addr_hit[171]: begin - reg_rdata_next[6:0] = mio_outsel_9_qs; + reg_rdata_next[6:0] = mio_outsel_5_qs; end addr_hit[172]: begin - reg_rdata_next[6:0] = mio_outsel_10_qs; + reg_rdata_next[6:0] = mio_outsel_6_qs; end addr_hit[173]: begin - reg_rdata_next[6:0] = mio_outsel_11_qs; + reg_rdata_next[6:0] = mio_outsel_7_qs; end addr_hit[174]: begin - reg_rdata_next[6:0] = mio_outsel_12_qs; + reg_rdata_next[6:0] = mio_outsel_8_qs; end addr_hit[175]: begin - reg_rdata_next[6:0] = mio_outsel_13_qs; + reg_rdata_next[6:0] = mio_outsel_9_qs; end addr_hit[176]: begin - reg_rdata_next[6:0] = mio_outsel_14_qs; + reg_rdata_next[6:0] = mio_outsel_10_qs; end addr_hit[177]: begin - reg_rdata_next[6:0] = mio_outsel_15_qs; + reg_rdata_next[6:0] = mio_outsel_11_qs; end addr_hit[178]: begin - reg_rdata_next[6:0] = mio_outsel_16_qs; + reg_rdata_next[6:0] = mio_outsel_12_qs; end addr_hit[179]: begin - reg_rdata_next[6:0] = mio_outsel_17_qs; + reg_rdata_next[6:0] = mio_outsel_13_qs; end addr_hit[180]: begin - reg_rdata_next[6:0] = mio_outsel_18_qs; + reg_rdata_next[6:0] = mio_outsel_14_qs; end addr_hit[181]: begin - reg_rdata_next[6:0] = mio_outsel_19_qs; + reg_rdata_next[6:0] = mio_outsel_15_qs; end addr_hit[182]: begin - reg_rdata_next[6:0] = mio_outsel_20_qs; + reg_rdata_next[6:0] = mio_outsel_16_qs; end addr_hit[183]: begin - reg_rdata_next[6:0] = mio_outsel_21_qs; + reg_rdata_next[6:0] = mio_outsel_17_qs; end addr_hit[184]: begin - reg_rdata_next[6:0] = mio_outsel_22_qs; + reg_rdata_next[6:0] = mio_outsel_18_qs; end addr_hit[185]: begin - reg_rdata_next[6:0] = mio_outsel_23_qs; + reg_rdata_next[6:0] = mio_outsel_19_qs; end addr_hit[186]: begin - reg_rdata_next[6:0] = mio_outsel_24_qs; + reg_rdata_next[6:0] = mio_outsel_20_qs; end addr_hit[187]: begin - reg_rdata_next[6:0] = mio_outsel_25_qs; + reg_rdata_next[6:0] = mio_outsel_21_qs; end addr_hit[188]: begin - reg_rdata_next[6:0] = mio_outsel_26_qs; + reg_rdata_next[6:0] = mio_outsel_22_qs; end addr_hit[189]: begin - reg_rdata_next[6:0] = mio_outsel_27_qs; + reg_rdata_next[6:0] = mio_outsel_23_qs; end addr_hit[190]: begin - reg_rdata_next[6:0] = mio_outsel_28_qs; + reg_rdata_next[6:0] = mio_outsel_24_qs; end addr_hit[191]: begin - reg_rdata_next[6:0] = mio_outsel_29_qs; + reg_rdata_next[6:0] = mio_outsel_25_qs; end addr_hit[192]: begin - reg_rdata_next[6:0] = mio_outsel_30_qs; + reg_rdata_next[6:0] = mio_outsel_26_qs; end addr_hit[193]: begin - reg_rdata_next[6:0] = mio_outsel_31_qs; + reg_rdata_next[6:0] = mio_outsel_27_qs; end addr_hit[194]: begin - reg_rdata_next[6:0] = mio_outsel_32_qs; + reg_rdata_next[6:0] = mio_outsel_28_qs; end addr_hit[195]: begin - reg_rdata_next[6:0] = mio_outsel_33_qs; + reg_rdata_next[6:0] = mio_outsel_29_qs; end addr_hit[196]: begin - reg_rdata_next[6:0] = mio_outsel_34_qs; + reg_rdata_next[6:0] = mio_outsel_30_qs; end addr_hit[197]: begin - reg_rdata_next[6:0] = mio_outsel_35_qs; + reg_rdata_next[6:0] = mio_outsel_31_qs; end addr_hit[198]: begin - reg_rdata_next[6:0] = mio_outsel_36_qs; + reg_rdata_next[6:0] = mio_outsel_32_qs; end addr_hit[199]: begin - reg_rdata_next[6:0] = mio_outsel_37_qs; + reg_rdata_next[6:0] = mio_outsel_33_qs; end addr_hit[200]: begin - reg_rdata_next[6:0] = mio_outsel_38_qs; + reg_rdata_next[6:0] = mio_outsel_34_qs; end addr_hit[201]: begin - reg_rdata_next[6:0] = mio_outsel_39_qs; + reg_rdata_next[6:0] = mio_outsel_35_qs; end addr_hit[202]: begin - reg_rdata_next[6:0] = mio_outsel_40_qs; + reg_rdata_next[6:0] = mio_outsel_36_qs; end addr_hit[203]: begin - reg_rdata_next[6:0] = mio_outsel_41_qs; + reg_rdata_next[6:0] = mio_outsel_37_qs; end addr_hit[204]: begin - reg_rdata_next[6:0] = mio_outsel_42_qs; + reg_rdata_next[6:0] = mio_outsel_38_qs; end addr_hit[205]: begin - reg_rdata_next[6:0] = mio_outsel_43_qs; + reg_rdata_next[6:0] = mio_outsel_39_qs; end addr_hit[206]: begin - reg_rdata_next[6:0] = mio_outsel_44_qs; + reg_rdata_next[6:0] = mio_outsel_40_qs; end addr_hit[207]: begin - reg_rdata_next[6:0] = mio_outsel_45_qs; + reg_rdata_next[6:0] = mio_outsel_41_qs; end addr_hit[208]: begin - reg_rdata_next[6:0] = mio_outsel_46_qs; + reg_rdata_next[6:0] = mio_outsel_42_qs; end addr_hit[209]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; + reg_rdata_next[6:0] = mio_outsel_43_qs; end addr_hit[210]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; + reg_rdata_next[6:0] = mio_outsel_44_qs; end addr_hit[211]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; + reg_rdata_next[6:0] = mio_outsel_45_qs; end addr_hit[212]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; + reg_rdata_next[6:0] = mio_outsel_46_qs; end addr_hit[213]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; end addr_hit[214]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; end addr_hit[215]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; end addr_hit[216]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; end addr_hit[217]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; end addr_hit[218]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; end addr_hit[219]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; end addr_hit[220]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; end addr_hit[221]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; end addr_hit[222]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; end addr_hit[223]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; end addr_hit[224]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; end addr_hit[225]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; end addr_hit[226]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; end addr_hit[227]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; end addr_hit[228]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; end addr_hit[229]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; end addr_hit[230]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; end addr_hit[231]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; end addr_hit[232]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; end addr_hit[233]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; end addr_hit[234]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; end addr_hit[235]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; end addr_hit[236]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; end addr_hit[237]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; end addr_hit[238]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; end addr_hit[239]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; end addr_hit[240]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; end addr_hit[241]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_32_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; end addr_hit[242]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_33_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; end addr_hit[243]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_34_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; end addr_hit[244]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_35_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; end addr_hit[245]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_36_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_32_qs; end addr_hit[246]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_37_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_33_qs; end addr_hit[247]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_38_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_34_qs; end addr_hit[248]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_39_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_35_qs; end addr_hit[249]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_40_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_36_qs; end addr_hit[250]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_41_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_37_qs; end addr_hit[251]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_42_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_38_qs; end addr_hit[252]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_43_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_39_qs; end addr_hit[253]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_44_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_40_qs; end addr_hit[254]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_45_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_41_qs; end addr_hit[255]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_46_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_42_qs; end addr_hit[256]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_43_qs; + end + + addr_hit[257]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_44_qs; + end + + addr_hit[258]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_45_qs; + end + + addr_hit[259]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_46_qs; + end + + addr_hit[260]: begin reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs; @@ -37049,7 +37223,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs; end - addr_hit[257]: begin + addr_hit[261]: begin reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs; @@ -37061,7 +37235,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs; end - addr_hit[258]: begin + addr_hit[262]: begin reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs; @@ -37073,7 +37247,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs; end - addr_hit[259]: begin + addr_hit[263]: begin reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs; @@ -37085,7 +37259,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs; end - addr_hit[260]: begin + addr_hit[264]: begin reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs; @@ -37097,7 +37271,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs; end - addr_hit[261]: begin + addr_hit[265]: begin reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs; @@ -37109,7 +37283,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs; end - addr_hit[262]: begin + addr_hit[266]: begin reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs; @@ -37121,7 +37295,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs; end - addr_hit[263]: begin + addr_hit[267]: begin reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs; @@ -37133,7 +37307,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs; end - addr_hit[264]: begin + addr_hit[268]: begin reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs; @@ -37145,7 +37319,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs; end - addr_hit[265]: begin + addr_hit[269]: begin reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs; @@ -37157,7 +37331,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs; end - addr_hit[266]: begin + addr_hit[270]: begin reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs; @@ -37169,7 +37343,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs; end - addr_hit[267]: begin + addr_hit[271]: begin reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs; @@ -37181,7 +37355,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs; end - addr_hit[268]: begin + addr_hit[272]: begin reg_rdata_next[0] = mio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = mio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = mio_pad_attr_12_pull_en_12_qs; @@ -37193,7 +37367,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_12_drive_strength_12_qs; end - addr_hit[269]: begin + addr_hit[273]: begin reg_rdata_next[0] = mio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = mio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = mio_pad_attr_13_pull_en_13_qs; @@ -37205,7 +37379,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_13_drive_strength_13_qs; end - addr_hit[270]: begin + addr_hit[274]: begin reg_rdata_next[0] = mio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = mio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = mio_pad_attr_14_pull_en_14_qs; @@ -37217,7 +37391,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_14_drive_strength_14_qs; end - addr_hit[271]: begin + addr_hit[275]: begin reg_rdata_next[0] = mio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = mio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = mio_pad_attr_15_pull_en_15_qs; @@ -37229,7 +37403,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_15_drive_strength_15_qs; end - addr_hit[272]: begin + addr_hit[276]: begin reg_rdata_next[0] = mio_pad_attr_16_invert_16_qs; reg_rdata_next[1] = mio_pad_attr_16_virtual_od_en_16_qs; reg_rdata_next[2] = mio_pad_attr_16_pull_en_16_qs; @@ -37241,7 +37415,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_16_drive_strength_16_qs; end - addr_hit[273]: begin + addr_hit[277]: begin reg_rdata_next[0] = mio_pad_attr_17_invert_17_qs; reg_rdata_next[1] = mio_pad_attr_17_virtual_od_en_17_qs; reg_rdata_next[2] = mio_pad_attr_17_pull_en_17_qs; @@ -37253,7 +37427,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_17_drive_strength_17_qs; end - addr_hit[274]: begin + addr_hit[278]: begin reg_rdata_next[0] = mio_pad_attr_18_invert_18_qs; reg_rdata_next[1] = mio_pad_attr_18_virtual_od_en_18_qs; reg_rdata_next[2] = mio_pad_attr_18_pull_en_18_qs; @@ -37265,7 +37439,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_18_drive_strength_18_qs; end - addr_hit[275]: begin + addr_hit[279]: begin reg_rdata_next[0] = mio_pad_attr_19_invert_19_qs; reg_rdata_next[1] = mio_pad_attr_19_virtual_od_en_19_qs; reg_rdata_next[2] = mio_pad_attr_19_pull_en_19_qs; @@ -37277,7 +37451,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_19_drive_strength_19_qs; end - addr_hit[276]: begin + addr_hit[280]: begin reg_rdata_next[0] = mio_pad_attr_20_invert_20_qs; reg_rdata_next[1] = mio_pad_attr_20_virtual_od_en_20_qs; reg_rdata_next[2] = mio_pad_attr_20_pull_en_20_qs; @@ -37289,7 +37463,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_20_drive_strength_20_qs; end - addr_hit[277]: begin + addr_hit[281]: begin reg_rdata_next[0] = mio_pad_attr_21_invert_21_qs; reg_rdata_next[1] = mio_pad_attr_21_virtual_od_en_21_qs; reg_rdata_next[2] = mio_pad_attr_21_pull_en_21_qs; @@ -37301,7 +37475,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_21_drive_strength_21_qs; end - addr_hit[278]: begin + addr_hit[282]: begin reg_rdata_next[0] = mio_pad_attr_22_invert_22_qs; reg_rdata_next[1] = mio_pad_attr_22_virtual_od_en_22_qs; reg_rdata_next[2] = mio_pad_attr_22_pull_en_22_qs; @@ -37313,7 +37487,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_22_drive_strength_22_qs; end - addr_hit[279]: begin + addr_hit[283]: begin reg_rdata_next[0] = mio_pad_attr_23_invert_23_qs; reg_rdata_next[1] = mio_pad_attr_23_virtual_od_en_23_qs; reg_rdata_next[2] = mio_pad_attr_23_pull_en_23_qs; @@ -37325,7 +37499,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_23_drive_strength_23_qs; end - addr_hit[280]: begin + addr_hit[284]: begin reg_rdata_next[0] = mio_pad_attr_24_invert_24_qs; reg_rdata_next[1] = mio_pad_attr_24_virtual_od_en_24_qs; reg_rdata_next[2] = mio_pad_attr_24_pull_en_24_qs; @@ -37337,7 +37511,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_24_drive_strength_24_qs; end - addr_hit[281]: begin + addr_hit[285]: begin reg_rdata_next[0] = mio_pad_attr_25_invert_25_qs; reg_rdata_next[1] = mio_pad_attr_25_virtual_od_en_25_qs; reg_rdata_next[2] = mio_pad_attr_25_pull_en_25_qs; @@ -37349,7 +37523,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_25_drive_strength_25_qs; end - addr_hit[282]: begin + addr_hit[286]: begin reg_rdata_next[0] = mio_pad_attr_26_invert_26_qs; reg_rdata_next[1] = mio_pad_attr_26_virtual_od_en_26_qs; reg_rdata_next[2] = mio_pad_attr_26_pull_en_26_qs; @@ -37361,7 +37535,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_26_drive_strength_26_qs; end - addr_hit[283]: begin + addr_hit[287]: begin reg_rdata_next[0] = mio_pad_attr_27_invert_27_qs; reg_rdata_next[1] = mio_pad_attr_27_virtual_od_en_27_qs; reg_rdata_next[2] = mio_pad_attr_27_pull_en_27_qs; @@ -37373,7 +37547,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_27_drive_strength_27_qs; end - addr_hit[284]: begin + addr_hit[288]: begin reg_rdata_next[0] = mio_pad_attr_28_invert_28_qs; reg_rdata_next[1] = mio_pad_attr_28_virtual_od_en_28_qs; reg_rdata_next[2] = mio_pad_attr_28_pull_en_28_qs; @@ -37385,7 +37559,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_28_drive_strength_28_qs; end - addr_hit[285]: begin + addr_hit[289]: begin reg_rdata_next[0] = mio_pad_attr_29_invert_29_qs; reg_rdata_next[1] = mio_pad_attr_29_virtual_od_en_29_qs; reg_rdata_next[2] = mio_pad_attr_29_pull_en_29_qs; @@ -37397,7 +37571,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_29_drive_strength_29_qs; end - addr_hit[286]: begin + addr_hit[290]: begin reg_rdata_next[0] = mio_pad_attr_30_invert_30_qs; reg_rdata_next[1] = mio_pad_attr_30_virtual_od_en_30_qs; reg_rdata_next[2] = mio_pad_attr_30_pull_en_30_qs; @@ -37409,7 +37583,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_30_drive_strength_30_qs; end - addr_hit[287]: begin + addr_hit[291]: begin reg_rdata_next[0] = mio_pad_attr_31_invert_31_qs; reg_rdata_next[1] = mio_pad_attr_31_virtual_od_en_31_qs; reg_rdata_next[2] = mio_pad_attr_31_pull_en_31_qs; @@ -37421,7 +37595,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_31_drive_strength_31_qs; end - addr_hit[288]: begin + addr_hit[292]: begin reg_rdata_next[0] = mio_pad_attr_32_invert_32_qs; reg_rdata_next[1] = mio_pad_attr_32_virtual_od_en_32_qs; reg_rdata_next[2] = mio_pad_attr_32_pull_en_32_qs; @@ -37433,7 +37607,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_32_drive_strength_32_qs; end - addr_hit[289]: begin + addr_hit[293]: begin reg_rdata_next[0] = mio_pad_attr_33_invert_33_qs; reg_rdata_next[1] = mio_pad_attr_33_virtual_od_en_33_qs; reg_rdata_next[2] = mio_pad_attr_33_pull_en_33_qs; @@ -37445,7 +37619,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_33_drive_strength_33_qs; end - addr_hit[290]: begin + addr_hit[294]: begin reg_rdata_next[0] = mio_pad_attr_34_invert_34_qs; reg_rdata_next[1] = mio_pad_attr_34_virtual_od_en_34_qs; reg_rdata_next[2] = mio_pad_attr_34_pull_en_34_qs; @@ -37457,7 +37631,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_34_drive_strength_34_qs; end - addr_hit[291]: begin + addr_hit[295]: begin reg_rdata_next[0] = mio_pad_attr_35_invert_35_qs; reg_rdata_next[1] = mio_pad_attr_35_virtual_od_en_35_qs; reg_rdata_next[2] = mio_pad_attr_35_pull_en_35_qs; @@ -37469,7 +37643,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_35_drive_strength_35_qs; end - addr_hit[292]: begin + addr_hit[296]: begin reg_rdata_next[0] = mio_pad_attr_36_invert_36_qs; reg_rdata_next[1] = mio_pad_attr_36_virtual_od_en_36_qs; reg_rdata_next[2] = mio_pad_attr_36_pull_en_36_qs; @@ -37481,7 +37655,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_36_drive_strength_36_qs; end - addr_hit[293]: begin + addr_hit[297]: begin reg_rdata_next[0] = mio_pad_attr_37_invert_37_qs; reg_rdata_next[1] = mio_pad_attr_37_virtual_od_en_37_qs; reg_rdata_next[2] = mio_pad_attr_37_pull_en_37_qs; @@ -37493,7 +37667,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_37_drive_strength_37_qs; end - addr_hit[294]: begin + addr_hit[298]: begin reg_rdata_next[0] = mio_pad_attr_38_invert_38_qs; reg_rdata_next[1] = mio_pad_attr_38_virtual_od_en_38_qs; reg_rdata_next[2] = mio_pad_attr_38_pull_en_38_qs; @@ -37505,7 +37679,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_38_drive_strength_38_qs; end - addr_hit[295]: begin + addr_hit[299]: begin reg_rdata_next[0] = mio_pad_attr_39_invert_39_qs; reg_rdata_next[1] = mio_pad_attr_39_virtual_od_en_39_qs; reg_rdata_next[2] = mio_pad_attr_39_pull_en_39_qs; @@ -37517,7 +37691,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_39_drive_strength_39_qs; end - addr_hit[296]: begin + addr_hit[300]: begin reg_rdata_next[0] = mio_pad_attr_40_invert_40_qs; reg_rdata_next[1] = mio_pad_attr_40_virtual_od_en_40_qs; reg_rdata_next[2] = mio_pad_attr_40_pull_en_40_qs; @@ -37529,7 +37703,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_40_drive_strength_40_qs; end - addr_hit[297]: begin + addr_hit[301]: begin reg_rdata_next[0] = mio_pad_attr_41_invert_41_qs; reg_rdata_next[1] = mio_pad_attr_41_virtual_od_en_41_qs; reg_rdata_next[2] = mio_pad_attr_41_pull_en_41_qs; @@ -37541,7 +37715,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_41_drive_strength_41_qs; end - addr_hit[298]: begin + addr_hit[302]: begin reg_rdata_next[0] = mio_pad_attr_42_invert_42_qs; reg_rdata_next[1] = mio_pad_attr_42_virtual_od_en_42_qs; reg_rdata_next[2] = mio_pad_attr_42_pull_en_42_qs; @@ -37553,7 +37727,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_42_drive_strength_42_qs; end - addr_hit[299]: begin + addr_hit[303]: begin reg_rdata_next[0] = mio_pad_attr_43_invert_43_qs; reg_rdata_next[1] = mio_pad_attr_43_virtual_od_en_43_qs; reg_rdata_next[2] = mio_pad_attr_43_pull_en_43_qs; @@ -37565,7 +37739,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_43_drive_strength_43_qs; end - addr_hit[300]: begin + addr_hit[304]: begin reg_rdata_next[0] = mio_pad_attr_44_invert_44_qs; reg_rdata_next[1] = mio_pad_attr_44_virtual_od_en_44_qs; reg_rdata_next[2] = mio_pad_attr_44_pull_en_44_qs; @@ -37577,7 +37751,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_44_drive_strength_44_qs; end - addr_hit[301]: begin + addr_hit[305]: begin reg_rdata_next[0] = mio_pad_attr_45_invert_45_qs; reg_rdata_next[1] = mio_pad_attr_45_virtual_od_en_45_qs; reg_rdata_next[2] = mio_pad_attr_45_pull_en_45_qs; @@ -37589,7 +37763,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_45_drive_strength_45_qs; end - addr_hit[302]: begin + addr_hit[306]: begin reg_rdata_next[0] = mio_pad_attr_46_invert_46_qs; reg_rdata_next[1] = mio_pad_attr_46_virtual_od_en_46_qs; reg_rdata_next[2] = mio_pad_attr_46_pull_en_46_qs; @@ -37601,71 +37775,71 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_46_drive_strength_46_qs; end - addr_hit[303]: begin + addr_hit[307]: begin reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; end - addr_hit[304]: begin + addr_hit[308]: begin reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; end - addr_hit[305]: begin + addr_hit[309]: begin reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; end - addr_hit[306]: begin + addr_hit[310]: begin reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; end - addr_hit[307]: begin + addr_hit[311]: begin reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; end - addr_hit[308]: begin + addr_hit[312]: begin reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; end - addr_hit[309]: begin + addr_hit[313]: begin reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; end - addr_hit[310]: begin + addr_hit[314]: begin reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; end - addr_hit[311]: begin + addr_hit[315]: begin reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; end - addr_hit[312]: begin + addr_hit[316]: begin reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; end - addr_hit[313]: begin + addr_hit[317]: begin reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; end - addr_hit[314]: begin + addr_hit[318]: begin reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; end - addr_hit[315]: begin + addr_hit[319]: begin reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; end - addr_hit[316]: begin + addr_hit[320]: begin reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; end - addr_hit[317]: begin + addr_hit[321]: begin reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; end - addr_hit[318]: begin + addr_hit[322]: begin reg_rdata_next[0] = dio_pad_attr_regwen_15_qs; end - addr_hit[319]: begin + addr_hit[323]: begin reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs; @@ -37677,7 +37851,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs; end - addr_hit[320]: begin + addr_hit[324]: begin reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs; @@ -37689,7 +37863,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs; end - addr_hit[321]: begin + addr_hit[325]: begin reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs; @@ -37701,7 +37875,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs; end - addr_hit[322]: begin + addr_hit[326]: begin reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs; @@ -37713,7 +37887,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs; end - addr_hit[323]: begin + addr_hit[327]: begin reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs; @@ -37725,7 +37899,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs; end - addr_hit[324]: begin + addr_hit[328]: begin reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs; @@ -37737,7 +37911,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs; end - addr_hit[325]: begin + addr_hit[329]: begin reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs; @@ -37749,7 +37923,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs; end - addr_hit[326]: begin + addr_hit[330]: begin reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs; @@ -37761,7 +37935,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs; end - addr_hit[327]: begin + addr_hit[331]: begin reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs; @@ -37773,7 +37947,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs; end - addr_hit[328]: begin + addr_hit[332]: begin reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs; @@ -37785,7 +37959,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs; end - addr_hit[329]: begin + addr_hit[333]: begin reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs; @@ -37797,7 +37971,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs; end - addr_hit[330]: begin + addr_hit[334]: begin reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs; @@ -37809,7 +37983,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs; end - addr_hit[331]: begin + addr_hit[335]: begin reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs; @@ -37821,7 +37995,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs; end - addr_hit[332]: begin + addr_hit[336]: begin reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs; @@ -37833,7 +38007,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs; end - addr_hit[333]: begin + addr_hit[337]: begin reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs; @@ -37845,7 +38019,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs; end - addr_hit[334]: begin + addr_hit[338]: begin reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs; @@ -37857,7 +38031,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs; end - addr_hit[335]: begin + addr_hit[339]: begin reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs; reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs; reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs; @@ -37892,7 +38066,7 @@ module pinmux_reg_top ( reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs; end - addr_hit[336]: begin + addr_hit[340]: begin reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs; reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs; reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs; @@ -37910,571 +38084,571 @@ module pinmux_reg_top ( reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs; end - addr_hit[337]: begin + addr_hit[341]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; end - addr_hit[338]: begin + addr_hit[342]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; end - addr_hit[339]: begin + addr_hit[343]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; end - addr_hit[340]: begin + addr_hit[344]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; end - addr_hit[341]: begin + addr_hit[345]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; end - addr_hit[342]: begin + addr_hit[346]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; end - addr_hit[343]: begin + addr_hit[347]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; end - addr_hit[344]: begin + addr_hit[348]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; end - addr_hit[345]: begin + addr_hit[349]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; end - addr_hit[346]: begin + addr_hit[350]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; end - addr_hit[347]: begin + addr_hit[351]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; end - addr_hit[348]: begin + addr_hit[352]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; end - addr_hit[349]: begin + addr_hit[353]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs; end - addr_hit[350]: begin + addr_hit[354]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs; end - addr_hit[351]: begin + addr_hit[355]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs; end - addr_hit[352]: begin + addr_hit[356]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs; end - addr_hit[353]: begin + addr_hit[357]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs; end - addr_hit[354]: begin + addr_hit[358]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs; end - addr_hit[355]: begin + addr_hit[359]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs; end - addr_hit[356]: begin + addr_hit[360]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs; end - addr_hit[357]: begin + addr_hit[361]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs; end - addr_hit[358]: begin + addr_hit[362]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs; end - addr_hit[359]: begin + addr_hit[363]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs; end - addr_hit[360]: begin + addr_hit[364]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs; end - addr_hit[361]: begin + addr_hit[365]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs; end - addr_hit[362]: begin + addr_hit[366]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs; end - addr_hit[363]: begin + addr_hit[367]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs; end - addr_hit[364]: begin + addr_hit[368]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs; end - addr_hit[365]: begin + addr_hit[369]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs; end - addr_hit[366]: begin + addr_hit[370]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs; end - addr_hit[367]: begin + addr_hit[371]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs; end - addr_hit[368]: begin + addr_hit[372]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs; end - addr_hit[369]: begin + addr_hit[373]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs; end - addr_hit[370]: begin + addr_hit[374]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs; end - addr_hit[371]: begin + addr_hit[375]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs; end - addr_hit[372]: begin + addr_hit[376]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs; end - addr_hit[373]: begin + addr_hit[377]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs; end - addr_hit[374]: begin + addr_hit[378]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs; end - addr_hit[375]: begin + addr_hit[379]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs; end - addr_hit[376]: begin + addr_hit[380]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs; end - addr_hit[377]: begin + addr_hit[381]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs; end - addr_hit[378]: begin + addr_hit[382]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs; end - addr_hit[379]: begin + addr_hit[383]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs; end - addr_hit[380]: begin + addr_hit[384]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs; end - addr_hit[381]: begin + addr_hit[385]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs; end - addr_hit[382]: begin + addr_hit[386]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs; end - addr_hit[383]: begin + addr_hit[387]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs; end - addr_hit[384]: begin + addr_hit[388]: begin reg_rdata_next[0] = mio_pad_sleep_en_0_qs; end - addr_hit[385]: begin + addr_hit[389]: begin reg_rdata_next[0] = mio_pad_sleep_en_1_qs; end - addr_hit[386]: begin + addr_hit[390]: begin reg_rdata_next[0] = mio_pad_sleep_en_2_qs; end - addr_hit[387]: begin + addr_hit[391]: begin reg_rdata_next[0] = mio_pad_sleep_en_3_qs; end - addr_hit[388]: begin + addr_hit[392]: begin reg_rdata_next[0] = mio_pad_sleep_en_4_qs; end - addr_hit[389]: begin + addr_hit[393]: begin reg_rdata_next[0] = mio_pad_sleep_en_5_qs; end - addr_hit[390]: begin + addr_hit[394]: begin reg_rdata_next[0] = mio_pad_sleep_en_6_qs; end - addr_hit[391]: begin + addr_hit[395]: begin reg_rdata_next[0] = mio_pad_sleep_en_7_qs; end - addr_hit[392]: begin + addr_hit[396]: begin reg_rdata_next[0] = mio_pad_sleep_en_8_qs; end - addr_hit[393]: begin + addr_hit[397]: begin reg_rdata_next[0] = mio_pad_sleep_en_9_qs; end - addr_hit[394]: begin + addr_hit[398]: begin reg_rdata_next[0] = mio_pad_sleep_en_10_qs; end - addr_hit[395]: begin + addr_hit[399]: begin reg_rdata_next[0] = mio_pad_sleep_en_11_qs; end - addr_hit[396]: begin + addr_hit[400]: begin reg_rdata_next[0] = mio_pad_sleep_en_12_qs; end - addr_hit[397]: begin + addr_hit[401]: begin reg_rdata_next[0] = mio_pad_sleep_en_13_qs; end - addr_hit[398]: begin + addr_hit[402]: begin reg_rdata_next[0] = mio_pad_sleep_en_14_qs; end - addr_hit[399]: begin + addr_hit[403]: begin reg_rdata_next[0] = mio_pad_sleep_en_15_qs; end - addr_hit[400]: begin + addr_hit[404]: begin reg_rdata_next[0] = mio_pad_sleep_en_16_qs; end - addr_hit[401]: begin + addr_hit[405]: begin reg_rdata_next[0] = mio_pad_sleep_en_17_qs; end - addr_hit[402]: begin + addr_hit[406]: begin reg_rdata_next[0] = mio_pad_sleep_en_18_qs; end - addr_hit[403]: begin + addr_hit[407]: begin reg_rdata_next[0] = mio_pad_sleep_en_19_qs; end - addr_hit[404]: begin + addr_hit[408]: begin reg_rdata_next[0] = mio_pad_sleep_en_20_qs; end - addr_hit[405]: begin + addr_hit[409]: begin reg_rdata_next[0] = mio_pad_sleep_en_21_qs; end - addr_hit[406]: begin + addr_hit[410]: begin reg_rdata_next[0] = mio_pad_sleep_en_22_qs; end - addr_hit[407]: begin + addr_hit[411]: begin reg_rdata_next[0] = mio_pad_sleep_en_23_qs; end - addr_hit[408]: begin + addr_hit[412]: begin reg_rdata_next[0] = mio_pad_sleep_en_24_qs; end - addr_hit[409]: begin + addr_hit[413]: begin reg_rdata_next[0] = mio_pad_sleep_en_25_qs; end - addr_hit[410]: begin + addr_hit[414]: begin reg_rdata_next[0] = mio_pad_sleep_en_26_qs; end - addr_hit[411]: begin + addr_hit[415]: begin reg_rdata_next[0] = mio_pad_sleep_en_27_qs; end - addr_hit[412]: begin + addr_hit[416]: begin reg_rdata_next[0] = mio_pad_sleep_en_28_qs; end - addr_hit[413]: begin + addr_hit[417]: begin reg_rdata_next[0] = mio_pad_sleep_en_29_qs; end - addr_hit[414]: begin + addr_hit[418]: begin reg_rdata_next[0] = mio_pad_sleep_en_30_qs; end - addr_hit[415]: begin + addr_hit[419]: begin reg_rdata_next[0] = mio_pad_sleep_en_31_qs; end - addr_hit[416]: begin + addr_hit[420]: begin reg_rdata_next[0] = mio_pad_sleep_en_32_qs; end - addr_hit[417]: begin + addr_hit[421]: begin reg_rdata_next[0] = mio_pad_sleep_en_33_qs; end - addr_hit[418]: begin + addr_hit[422]: begin reg_rdata_next[0] = mio_pad_sleep_en_34_qs; end - addr_hit[419]: begin + addr_hit[423]: begin reg_rdata_next[0] = mio_pad_sleep_en_35_qs; end - addr_hit[420]: begin + addr_hit[424]: begin reg_rdata_next[0] = mio_pad_sleep_en_36_qs; end - addr_hit[421]: begin + addr_hit[425]: begin reg_rdata_next[0] = mio_pad_sleep_en_37_qs; end - addr_hit[422]: begin + addr_hit[426]: begin reg_rdata_next[0] = mio_pad_sleep_en_38_qs; end - addr_hit[423]: begin + addr_hit[427]: begin reg_rdata_next[0] = mio_pad_sleep_en_39_qs; end - addr_hit[424]: begin + addr_hit[428]: begin reg_rdata_next[0] = mio_pad_sleep_en_40_qs; end - addr_hit[425]: begin + addr_hit[429]: begin reg_rdata_next[0] = mio_pad_sleep_en_41_qs; end - addr_hit[426]: begin + addr_hit[430]: begin reg_rdata_next[0] = mio_pad_sleep_en_42_qs; end - addr_hit[427]: begin + addr_hit[431]: begin reg_rdata_next[0] = mio_pad_sleep_en_43_qs; end - addr_hit[428]: begin + addr_hit[432]: begin reg_rdata_next[0] = mio_pad_sleep_en_44_qs; end - addr_hit[429]: begin + addr_hit[433]: begin reg_rdata_next[0] = mio_pad_sleep_en_45_qs; end - addr_hit[430]: begin + addr_hit[434]: begin reg_rdata_next[0] = mio_pad_sleep_en_46_qs; end - addr_hit[431]: begin + addr_hit[435]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; end - addr_hit[432]: begin + addr_hit[436]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; end - addr_hit[433]: begin + addr_hit[437]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; end - addr_hit[434]: begin + addr_hit[438]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; end - addr_hit[435]: begin + addr_hit[439]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; end - addr_hit[436]: begin + addr_hit[440]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; end - addr_hit[437]: begin + addr_hit[441]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; end - addr_hit[438]: begin + addr_hit[442]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; end - addr_hit[439]: begin + addr_hit[443]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; end - addr_hit[440]: begin + addr_hit[444]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; end - addr_hit[441]: begin + addr_hit[445]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; end - addr_hit[442]: begin + addr_hit[446]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; end - addr_hit[443]: begin + addr_hit[447]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs; end - addr_hit[444]: begin + addr_hit[448]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs; end - addr_hit[445]: begin + addr_hit[449]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs; end - addr_hit[446]: begin + addr_hit[450]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs; end - addr_hit[447]: begin + addr_hit[451]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs; end - addr_hit[448]: begin + addr_hit[452]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs; end - addr_hit[449]: begin + addr_hit[453]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs; end - addr_hit[450]: begin + addr_hit[454]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs; end - addr_hit[451]: begin + addr_hit[455]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs; end - addr_hit[452]: begin + addr_hit[456]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs; end - addr_hit[453]: begin + addr_hit[457]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs; end - addr_hit[454]: begin + addr_hit[458]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs; end - addr_hit[455]: begin + addr_hit[459]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs; end - addr_hit[456]: begin + addr_hit[460]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs; end - addr_hit[457]: begin + addr_hit[461]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs; end - addr_hit[458]: begin + addr_hit[462]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs; end - addr_hit[459]: begin + addr_hit[463]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs; end - addr_hit[460]: begin + addr_hit[464]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs; end - addr_hit[461]: begin + addr_hit[465]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs; end - addr_hit[462]: begin + addr_hit[466]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs; end - addr_hit[463]: begin + addr_hit[467]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs; end - addr_hit[464]: begin + addr_hit[468]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs; end - addr_hit[465]: begin + addr_hit[469]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs; end - addr_hit[466]: begin + addr_hit[470]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs; end - addr_hit[467]: begin + addr_hit[471]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs; end - addr_hit[468]: begin + addr_hit[472]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs; end - addr_hit[469]: begin + addr_hit[473]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs; end - addr_hit[470]: begin + addr_hit[474]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs; end - addr_hit[471]: begin + addr_hit[475]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs; end - addr_hit[472]: begin + addr_hit[476]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs; end - addr_hit[473]: begin + addr_hit[477]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs; end - addr_hit[474]: begin + addr_hit[478]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs; end - addr_hit[475]: begin + addr_hit[479]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs; end - addr_hit[476]: begin + addr_hit[480]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs; end - addr_hit[477]: begin + addr_hit[481]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs; end - addr_hit[478]: begin + addr_hit[482]: begin reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs; reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs; reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs; @@ -38493,335 +38667,335 @@ module pinmux_reg_top ( reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs; end - addr_hit[479]: begin + addr_hit[483]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; end - addr_hit[480]: begin + addr_hit[484]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; end - addr_hit[481]: begin + addr_hit[485]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; end - addr_hit[482]: begin + addr_hit[486]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; end - addr_hit[483]: begin + addr_hit[487]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; end - addr_hit[484]: begin + addr_hit[488]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; end - addr_hit[485]: begin + addr_hit[489]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; end - addr_hit[486]: begin + addr_hit[490]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; end - addr_hit[487]: begin + addr_hit[491]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; end - addr_hit[488]: begin + addr_hit[492]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; end - addr_hit[489]: begin + addr_hit[493]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; end - addr_hit[490]: begin + addr_hit[494]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; end - addr_hit[491]: begin + addr_hit[495]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; end - addr_hit[492]: begin + addr_hit[496]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; end - addr_hit[493]: begin + addr_hit[497]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; end - addr_hit[494]: begin + addr_hit[498]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs; end - addr_hit[495]: begin + addr_hit[499]: begin reg_rdata_next[0] = dio_pad_sleep_en_0_qs; end - addr_hit[496]: begin + addr_hit[500]: begin reg_rdata_next[0] = dio_pad_sleep_en_1_qs; end - addr_hit[497]: begin + addr_hit[501]: begin reg_rdata_next[0] = dio_pad_sleep_en_2_qs; end - addr_hit[498]: begin + addr_hit[502]: begin reg_rdata_next[0] = dio_pad_sleep_en_3_qs; end - addr_hit[499]: begin + addr_hit[503]: begin reg_rdata_next[0] = dio_pad_sleep_en_4_qs; end - addr_hit[500]: begin + addr_hit[504]: begin reg_rdata_next[0] = dio_pad_sleep_en_5_qs; end - addr_hit[501]: begin + addr_hit[505]: begin reg_rdata_next[0] = dio_pad_sleep_en_6_qs; end - addr_hit[502]: begin + addr_hit[506]: begin reg_rdata_next[0] = dio_pad_sleep_en_7_qs; end - addr_hit[503]: begin + addr_hit[507]: begin reg_rdata_next[0] = dio_pad_sleep_en_8_qs; end - addr_hit[504]: begin + addr_hit[508]: begin reg_rdata_next[0] = dio_pad_sleep_en_9_qs; end - addr_hit[505]: begin + addr_hit[509]: begin reg_rdata_next[0] = dio_pad_sleep_en_10_qs; end - addr_hit[506]: begin + addr_hit[510]: begin reg_rdata_next[0] = dio_pad_sleep_en_11_qs; end - addr_hit[507]: begin + addr_hit[511]: begin reg_rdata_next[0] = dio_pad_sleep_en_12_qs; end - addr_hit[508]: begin + addr_hit[512]: begin reg_rdata_next[0] = dio_pad_sleep_en_13_qs; end - addr_hit[509]: begin + addr_hit[513]: begin reg_rdata_next[0] = dio_pad_sleep_en_14_qs; end - addr_hit[510]: begin + addr_hit[514]: begin reg_rdata_next[0] = dio_pad_sleep_en_15_qs; end - addr_hit[511]: begin + addr_hit[515]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; end - addr_hit[512]: begin + addr_hit[516]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; end - addr_hit[513]: begin + addr_hit[517]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; end - addr_hit[514]: begin + addr_hit[518]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; end - addr_hit[515]: begin + addr_hit[519]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; end - addr_hit[516]: begin + addr_hit[520]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; end - addr_hit[517]: begin + addr_hit[521]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; end - addr_hit[518]: begin + addr_hit[522]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; end - addr_hit[519]: begin + addr_hit[523]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; end - addr_hit[520]: begin + addr_hit[524]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; end - addr_hit[521]: begin + addr_hit[525]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; end - addr_hit[522]: begin + addr_hit[526]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; end - addr_hit[523]: begin + addr_hit[527]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; end - addr_hit[524]: begin + addr_hit[528]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; end - addr_hit[525]: begin + addr_hit[529]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; end - addr_hit[526]: begin + addr_hit[530]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs; end - addr_hit[527]: begin + addr_hit[531]: begin reg_rdata_next[0] = wkup_detector_regwen_0_qs; end - addr_hit[528]: begin + addr_hit[532]: begin reg_rdata_next[0] = wkup_detector_regwen_1_qs; end - addr_hit[529]: begin + addr_hit[533]: begin reg_rdata_next[0] = wkup_detector_regwen_2_qs; end - addr_hit[530]: begin + addr_hit[534]: begin reg_rdata_next[0] = wkup_detector_regwen_3_qs; end - addr_hit[531]: begin + addr_hit[535]: begin reg_rdata_next[0] = wkup_detector_regwen_4_qs; end - addr_hit[532]: begin + addr_hit[536]: begin reg_rdata_next[0] = wkup_detector_regwen_5_qs; end - addr_hit[533]: begin + addr_hit[537]: begin reg_rdata_next[0] = wkup_detector_regwen_6_qs; end - addr_hit[534]: begin + addr_hit[538]: begin reg_rdata_next[0] = wkup_detector_regwen_7_qs; end - addr_hit[535]: begin + addr_hit[539]: begin reg_rdata_next = DW'(wkup_detector_en_0_qs); end - addr_hit[536]: begin + addr_hit[540]: begin reg_rdata_next = DW'(wkup_detector_en_1_qs); end - addr_hit[537]: begin + addr_hit[541]: begin reg_rdata_next = DW'(wkup_detector_en_2_qs); end - addr_hit[538]: begin + addr_hit[542]: begin reg_rdata_next = DW'(wkup_detector_en_3_qs); end - addr_hit[539]: begin + addr_hit[543]: begin reg_rdata_next = DW'(wkup_detector_en_4_qs); end - addr_hit[540]: begin + addr_hit[544]: begin reg_rdata_next = DW'(wkup_detector_en_5_qs); end - addr_hit[541]: begin + addr_hit[545]: begin reg_rdata_next = DW'(wkup_detector_en_6_qs); end - addr_hit[542]: begin + addr_hit[546]: begin reg_rdata_next = DW'(wkup_detector_en_7_qs); end - addr_hit[543]: begin + addr_hit[547]: begin reg_rdata_next = DW'(wkup_detector_0_qs); end - addr_hit[544]: begin + addr_hit[548]: begin reg_rdata_next = DW'(wkup_detector_1_qs); end - addr_hit[545]: begin + addr_hit[549]: begin reg_rdata_next = DW'(wkup_detector_2_qs); end - addr_hit[546]: begin + addr_hit[550]: begin reg_rdata_next = DW'(wkup_detector_3_qs); end - addr_hit[547]: begin + addr_hit[551]: begin reg_rdata_next = DW'(wkup_detector_4_qs); end - addr_hit[548]: begin + addr_hit[552]: begin reg_rdata_next = DW'(wkup_detector_5_qs); end - addr_hit[549]: begin + addr_hit[553]: begin reg_rdata_next = DW'(wkup_detector_6_qs); end - addr_hit[550]: begin + addr_hit[554]: begin reg_rdata_next = DW'(wkup_detector_7_qs); end - addr_hit[551]: begin + addr_hit[555]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs); end - addr_hit[552]: begin + addr_hit[556]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs); end - addr_hit[553]: begin + addr_hit[557]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs); end - addr_hit[554]: begin + addr_hit[558]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs); end - addr_hit[555]: begin + addr_hit[559]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs); end - addr_hit[556]: begin + addr_hit[560]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs); end - addr_hit[557]: begin + addr_hit[561]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs); end - addr_hit[558]: begin + addr_hit[562]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs); end - addr_hit[559]: begin + addr_hit[563]: begin reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; end - addr_hit[560]: begin + addr_hit[564]: begin reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; end - addr_hit[561]: begin + addr_hit[565]: begin reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; end - addr_hit[562]: begin + addr_hit[566]: begin reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; end - addr_hit[563]: begin + addr_hit[567]: begin reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; end - addr_hit[564]: begin + addr_hit[568]: begin reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; end - addr_hit[565]: begin + addr_hit[569]: begin reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; end - addr_hit[566]: begin + addr_hit[570]: begin reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; end - addr_hit[567]: begin + addr_hit[571]: begin reg_rdata_next = DW'(wkup_cause_qs); end default: begin @@ -38840,79 +39014,79 @@ module pinmux_reg_top ( always_comb begin reg_busy_sel = '0; unique case (1'b1) - addr_hit[535]: begin + addr_hit[539]: begin reg_busy_sel = wkup_detector_en_0_busy; end - addr_hit[536]: begin + addr_hit[540]: begin reg_busy_sel = wkup_detector_en_1_busy; end - addr_hit[537]: begin + addr_hit[541]: begin reg_busy_sel = wkup_detector_en_2_busy; end - addr_hit[538]: begin + addr_hit[542]: begin reg_busy_sel = wkup_detector_en_3_busy; end - addr_hit[539]: begin + addr_hit[543]: begin reg_busy_sel = wkup_detector_en_4_busy; end - addr_hit[540]: begin + addr_hit[544]: begin reg_busy_sel = wkup_detector_en_5_busy; end - addr_hit[541]: begin + addr_hit[545]: begin reg_busy_sel = wkup_detector_en_6_busy; end - addr_hit[542]: begin + addr_hit[546]: begin reg_busy_sel = wkup_detector_en_7_busy; end - addr_hit[543]: begin + addr_hit[547]: begin reg_busy_sel = wkup_detector_0_busy; end - addr_hit[544]: begin + addr_hit[548]: begin reg_busy_sel = wkup_detector_1_busy; end - addr_hit[545]: begin + addr_hit[549]: begin reg_busy_sel = wkup_detector_2_busy; end - addr_hit[546]: begin + addr_hit[550]: begin reg_busy_sel = wkup_detector_3_busy; end - addr_hit[547]: begin + addr_hit[551]: begin reg_busy_sel = wkup_detector_4_busy; end - addr_hit[548]: begin + addr_hit[552]: begin reg_busy_sel = wkup_detector_5_busy; end - addr_hit[549]: begin + addr_hit[553]: begin reg_busy_sel = wkup_detector_6_busy; end - addr_hit[550]: begin + addr_hit[554]: begin reg_busy_sel = wkup_detector_7_busy; end - addr_hit[551]: begin + addr_hit[555]: begin reg_busy_sel = wkup_detector_cnt_th_0_busy; end - addr_hit[552]: begin + addr_hit[556]: begin reg_busy_sel = wkup_detector_cnt_th_1_busy; end - addr_hit[553]: begin + addr_hit[557]: begin reg_busy_sel = wkup_detector_cnt_th_2_busy; end - addr_hit[554]: begin + addr_hit[558]: begin reg_busy_sel = wkup_detector_cnt_th_3_busy; end - addr_hit[555]: begin + addr_hit[559]: begin reg_busy_sel = wkup_detector_cnt_th_4_busy; end - addr_hit[556]: begin + addr_hit[560]: begin reg_busy_sel = wkup_detector_cnt_th_5_busy; end - addr_hit[557]: begin + addr_hit[561]: begin reg_busy_sel = wkup_detector_cnt_th_6_busy; end - addr_hit[558]: begin + addr_hit[562]: begin reg_busy_sel = wkup_detector_cnt_th_7_busy; end - addr_hit[567]: begin + addr_hit[571]: begin reg_busy_sel = wkup_cause_busy; end default: begin diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 7024bdfddeec15..de98c2f39fcee6 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson @@ -41,6 +41,7 @@ i2c0 i2c1 i2c2 + i2c3 pattgen gpio spi_device @@ -203,6 +204,24 @@ stub: false req_fifo_pass: true } + { + name: i2c3 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: i2c + addr_range: + [ + { + base_addr: 0x400b0000 + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } { name: pattgen type: device diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson index 711719862c35f6..8c167a0c4e4d01 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson @@ -61,6 +61,12 @@ act: "req" package: "tlul_pkg" } + { struct: "tl" + type: "req_rsp" + name: "tl_i2c3" + act: "req" + package: "tlul_pkg" + } { struct: "tl" type: "req_rsp" name: "tl_pattgen" diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv index 4dbad9bc51dd9c..f2f1c3472eefa0 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv @@ -24,6 +24,7 @@ initial force dut.rst_peri_ni = rst_n; `CONNECT_TL_DEVICE_IF(i2c0, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(i2c1, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(i2c2, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(i2c3, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(pattgen, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(pwm_aon, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n) diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg index 75d65fd27ee9ae..8f1d5d20ff7a52 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg @@ -43,6 +43,10 @@ -node tb.dut tl_i2c2_o.a_address[18:18] -node tb.dut tl_i2c2_o.a_address[29:20] -node tb.dut tl_i2c2_o.a_address[31:31] +-node tb.dut tl_i2c3_o.a_address[15:7] +-node tb.dut tl_i2c3_o.a_address[18:18] +-node tb.dut tl_i2c3_o.a_address[29:20] +-node tb.dut tl_i2c3_o.a_address[31:31] -node tb.dut tl_pattgen_o.a_address[16:6] -node tb.dut tl_pattgen_o.a_address[29:20] -node tb.dut tl_pattgen_o.a_address[31:31] diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv index 7c471f01c17cba..b43a70526997c6 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv @@ -28,6 +28,9 @@ tl_device_t xbar_devices[$] = '{ '{"i2c2", '{ '{32'h400a0000, 32'h400a007f} }}, + '{"i2c3", '{ + '{32'h400b0000, 32'h400b007f} + }}, '{"pattgen", '{ '{32'h400e0000, 32'h400e003f} }}, @@ -99,6 +102,7 @@ tl_host_t xbar_hosts[$] = '{ "i2c0", "i2c1", "i2c2", + "i2c3", "pattgen", "gpio", "spi_device", diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv index 9a45ebc55a0410..7d03fedb94f25a 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv @@ -56,6 +56,12 @@ module xbar_peri_bind; .h2d (tl_i2c2_o), .d2h (tl_i2c2_i) ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c3 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_i2c3_o), + .d2h (tl_i2c3_i) + ); bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pattgen ( .clk_i (clk_peri_i), .rst_ni (rst_peri_ni), diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv index ab40188fa51a1a..58a71130b1e931 100644 --- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv @@ -13,6 +13,7 @@ package tl_peri_pkg; localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 40080000; localparam logic [31:0] ADDR_SPACE_I2C1 = 32'h 40090000; localparam logic [31:0] ADDR_SPACE_I2C2 = 32'h 400a0000; + localparam logic [31:0] ADDR_SPACE_I2C3 = 32'h 400b0000; localparam logic [31:0] ADDR_SPACE_PATTGEN = 32'h 400e0000; localparam logic [31:0] ADDR_SPACE_PWM_AON = 32'h 40450000; localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000; @@ -41,6 +42,7 @@ package tl_peri_pkg; localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_I2C1 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_I2C2 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_I2C3 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_PATTGEN = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_PWM_AON = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_GPIO = 32'h 0000003f; @@ -63,7 +65,7 @@ package tl_peri_pkg; localparam logic [31:0] ADDR_MASK_AST = 32'h 000003ff; localparam int N_HOST = 1; - localparam int N_DEVICE = 27; + localparam int N_DEVICE = 28; typedef enum int { TlUart0 = 0, @@ -73,26 +75,27 @@ package tl_peri_pkg; TlI2C0 = 4, TlI2C1 = 5, TlI2C2 = 6, - TlPattgen = 7, - TlPwmAon = 8, - TlGpio = 9, - TlSpiDevice = 10, - TlRvTimer = 11, - TlPwrmgrAon = 12, - TlRstmgrAon = 13, - TlClkmgrAon = 14, - TlPinmuxAon = 15, - TlOtpCtrlCore = 16, - TlOtpCtrlPrim = 17, - TlLcCtrl = 18, - TlSensorCtrlAon = 19, - TlAlertHandler = 20, - TlSramCtrlRetAonRegs = 21, - TlSramCtrlRetAonRam = 22, - TlAonTimerAon = 23, - TlSysrstCtrlAon = 24, - TlAdcCtrlAon = 25, - TlAst = 26 + TlI2C3 = 7, + TlPattgen = 8, + TlPwmAon = 9, + TlGpio = 10, + TlSpiDevice = 11, + TlRvTimer = 12, + TlPwrmgrAon = 13, + TlRstmgrAon = 14, + TlClkmgrAon = 15, + TlPinmuxAon = 16, + TlOtpCtrlCore = 17, + TlOtpCtrlPrim = 18, + TlLcCtrl = 19, + TlSensorCtrlAon = 20, + TlAlertHandler = 21, + TlSramCtrlRetAonRegs = 22, + TlSramCtrlRetAonRam = 23, + TlAonTimerAon = 24, + TlSysrstCtrlAon = 25, + TlAdcCtrlAon = 26, + TlAst = 27 } tl_device_e; typedef enum int { diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv index 6301b4873a0d38..b224de13865793 100644 --- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv @@ -7,7 +7,7 @@ // // Interconnect // main -// -> s1n_28 +// -> s1n_29 // -> uart0 // -> uart1 // -> uart2 @@ -15,6 +15,7 @@ // -> i2c0 // -> i2c1 // -> i2c2 +// -> i2c3 // -> pattgen // -> gpio // -> spi_device @@ -59,6 +60,8 @@ module xbar_peri ( input tlul_pkg::tl_d2h_t tl_i2c1_i, output tlul_pkg::tl_h2d_t tl_i2c2_o, input tlul_pkg::tl_d2h_t tl_i2c2_i, + output tlul_pkg::tl_h2d_t tl_i2c3_o, + input tlul_pkg::tl_d2h_t tl_i2c3_i, output tlul_pkg::tl_h2d_t tl_pattgen_o, input tlul_pkg::tl_d2h_t tl_pattgen_i, output tlul_pkg::tl_h2d_t tl_pwm_aon_o, @@ -111,212 +114,219 @@ module xbar_peri ( logic unused_scanmode; assign unused_scanmode = ^scanmode_i; - tl_h2d_t tl_s1n_28_us_h2d ; - tl_d2h_t tl_s1n_28_us_d2h ; + tl_h2d_t tl_s1n_29_us_h2d ; + tl_d2h_t tl_s1n_29_us_d2h ; - tl_h2d_t tl_s1n_28_ds_h2d [27]; - tl_d2h_t tl_s1n_28_ds_d2h [27]; + tl_h2d_t tl_s1n_29_ds_h2d [28]; + tl_d2h_t tl_s1n_29_ds_d2h [28]; // Create steering signal - logic [4:0] dev_sel_s1n_28; + logic [4:0] dev_sel_s1n_29; - assign tl_uart0_o = tl_s1n_28_ds_h2d[0]; - assign tl_s1n_28_ds_d2h[0] = tl_uart0_i; + assign tl_uart0_o = tl_s1n_29_ds_h2d[0]; + assign tl_s1n_29_ds_d2h[0] = tl_uart0_i; - assign tl_uart1_o = tl_s1n_28_ds_h2d[1]; - assign tl_s1n_28_ds_d2h[1] = tl_uart1_i; + assign tl_uart1_o = tl_s1n_29_ds_h2d[1]; + assign tl_s1n_29_ds_d2h[1] = tl_uart1_i; - assign tl_uart2_o = tl_s1n_28_ds_h2d[2]; - assign tl_s1n_28_ds_d2h[2] = tl_uart2_i; + assign tl_uart2_o = tl_s1n_29_ds_h2d[2]; + assign tl_s1n_29_ds_d2h[2] = tl_uart2_i; - assign tl_uart3_o = tl_s1n_28_ds_h2d[3]; - assign tl_s1n_28_ds_d2h[3] = tl_uart3_i; + assign tl_uart3_o = tl_s1n_29_ds_h2d[3]; + assign tl_s1n_29_ds_d2h[3] = tl_uart3_i; - assign tl_i2c0_o = tl_s1n_28_ds_h2d[4]; - assign tl_s1n_28_ds_d2h[4] = tl_i2c0_i; + assign tl_i2c0_o = tl_s1n_29_ds_h2d[4]; + assign tl_s1n_29_ds_d2h[4] = tl_i2c0_i; - assign tl_i2c1_o = tl_s1n_28_ds_h2d[5]; - assign tl_s1n_28_ds_d2h[5] = tl_i2c1_i; + assign tl_i2c1_o = tl_s1n_29_ds_h2d[5]; + assign tl_s1n_29_ds_d2h[5] = tl_i2c1_i; - assign tl_i2c2_o = tl_s1n_28_ds_h2d[6]; - assign tl_s1n_28_ds_d2h[6] = tl_i2c2_i; + assign tl_i2c2_o = tl_s1n_29_ds_h2d[6]; + assign tl_s1n_29_ds_d2h[6] = tl_i2c2_i; - assign tl_pattgen_o = tl_s1n_28_ds_h2d[7]; - assign tl_s1n_28_ds_d2h[7] = tl_pattgen_i; + assign tl_i2c3_o = tl_s1n_29_ds_h2d[7]; + assign tl_s1n_29_ds_d2h[7] = tl_i2c3_i; - assign tl_gpio_o = tl_s1n_28_ds_h2d[8]; - assign tl_s1n_28_ds_d2h[8] = tl_gpio_i; + assign tl_pattgen_o = tl_s1n_29_ds_h2d[8]; + assign tl_s1n_29_ds_d2h[8] = tl_pattgen_i; - assign tl_spi_device_o = tl_s1n_28_ds_h2d[9]; - assign tl_s1n_28_ds_d2h[9] = tl_spi_device_i; + assign tl_gpio_o = tl_s1n_29_ds_h2d[9]; + assign tl_s1n_29_ds_d2h[9] = tl_gpio_i; - assign tl_rv_timer_o = tl_s1n_28_ds_h2d[10]; - assign tl_s1n_28_ds_d2h[10] = tl_rv_timer_i; + assign tl_spi_device_o = tl_s1n_29_ds_h2d[10]; + assign tl_s1n_29_ds_d2h[10] = tl_spi_device_i; - assign tl_pwrmgr_aon_o = tl_s1n_28_ds_h2d[11]; - assign tl_s1n_28_ds_d2h[11] = tl_pwrmgr_aon_i; + assign tl_rv_timer_o = tl_s1n_29_ds_h2d[11]; + assign tl_s1n_29_ds_d2h[11] = tl_rv_timer_i; - assign tl_rstmgr_aon_o = tl_s1n_28_ds_h2d[12]; - assign tl_s1n_28_ds_d2h[12] = tl_rstmgr_aon_i; + assign tl_pwrmgr_aon_o = tl_s1n_29_ds_h2d[12]; + assign tl_s1n_29_ds_d2h[12] = tl_pwrmgr_aon_i; - assign tl_clkmgr_aon_o = tl_s1n_28_ds_h2d[13]; - assign tl_s1n_28_ds_d2h[13] = tl_clkmgr_aon_i; + assign tl_rstmgr_aon_o = tl_s1n_29_ds_h2d[13]; + assign tl_s1n_29_ds_d2h[13] = tl_rstmgr_aon_i; - assign tl_pinmux_aon_o = tl_s1n_28_ds_h2d[14]; - assign tl_s1n_28_ds_d2h[14] = tl_pinmux_aon_i; + assign tl_clkmgr_aon_o = tl_s1n_29_ds_h2d[14]; + assign tl_s1n_29_ds_d2h[14] = tl_clkmgr_aon_i; - assign tl_otp_ctrl__core_o = tl_s1n_28_ds_h2d[15]; - assign tl_s1n_28_ds_d2h[15] = tl_otp_ctrl__core_i; + assign tl_pinmux_aon_o = tl_s1n_29_ds_h2d[15]; + assign tl_s1n_29_ds_d2h[15] = tl_pinmux_aon_i; - assign tl_otp_ctrl__prim_o = tl_s1n_28_ds_h2d[16]; - assign tl_s1n_28_ds_d2h[16] = tl_otp_ctrl__prim_i; + assign tl_otp_ctrl__core_o = tl_s1n_29_ds_h2d[16]; + assign tl_s1n_29_ds_d2h[16] = tl_otp_ctrl__core_i; - assign tl_lc_ctrl_o = tl_s1n_28_ds_h2d[17]; - assign tl_s1n_28_ds_d2h[17] = tl_lc_ctrl_i; + assign tl_otp_ctrl__prim_o = tl_s1n_29_ds_h2d[17]; + assign tl_s1n_29_ds_d2h[17] = tl_otp_ctrl__prim_i; - assign tl_sensor_ctrl_aon_o = tl_s1n_28_ds_h2d[18]; - assign tl_s1n_28_ds_d2h[18] = tl_sensor_ctrl_aon_i; + assign tl_lc_ctrl_o = tl_s1n_29_ds_h2d[18]; + assign tl_s1n_29_ds_d2h[18] = tl_lc_ctrl_i; - assign tl_alert_handler_o = tl_s1n_28_ds_h2d[19]; - assign tl_s1n_28_ds_d2h[19] = tl_alert_handler_i; + assign tl_sensor_ctrl_aon_o = tl_s1n_29_ds_h2d[19]; + assign tl_s1n_29_ds_d2h[19] = tl_sensor_ctrl_aon_i; - assign tl_ast_o = tl_s1n_28_ds_h2d[20]; - assign tl_s1n_28_ds_d2h[20] = tl_ast_i; + assign tl_alert_handler_o = tl_s1n_29_ds_h2d[20]; + assign tl_s1n_29_ds_d2h[20] = tl_alert_handler_i; - assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_28_ds_h2d[21]; - assign tl_s1n_28_ds_d2h[21] = tl_sram_ctrl_ret_aon__ram_i; + assign tl_ast_o = tl_s1n_29_ds_h2d[21]; + assign tl_s1n_29_ds_d2h[21] = tl_ast_i; - assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_28_ds_h2d[22]; - assign tl_s1n_28_ds_d2h[22] = tl_sram_ctrl_ret_aon__regs_i; + assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_29_ds_h2d[22]; + assign tl_s1n_29_ds_d2h[22] = tl_sram_ctrl_ret_aon__ram_i; - assign tl_aon_timer_aon_o = tl_s1n_28_ds_h2d[23]; - assign tl_s1n_28_ds_d2h[23] = tl_aon_timer_aon_i; + assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_29_ds_h2d[23]; + assign tl_s1n_29_ds_d2h[23] = tl_sram_ctrl_ret_aon__regs_i; - assign tl_adc_ctrl_aon_o = tl_s1n_28_ds_h2d[24]; - assign tl_s1n_28_ds_d2h[24] = tl_adc_ctrl_aon_i; + assign tl_aon_timer_aon_o = tl_s1n_29_ds_h2d[24]; + assign tl_s1n_29_ds_d2h[24] = tl_aon_timer_aon_i; - assign tl_sysrst_ctrl_aon_o = tl_s1n_28_ds_h2d[25]; - assign tl_s1n_28_ds_d2h[25] = tl_sysrst_ctrl_aon_i; + assign tl_adc_ctrl_aon_o = tl_s1n_29_ds_h2d[25]; + assign tl_s1n_29_ds_d2h[25] = tl_adc_ctrl_aon_i; - assign tl_pwm_aon_o = tl_s1n_28_ds_h2d[26]; - assign tl_s1n_28_ds_d2h[26] = tl_pwm_aon_i; + assign tl_sysrst_ctrl_aon_o = tl_s1n_29_ds_h2d[26]; + assign tl_s1n_29_ds_d2h[26] = tl_sysrst_ctrl_aon_i; - assign tl_s1n_28_us_h2d = tl_main_i; - assign tl_main_o = tl_s1n_28_us_d2h; + assign tl_pwm_aon_o = tl_s1n_29_ds_h2d[27]; + assign tl_s1n_29_ds_d2h[27] = tl_pwm_aon_i; + + assign tl_s1n_29_us_h2d = tl_main_i; + assign tl_main_o = tl_s1n_29_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_28 = 5'd27; - if ((tl_s1n_28_us_h2d.a_address & + dev_sel_s1n_29 = 5'd28; + if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin - dev_sel_s1n_28 = 5'd0; + dev_sel_s1n_29 = 5'd0; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin - dev_sel_s1n_28 = 5'd1; + dev_sel_s1n_29 = 5'd1; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin - dev_sel_s1n_28 = 5'd2; + dev_sel_s1n_29 = 5'd2; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin - dev_sel_s1n_28 = 5'd3; + dev_sel_s1n_29 = 5'd3; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin - dev_sel_s1n_28 = 5'd4; + dev_sel_s1n_29 = 5'd4; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin - dev_sel_s1n_28 = 5'd5; + dev_sel_s1n_29 = 5'd5; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin - dev_sel_s1n_28 = 5'd6; + dev_sel_s1n_29 = 5'd6; + + end else if ((tl_s1n_29_us_h2d.a_address & + ~(ADDR_MASK_I2C3)) == ADDR_SPACE_I2C3) begin + dev_sel_s1n_29 = 5'd7; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin - dev_sel_s1n_28 = 5'd7; + dev_sel_s1n_29 = 5'd8; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_28 = 5'd8; + dev_sel_s1n_29 = 5'd9; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin - dev_sel_s1n_28 = 5'd9; + dev_sel_s1n_29 = 5'd10; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin - dev_sel_s1n_28 = 5'd10; + dev_sel_s1n_29 = 5'd11; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin - dev_sel_s1n_28 = 5'd11; + dev_sel_s1n_29 = 5'd12; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin - dev_sel_s1n_28 = 5'd12; + dev_sel_s1n_29 = 5'd13; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin - dev_sel_s1n_28 = 5'd13; + dev_sel_s1n_29 = 5'd14; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin - dev_sel_s1n_28 = 5'd14; + dev_sel_s1n_29 = 5'd15; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin - dev_sel_s1n_28 = 5'd15; + dev_sel_s1n_29 = 5'd16; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL__PRIM)) == ADDR_SPACE_OTP_CTRL__PRIM) begin - dev_sel_s1n_28 = 5'd16; + dev_sel_s1n_29 = 5'd17; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin - dev_sel_s1n_28 = 5'd17; + dev_sel_s1n_29 = 5'd18; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin - dev_sel_s1n_28 = 5'd18; + dev_sel_s1n_29 = 5'd19; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin - dev_sel_s1n_28 = 5'd19; + dev_sel_s1n_29 = 5'd20; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin - dev_sel_s1n_28 = 5'd20; + dev_sel_s1n_29 = 5'd21; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin - dev_sel_s1n_28 = 5'd21; + dev_sel_s1n_29 = 5'd22; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin - dev_sel_s1n_28 = 5'd22; + dev_sel_s1n_29 = 5'd23; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin - dev_sel_s1n_28 = 5'd23; + dev_sel_s1n_29 = 5'd24; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_ADC_CTRL_AON)) == ADDR_SPACE_ADC_CTRL_AON) begin - dev_sel_s1n_28 = 5'd24; + dev_sel_s1n_29 = 5'd25; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SYSRST_CTRL_AON)) == ADDR_SPACE_SYSRST_CTRL_AON) begin - dev_sel_s1n_28 = 5'd25; + dev_sel_s1n_29 = 5'd26; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_PWM_AON)) == ADDR_SPACE_PWM_AON) begin - dev_sel_s1n_28 = 5'd26; + dev_sel_s1n_29 = 5'd27; end end @@ -325,17 +335,17 @@ end tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (108'h0), - .DRspDepth (108'h0), - .N (27) - ) u_s1n_28 ( + .DReqDepth (112'h0), + .DRspDepth (112'h0), + .N (28) + ) u_s1n_29 ( .clk_i (clk_peri_i), .rst_ni (rst_peri_ni), - .tl_h_i (tl_s1n_28_us_h2d), - .tl_h_o (tl_s1n_28_us_d2h), - .tl_d_o (tl_s1n_28_ds_h2d), - .tl_d_i (tl_s1n_28_ds_d2h), - .dev_select_i (dev_sel_s1n_28) + .tl_h_i (tl_s1n_29_us_h2d), + .tl_h_o (tl_s1n_29_us_d2h), + .tl_d_o (tl_s1n_29_ds_h2d), + .tl_d_i (tl_s1n_29_ds_d2h), + .dev_select_i (dev_sel_s1n_29) ); endmodule diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson index 8d0ab265293666..c66e65365f6404 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson @@ -44,13 +44,13 @@ { name: "NAlerts", desc: "Number of alert channels.", type: "int", - default: "65", + default: "66", local: "true" }, { name: "NLpg", desc: "Number of LPGs.", type: "int", - default: "24", + default: "25", local: "true" }, { name: "NLpgWidth", @@ -66,62 +66,63 @@ type: "logic [NAlerts-1:0][NLpgWidth-1:0]", default: ''' { - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, + 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd24, + 5'd24, 5'd23, 5'd23, 5'd22, - 5'd22, 5'd21, - 5'd20, + 5'd21, 5'd20, 5'd19, 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd18, 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd16, - 5'd12, + 5'd13, + 5'd13, + 5'd15, 5'd12, 5'd14, - 5'd11, - 5'd13, + 5'd14, 5'd13, 5'd12, - 5'd11, - 5'd11, - 5'd11, + 5'd12, + 5'd12, + 5'd12, 5'd11, 5'd10, 5'd9, 5'd8, 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd5, 5'd0, + 5'd5, 5'd4, 5'd3, 5'd2, @@ -219,6 +220,7 @@ 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1 } ''' diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson index af5299672cfe50..19641c4ab4aef0 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson @@ -5,7 +5,7 @@ instance_name: top_earlgrey_alert_handler param_values: { - n_alerts: 65 + n_alerts: 66 esc_cnt_dw: 32 accu_cnt_dw: 16 async_on: @@ -75,9 +75,10 @@ 1'b1 1'b1 1'b1 + 1'b1 ] n_classes: 4 - n_lpg: 24 + n_lpg: 25 lpg_map: [ 5'd0 @@ -89,62 +90,63 @@ 5'd2 5'd3 5'd4 - 5'd0 5'd5 + 5'd0 5'd6 - 5'd6 - 5'd6 - 5'd6 - 5'd6 - 5'd6 - 5'd6 - 5'd6 + 5'd7 + 5'd7 + 5'd7 + 5'd7 + 5'd7 + 5'd7 + 5'd7 5'd7 5'd8 5'd9 5'd10 5'd11 - 5'd11 - 5'd11 - 5'd11 + 5'd12 + 5'd12 + 5'd12 5'd12 5'd13 - 5'd13 - 5'd11 + 5'd14 5'd14 5'd12 - 5'd12 - 5'd16 - 5'd17 - 5'd17 - 5'd17 - 5'd17 + 5'd15 + 5'd13 + 5'd13 5'd17 5'd18 + 5'd18 + 5'd18 + 5'd18 + 5'd18 5'd19 5'd20 - 5'd20 5'd21 - 5'd22 + 5'd21 5'd22 5'd23 5'd23 - 5'd19 - 5'd19 - 5'd19 - 5'd19 - 5'd19 - 5'd19 - 5'd19 - 5'd19 - 5'd19 - 5'd19 - 5'd17 - 5'd17 - 5'd17 - 5'd17 - 5'd17 - 5'd17 + 5'd24 + 5'd24 + 5'd20 + 5'd20 + 5'd20 + 5'd20 + 5'd20 + 5'd20 + 5'd20 + 5'd20 + 5'd20 + 5'd20 + 5'd18 + 5'd18 + 5'd18 + 5'd18 + 5'd18 + 5'd18 ] topname: earlgrey } diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md index 6a6b391c9fd5d7..14a573db82dfde 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md +++ b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md @@ -24,8 +24,8 @@ The parameterization rules are explained in more detail in the architectural des Localparam | Default (Max) | This Core | Description ---------------|-----------------------|----------------|--------------- -`NAlerts` | 8 (248) | 65 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. -`NLpg` | 1 | 24 | Number of unique low-power groups as determined by topgen. +`NAlerts` | 8 (248) | 66 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. +`NLpg` | 1 | 25 | Number of unique low-power groups as determined by topgen. `LpgMap` | {0} | see RTL | Array mapping each alert to a unique low-power group as determined by topgen. `EscCntWidth` | 32 (32) | 32 | Width of the escalation counters in bit. `AccuCntWidth` | 16 (32) | 16 | Width of the alert accumulation counters in bit. diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv index f6c7aa284910c3..cb3249a74a8728 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -7,66 +7,67 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 65; - parameter int NLpg = 24; + parameter int NAlerts = 66; + parameter int NLpg = 25; parameter int NLpgWidth = 5; parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = { - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, - 5'd19, + 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd20, + 5'd24, + 5'd24, 5'd23, 5'd23, 5'd22, - 5'd22, 5'd21, - 5'd20, + 5'd21, 5'd20, 5'd19, 5'd18, + 5'd18, + 5'd18, + 5'd18, + 5'd18, 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd16, - 5'd12, + 5'd13, + 5'd13, + 5'd15, 5'd12, 5'd14, - 5'd11, - 5'd13, + 5'd14, 5'd13, 5'd12, - 5'd11, - 5'd11, - 5'd11, + 5'd12, + 5'd12, + 5'd12, 5'd11, 5'd10, 5'd9, 5'd8, 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd6, - 5'd5, 5'd0, + 5'd5, 5'd4, 5'd3, 5'd2, @@ -144,6 +145,7 @@ package alert_handler_reg_pkg; 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1 }; parameter int N_CLASSES = 4; @@ -617,15 +619,15 @@ package alert_handler_reg_pkg; // Register -> HW type typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [1161:1158] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1157:1154] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [1153:1146] - alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1145:1130] - alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1129:1129] - alert_handler_reg2hw_alert_regwen_mreg_t [64:0] alert_regwen; // [1128:1064] - alert_handler_reg2hw_alert_en_shadowed_mreg_t [64:0] alert_en_shadowed; // [1063:999] - alert_handler_reg2hw_alert_class_shadowed_mreg_t [64:0] alert_class_shadowed; // [998:869] - alert_handler_reg2hw_alert_cause_mreg_t [64:0] alert_cause; // [868:804] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1166:1163] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1162:1159] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1158:1151] + alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1150:1135] + alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1134:1134] + alert_handler_reg2hw_alert_regwen_mreg_t [65:0] alert_regwen; // [1133:1068] + alert_handler_reg2hw_alert_en_shadowed_mreg_t [65:0] alert_en_shadowed; // [1067:1002] + alert_handler_reg2hw_alert_class_shadowed_mreg_t [65:0] alert_class_shadowed; // [1001:870] + alert_handler_reg2hw_alert_cause_mreg_t [65:0] alert_cause; // [869:804] alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797] alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] loc_alert_class_shadowed; // [796:783] @@ -678,8 +680,8 @@ package alert_handler_reg_pkg; // HW -> register type typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [363:356] - alert_handler_hw2reg_alert_cause_mreg_t [64:0] alert_cause; // [355:226] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [365:358] + alert_handler_hw2reg_alert_cause_mreg_t [65:0] alert_cause; // [357:226] alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212] alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] @@ -771,285 +773,289 @@ package alert_handler_reg_pkg; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 11c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 120; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 124; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 128; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 12c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 130; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 134; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 138; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 13c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 140; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 144; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 148; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 14c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 150; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 154; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 158; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 15c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 160; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 164; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 168; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 16c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 170; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 174; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 178; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 17c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 180; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 184; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 188; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 18c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 190; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 194; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 198; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 19c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 200; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 440; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 444; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 448; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 44c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 450; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 454; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 458; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 45c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 460; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 464; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 468; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 46c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 470; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 474; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 478; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 47c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 480; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 484; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 488; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 48c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 490; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 494; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 498; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 49c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 4a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 500; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 504; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 508; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 50c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 510; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 514; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 518; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 51c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 520; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 524; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 528; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 52c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 530; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 534; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 538; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 53c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 540; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 544; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 548; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 54c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 550; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 554; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 558; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 55c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 560; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 564; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 568; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 56c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 570; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 584; // Reset values for hwext registers and their fields parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; @@ -1143,6 +1149,7 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_REGWEN_62, ALERT_HANDLER_ALERT_REGWEN_63, ALERT_HANDLER_ALERT_REGWEN_64, + ALERT_HANDLER_ALERT_REGWEN_65, ALERT_HANDLER_ALERT_EN_SHADOWED_0, ALERT_HANDLER_ALERT_EN_SHADOWED_1, ALERT_HANDLER_ALERT_EN_SHADOWED_2, @@ -1208,6 +1215,7 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_EN_SHADOWED_62, ALERT_HANDLER_ALERT_EN_SHADOWED_63, ALERT_HANDLER_ALERT_EN_SHADOWED_64, + ALERT_HANDLER_ALERT_EN_SHADOWED_65, ALERT_HANDLER_ALERT_CLASS_SHADOWED_0, ALERT_HANDLER_ALERT_CLASS_SHADOWED_1, ALERT_HANDLER_ALERT_CLASS_SHADOWED_2, @@ -1273,6 +1281,7 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CLASS_SHADOWED_62, ALERT_HANDLER_ALERT_CLASS_SHADOWED_63, ALERT_HANDLER_ALERT_CLASS_SHADOWED_64, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_65, ALERT_HANDLER_ALERT_CAUSE_0, ALERT_HANDLER_ALERT_CAUSE_1, ALERT_HANDLER_ALERT_CAUSE_2, @@ -1338,6 +1347,7 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CAUSE_62, ALERT_HANDLER_ALERT_CAUSE_63, ALERT_HANDLER_ALERT_CAUSE_64, + ALERT_HANDLER_ALERT_CAUSE_65, ALERT_HANDLER_LOC_ALERT_REGWEN_0, ALERT_HANDLER_LOC_ALERT_REGWEN_1, ALERT_HANDLER_LOC_ALERT_REGWEN_2, @@ -1425,7 +1435,7 @@ package alert_handler_reg_pkg; } alert_handler_id_e; // Register width information to check illegal writes - parameter logic [3:0] ALERT_HANDLER_PERMIT [350] = '{ + parameter logic [3:0] ALERT_HANDLER_PERMIT [354] = '{ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST @@ -1497,285 +1507,289 @@ package alert_handler_reg_pkg; 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 - 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_7 - 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_8 - 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_9 - 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_10 - 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_11 - 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_12 - 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_13 - 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_14 - 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_15 - 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_16 - 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_17 - 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_18 - 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_19 - 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_20 - 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_21 - 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_22 - 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_23 - 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_24 - 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_25 - 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_26 - 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_27 - 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_28 - 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_29 - 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_30 - 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_31 - 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_32 - 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_33 - 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_34 - 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_35 - 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_36 - 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_37 - 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_38 - 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_39 - 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_40 - 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_41 - 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_42 - 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_43 - 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_44 - 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_45 - 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_46 - 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_47 - 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_48 - 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_49 - 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_50 - 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_51 - 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_52 - 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_53 - 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_54 - 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_55 - 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_56 - 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_57 - 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_58 - 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_59 - 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_60 - 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_61 - 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_62 - 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_63 - 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_64 - 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 - 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 - 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 - 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 - 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 - 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 - 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 - 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 - 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 - 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 - 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 - 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 - 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 - 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 - 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 - 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 - 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 - 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 - 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 - 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 - 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 - 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 - 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 - 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 - 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 - 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 - 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 - 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 - 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 - 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 - 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 - 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 - 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 - 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 - 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 - 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 - 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 - 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 - 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 - 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 - 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 - 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 - 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 - 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 - 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 - 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 - 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 - 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 - 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 - 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 - 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 - 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 - 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 - 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 - 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 - 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 - 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 - 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 - 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_0 - 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_1 - 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_2 - 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_3 - 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_4 - 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_5 - 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_6 - 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_7 - 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_8 - 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_9 - 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_10 - 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_11 - 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_12 - 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_13 - 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_14 - 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_15 - 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_16 - 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_17 - 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_18 - 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_19 - 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_20 - 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_21 - 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_22 - 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_23 - 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_24 - 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_25 - 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_26 - 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_27 - 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_28 - 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_29 - 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_30 - 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_31 - 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_32 - 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_33 - 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_34 - 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_35 - 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_36 - 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_37 - 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_38 - 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_39 - 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_40 - 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_41 - 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_42 - 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_43 - 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_44 - 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_45 - 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_46 - 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_47 - 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_48 - 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_49 - 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_50 - 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_51 - 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_52 - 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_53 - 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_54 - 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_55 - 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_56 - 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_57 - 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_58 - 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_59 - 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_60 - 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_61 - 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_62 - 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_63 - 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_64 - 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_REGWEN_0 - 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_REGWEN_1 - 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_REGWEN_2 - 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_REGWEN_3 - 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_REGWEN_4 - 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_REGWEN_5 - 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_REGWEN_6 - 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CAUSE_0 - 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CAUSE_1 - 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_2 - 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CAUSE_3 - 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CAUSE_4 - 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CAUSE_5 - 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_6 - 4'b 0001, // index[294] ALERT_HANDLER_CLASSA_REGWEN - 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_CTRL_SHADOWED - 4'b 0001, // index[296] ALERT_HANDLER_CLASSA_CLR_REGWEN - 4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CLR_SHADOWED - 4'b 0011, // index[298] ALERT_HANDLER_CLASSA_ACCUM_CNT - 4'b 0011, // index[299] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[301] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[302] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED - 4'b 1111, // index[303] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED - 4'b 1111, // index[304] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED - 4'b 1111, // index[305] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED - 4'b 1111, // index[306] ALERT_HANDLER_CLASSA_ESC_CNT - 4'b 0001, // index[307] ALERT_HANDLER_CLASSA_STATE - 4'b 0001, // index[308] ALERT_HANDLER_CLASSB_REGWEN - 4'b 0011, // index[309] ALERT_HANDLER_CLASSB_CTRL_SHADOWED - 4'b 0001, // index[310] ALERT_HANDLER_CLASSB_CLR_REGWEN - 4'b 0001, // index[311] ALERT_HANDLER_CLASSB_CLR_SHADOWED - 4'b 0011, // index[312] ALERT_HANDLER_CLASSB_ACCUM_CNT - 4'b 0011, // index[313] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[315] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[316] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED - 4'b 1111, // index[317] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED - 4'b 1111, // index[318] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED - 4'b 1111, // index[319] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED - 4'b 1111, // index[320] ALERT_HANDLER_CLASSB_ESC_CNT - 4'b 0001, // index[321] ALERT_HANDLER_CLASSB_STATE - 4'b 0001, // index[322] ALERT_HANDLER_CLASSC_REGWEN - 4'b 0011, // index[323] ALERT_HANDLER_CLASSC_CTRL_SHADOWED - 4'b 0001, // index[324] ALERT_HANDLER_CLASSC_CLR_REGWEN - 4'b 0001, // index[325] ALERT_HANDLER_CLASSC_CLR_SHADOWED - 4'b 0011, // index[326] ALERT_HANDLER_CLASSC_ACCUM_CNT - 4'b 0011, // index[327] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[328] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[329] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED - 4'b 1111, // index[331] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED - 4'b 1111, // index[332] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED - 4'b 1111, // index[333] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED - 4'b 1111, // index[334] ALERT_HANDLER_CLASSC_ESC_CNT - 4'b 0001, // index[335] ALERT_HANDLER_CLASSC_STATE - 4'b 0001, // index[336] ALERT_HANDLER_CLASSD_REGWEN - 4'b 0011, // index[337] ALERT_HANDLER_CLASSD_CTRL_SHADOWED - 4'b 0001, // index[338] ALERT_HANDLER_CLASSD_CLR_REGWEN - 4'b 0001, // index[339] ALERT_HANDLER_CLASSD_CLR_SHADOWED - 4'b 0011, // index[340] ALERT_HANDLER_CLASSD_ACCUM_CNT - 4'b 0011, // index[341] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[342] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[343] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED - 4'b 1111, // index[345] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED - 4'b 1111, // index[346] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED - 4'b 1111, // index[347] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED - 4'b 1111, // index[348] ALERT_HANDLER_CLASSD_ESC_CNT - 4'b 0001 // index[349] ALERT_HANDLER_CLASSD_STATE + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_7 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_8 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_9 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_10 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_11 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_12 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_13 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_14 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_15 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_16 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_17 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_18 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_19 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_20 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_21 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_22 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_23 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_24 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_25 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_26 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_27 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_28 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_29 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_30 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_31 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_32 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_33 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_34 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_35 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_36 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_37 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_38 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_39 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_40 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_41 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_42 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_43 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_44 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_45 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_46 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_47 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_48 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_49 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_50 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_51 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_52 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_53 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_54 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_55 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_56 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_57 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_58 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_59 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_60 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_61 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_62 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_63 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_SHADOWED_64 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_SHADOWED_65 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_65 + 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[294] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[295] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[296] ALERT_HANDLER_LOC_ALERT_CAUSE_5 + 4'b 0001, // index[297] ALERT_HANDLER_LOC_ALERT_CAUSE_6 + 4'b 0001, // index[298] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[299] ALERT_HANDLER_CLASSA_CTRL_SHADOWED + 4'b 0001, // index[300] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[301] ALERT_HANDLER_CLASSA_CLR_SHADOWED + 4'b 0011, // index[302] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[303] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[304] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[305] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[306] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED + 4'b 1111, // index[307] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED + 4'b 1111, // index[308] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED + 4'b 1111, // index[309] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED + 4'b 1111, // index[310] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[311] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[312] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[313] ALERT_HANDLER_CLASSB_CTRL_SHADOWED + 4'b 0001, // index[314] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[315] ALERT_HANDLER_CLASSB_CLR_SHADOWED + 4'b 0011, // index[316] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[317] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[318] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[319] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[320] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED + 4'b 1111, // index[321] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED + 4'b 1111, // index[322] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED + 4'b 1111, // index[323] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED + 4'b 1111, // index[324] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[325] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[326] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[327] ALERT_HANDLER_CLASSC_CTRL_SHADOWED + 4'b 0001, // index[328] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[329] ALERT_HANDLER_CLASSC_CLR_SHADOWED + 4'b 0011, // index[330] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[331] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[332] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[333] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[334] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED + 4'b 1111, // index[335] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED + 4'b 1111, // index[336] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED + 4'b 1111, // index[337] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED + 4'b 1111, // index[338] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[339] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[340] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[341] ALERT_HANDLER_CLASSD_CTRL_SHADOWED + 4'b 0001, // index[342] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[343] ALERT_HANDLER_CLASSD_CLR_SHADOWED + 4'b 0011, // index[344] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[345] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[346] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[347] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[348] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED + 4'b 1111, // index[349] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED + 4'b 1111, // index[350] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED + 4'b 1111, // index[351] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED + 4'b 1111, // index[352] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[353] ALERT_HANDLER_CLASSD_STATE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv index bf7a812533f6cb..484c4960676006 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv @@ -56,9 +56,9 @@ module alert_handler_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [349:0] reg_we_check; + logic [353:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(350) + .OneHotWidth(354) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -358,6 +358,9 @@ module alert_handler_reg_top ( logic alert_regwen_64_we; logic alert_regwen_64_qs; logic alert_regwen_64_wd; + logic alert_regwen_65_we; + logic alert_regwen_65_qs; + logic alert_regwen_65_wd; logic alert_en_shadowed_0_re; logic alert_en_shadowed_0_we; logic alert_en_shadowed_0_qs; @@ -748,6 +751,12 @@ module alert_handler_reg_top ( logic alert_en_shadowed_64_wd; logic alert_en_shadowed_64_storage_err; logic alert_en_shadowed_64_update_err; + logic alert_en_shadowed_65_re; + logic alert_en_shadowed_65_we; + logic alert_en_shadowed_65_qs; + logic alert_en_shadowed_65_wd; + logic alert_en_shadowed_65_storage_err; + logic alert_en_shadowed_65_update_err; logic alert_class_shadowed_0_re; logic alert_class_shadowed_0_we; logic [1:0] alert_class_shadowed_0_qs; @@ -1138,6 +1147,12 @@ module alert_handler_reg_top ( logic [1:0] alert_class_shadowed_64_wd; logic alert_class_shadowed_64_storage_err; logic alert_class_shadowed_64_update_err; + logic alert_class_shadowed_65_re; + logic alert_class_shadowed_65_we; + logic [1:0] alert_class_shadowed_65_qs; + logic [1:0] alert_class_shadowed_65_wd; + logic alert_class_shadowed_65_storage_err; + logic alert_class_shadowed_65_update_err; logic alert_cause_0_we; logic alert_cause_0_qs; logic alert_cause_0_wd; @@ -1333,6 +1348,9 @@ module alert_handler_reg_top ( logic alert_cause_64_we; logic alert_cause_64_qs; logic alert_cause_64_wd; + logic alert_cause_65_we; + logic alert_cause_65_qs; + logic alert_cause_65_wd; logic loc_alert_regwen_0_we; logic loc_alert_regwen_0_qs; logic loc_alert_regwen_0_wd; @@ -4151,6 +4169,35 @@ module alert_handler_reg_top ( ); + // Subregister 65 of Multireg alert_regwen + // R[alert_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_65_we), + .wd (alert_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[65].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_65_qs) + ); + + // Subregister 0 of Multireg alert_en_shadowed // R[alert_en_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -6816,6 +6863,47 @@ module alert_handler_reg_top ( ); + // Subregister 65 of Multireg alert_en_shadowed + // R[alert_en_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_65_gated_we; + assign alert_en_shadowed_65_gated_we = alert_en_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_65_re), + .we (alert_en_shadowed_65_gated_we), + .wd (alert_en_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_65_update_err), + .err_storage (alert_en_shadowed_65_storage_err) + ); + + // Subregister 0 of Multireg alert_class_shadowed // R[alert_class_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -9481,6 +9569,47 @@ module alert_handler_reg_top ( ); + // Subregister 65 of Multireg alert_class_shadowed + // R[alert_class_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_65_gated_we; + assign alert_class_shadowed_65_gated_we = alert_class_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_65_re), + .we (alert_class_shadowed_65_gated_we), + .wd (alert_class_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_65_update_err), + .err_storage (alert_class_shadowed_65_storage_err) + ); + + // Subregister 0 of Multireg alert_cause // R[alert_cause_0]: V(False) prim_subreg #( @@ -11366,6 +11495,35 @@ module alert_handler_reg_top ( ); + // Subregister 65 of Multireg alert_cause + // R[alert_cause_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_65_we), + .wd (alert_cause_65_wd), + + // from internal hardware + .de (hw2reg.alert_cause[65].de), + .d (hw2reg.alert_cause[65].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[65].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_65_qs) + ); + + // Subregister 0 of Multireg loc_alert_regwen // R[loc_alert_regwen_0]: V(False) prim_subreg #( @@ -15562,7 +15720,7 @@ module alert_handler_reg_top ( - logic [349:0] addr_hit; + logic [353:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); @@ -15636,285 +15794,289 @@ module alert_handler_reg_top ( addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET); addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET); addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); - addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); - addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); - addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); - addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); - addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); - addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); - addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); - addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); - addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); - addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); - addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); - addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); - addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); - addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); - addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); - addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); - addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); - addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); - addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); - addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); - addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); - addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); - addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); - addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); - addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); - addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); - addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); - addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); - addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); - addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); - addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); - addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); - addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); - addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); - addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); - addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); - addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); - addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); - addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); - addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); - addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); - addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); - addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); - addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); - addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); - addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); - addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); - addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); - addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); - addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); - addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); - addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); - addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); - addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); - addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); - addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); - addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); - addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET); - addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); - addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); - addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); - addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); - addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); - addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); - addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); - addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); - addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); - addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); - addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); - addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); - addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); - addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); - addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); - addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); - addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); - addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); - addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); - addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); - addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); - addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); - addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); - addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); - addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); - addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); - addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); - addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); - addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); - addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); - addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); - addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); - addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); - addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); - addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); - addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); - addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); - addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); - addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); - addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); - addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); - addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); - addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); - addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); - addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); - addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); - addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); - addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); - addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); - addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); - addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); - addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); - addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); - addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); - addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); - addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); - addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); - addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET); - addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); - addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); - addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); - addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); - addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); - addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); - addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); - addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); - addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); - addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); - addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); - addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); - addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); - addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); - addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); - addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); - addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); - addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); - addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); - addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); - addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); - addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); - addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); - addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); - addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); - addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); - addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); - addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); - addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); - addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); - addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); - addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); - addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); - addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); - addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); - addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); - addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); - addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); - addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); - addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); - addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); - addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); - addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); - addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); - addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); - addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); - addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); - addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); - addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); - addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); - addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); - addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); - addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); - addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); - addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); - addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); - addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); - addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); - addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); - addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); - addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); - addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); - addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); - addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); - addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); - addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); - addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); - addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); - addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); - addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); - addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); - addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); - addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); - addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); - addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); - addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); - addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); - addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); - addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); - addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); - addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); - addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); - addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); - addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); - addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); - addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); - addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); - addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); - addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); - addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); - addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); - addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); - addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); - addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); - addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); - addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); - addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); - addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); - addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); - addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); - addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); - addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); - addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); - addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); - addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); - addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); - addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[350] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[351] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[352] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[353] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -16271,7 +16433,11 @@ module alert_handler_reg_top ( (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) | (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) | (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) | - (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))))); + (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))) | + (addr_hit[350] & (|(ALERT_HANDLER_PERMIT[350] & ~reg_be))) | + (addr_hit[351] & (|(ALERT_HANDLER_PERMIT[351] & ~reg_be))) | + (addr_hit[352] & (|(ALERT_HANDLER_PERMIT[352] & ~reg_be))) | + (addr_hit[353] & (|(ALERT_HANDLER_PERMIT[353] & ~reg_be))))); end // Generate write-enables @@ -16508,824 +16674,838 @@ module alert_handler_reg_top ( assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error; assign alert_regwen_64_wd = reg_wdata[0]; - assign alert_en_shadowed_0_re = addr_hit[71] & reg_re & !reg_error; - assign alert_en_shadowed_0_we = addr_hit[71] & reg_we & !reg_error; + assign alert_regwen_65_we = addr_hit[71] & reg_we & !reg_error; + + assign alert_regwen_65_wd = reg_wdata[0]; + assign alert_en_shadowed_0_re = addr_hit[72] & reg_re & !reg_error; + assign alert_en_shadowed_0_we = addr_hit[72] & reg_we & !reg_error; assign alert_en_shadowed_0_wd = reg_wdata[0]; - assign alert_en_shadowed_1_re = addr_hit[72] & reg_re & !reg_error; - assign alert_en_shadowed_1_we = addr_hit[72] & reg_we & !reg_error; + assign alert_en_shadowed_1_re = addr_hit[73] & reg_re & !reg_error; + assign alert_en_shadowed_1_we = addr_hit[73] & reg_we & !reg_error; assign alert_en_shadowed_1_wd = reg_wdata[0]; - assign alert_en_shadowed_2_re = addr_hit[73] & reg_re & !reg_error; - assign alert_en_shadowed_2_we = addr_hit[73] & reg_we & !reg_error; + assign alert_en_shadowed_2_re = addr_hit[74] & reg_re & !reg_error; + assign alert_en_shadowed_2_we = addr_hit[74] & reg_we & !reg_error; assign alert_en_shadowed_2_wd = reg_wdata[0]; - assign alert_en_shadowed_3_re = addr_hit[74] & reg_re & !reg_error; - assign alert_en_shadowed_3_we = addr_hit[74] & reg_we & !reg_error; + assign alert_en_shadowed_3_re = addr_hit[75] & reg_re & !reg_error; + assign alert_en_shadowed_3_we = addr_hit[75] & reg_we & !reg_error; assign alert_en_shadowed_3_wd = reg_wdata[0]; - assign alert_en_shadowed_4_re = addr_hit[75] & reg_re & !reg_error; - assign alert_en_shadowed_4_we = addr_hit[75] & reg_we & !reg_error; + assign alert_en_shadowed_4_re = addr_hit[76] & reg_re & !reg_error; + assign alert_en_shadowed_4_we = addr_hit[76] & reg_we & !reg_error; assign alert_en_shadowed_4_wd = reg_wdata[0]; - assign alert_en_shadowed_5_re = addr_hit[76] & reg_re & !reg_error; - assign alert_en_shadowed_5_we = addr_hit[76] & reg_we & !reg_error; + assign alert_en_shadowed_5_re = addr_hit[77] & reg_re & !reg_error; + assign alert_en_shadowed_5_we = addr_hit[77] & reg_we & !reg_error; assign alert_en_shadowed_5_wd = reg_wdata[0]; - assign alert_en_shadowed_6_re = addr_hit[77] & reg_re & !reg_error; - assign alert_en_shadowed_6_we = addr_hit[77] & reg_we & !reg_error; + assign alert_en_shadowed_6_re = addr_hit[78] & reg_re & !reg_error; + assign alert_en_shadowed_6_we = addr_hit[78] & reg_we & !reg_error; assign alert_en_shadowed_6_wd = reg_wdata[0]; - assign alert_en_shadowed_7_re = addr_hit[78] & reg_re & !reg_error; - assign alert_en_shadowed_7_we = addr_hit[78] & reg_we & !reg_error; + assign alert_en_shadowed_7_re = addr_hit[79] & reg_re & !reg_error; + assign alert_en_shadowed_7_we = addr_hit[79] & reg_we & !reg_error; assign alert_en_shadowed_7_wd = reg_wdata[0]; - assign alert_en_shadowed_8_re = addr_hit[79] & reg_re & !reg_error; - assign alert_en_shadowed_8_we = addr_hit[79] & reg_we & !reg_error; + assign alert_en_shadowed_8_re = addr_hit[80] & reg_re & !reg_error; + assign alert_en_shadowed_8_we = addr_hit[80] & reg_we & !reg_error; assign alert_en_shadowed_8_wd = reg_wdata[0]; - assign alert_en_shadowed_9_re = addr_hit[80] & reg_re & !reg_error; - assign alert_en_shadowed_9_we = addr_hit[80] & reg_we & !reg_error; + assign alert_en_shadowed_9_re = addr_hit[81] & reg_re & !reg_error; + assign alert_en_shadowed_9_we = addr_hit[81] & reg_we & !reg_error; assign alert_en_shadowed_9_wd = reg_wdata[0]; - assign alert_en_shadowed_10_re = addr_hit[81] & reg_re & !reg_error; - assign alert_en_shadowed_10_we = addr_hit[81] & reg_we & !reg_error; + assign alert_en_shadowed_10_re = addr_hit[82] & reg_re & !reg_error; + assign alert_en_shadowed_10_we = addr_hit[82] & reg_we & !reg_error; assign alert_en_shadowed_10_wd = reg_wdata[0]; - assign alert_en_shadowed_11_re = addr_hit[82] & reg_re & !reg_error; - assign alert_en_shadowed_11_we = addr_hit[82] & reg_we & !reg_error; + assign alert_en_shadowed_11_re = addr_hit[83] & reg_re & !reg_error; + assign alert_en_shadowed_11_we = addr_hit[83] & reg_we & !reg_error; assign alert_en_shadowed_11_wd = reg_wdata[0]; - assign alert_en_shadowed_12_re = addr_hit[83] & reg_re & !reg_error; - assign alert_en_shadowed_12_we = addr_hit[83] & reg_we & !reg_error; + assign alert_en_shadowed_12_re = addr_hit[84] & reg_re & !reg_error; + assign alert_en_shadowed_12_we = addr_hit[84] & reg_we & !reg_error; assign alert_en_shadowed_12_wd = reg_wdata[0]; - assign alert_en_shadowed_13_re = addr_hit[84] & reg_re & !reg_error; - assign alert_en_shadowed_13_we = addr_hit[84] & reg_we & !reg_error; + assign alert_en_shadowed_13_re = addr_hit[85] & reg_re & !reg_error; + assign alert_en_shadowed_13_we = addr_hit[85] & reg_we & !reg_error; assign alert_en_shadowed_13_wd = reg_wdata[0]; - assign alert_en_shadowed_14_re = addr_hit[85] & reg_re & !reg_error; - assign alert_en_shadowed_14_we = addr_hit[85] & reg_we & !reg_error; + assign alert_en_shadowed_14_re = addr_hit[86] & reg_re & !reg_error; + assign alert_en_shadowed_14_we = addr_hit[86] & reg_we & !reg_error; assign alert_en_shadowed_14_wd = reg_wdata[0]; - assign alert_en_shadowed_15_re = addr_hit[86] & reg_re & !reg_error; - assign alert_en_shadowed_15_we = addr_hit[86] & reg_we & !reg_error; + assign alert_en_shadowed_15_re = addr_hit[87] & reg_re & !reg_error; + assign alert_en_shadowed_15_we = addr_hit[87] & reg_we & !reg_error; assign alert_en_shadowed_15_wd = reg_wdata[0]; - assign alert_en_shadowed_16_re = addr_hit[87] & reg_re & !reg_error; - assign alert_en_shadowed_16_we = addr_hit[87] & reg_we & !reg_error; + assign alert_en_shadowed_16_re = addr_hit[88] & reg_re & !reg_error; + assign alert_en_shadowed_16_we = addr_hit[88] & reg_we & !reg_error; assign alert_en_shadowed_16_wd = reg_wdata[0]; - assign alert_en_shadowed_17_re = addr_hit[88] & reg_re & !reg_error; - assign alert_en_shadowed_17_we = addr_hit[88] & reg_we & !reg_error; + assign alert_en_shadowed_17_re = addr_hit[89] & reg_re & !reg_error; + assign alert_en_shadowed_17_we = addr_hit[89] & reg_we & !reg_error; assign alert_en_shadowed_17_wd = reg_wdata[0]; - assign alert_en_shadowed_18_re = addr_hit[89] & reg_re & !reg_error; - assign alert_en_shadowed_18_we = addr_hit[89] & reg_we & !reg_error; + assign alert_en_shadowed_18_re = addr_hit[90] & reg_re & !reg_error; + assign alert_en_shadowed_18_we = addr_hit[90] & reg_we & !reg_error; assign alert_en_shadowed_18_wd = reg_wdata[0]; - assign alert_en_shadowed_19_re = addr_hit[90] & reg_re & !reg_error; - assign alert_en_shadowed_19_we = addr_hit[90] & reg_we & !reg_error; + assign alert_en_shadowed_19_re = addr_hit[91] & reg_re & !reg_error; + assign alert_en_shadowed_19_we = addr_hit[91] & reg_we & !reg_error; assign alert_en_shadowed_19_wd = reg_wdata[0]; - assign alert_en_shadowed_20_re = addr_hit[91] & reg_re & !reg_error; - assign alert_en_shadowed_20_we = addr_hit[91] & reg_we & !reg_error; + assign alert_en_shadowed_20_re = addr_hit[92] & reg_re & !reg_error; + assign alert_en_shadowed_20_we = addr_hit[92] & reg_we & !reg_error; assign alert_en_shadowed_20_wd = reg_wdata[0]; - assign alert_en_shadowed_21_re = addr_hit[92] & reg_re & !reg_error; - assign alert_en_shadowed_21_we = addr_hit[92] & reg_we & !reg_error; + assign alert_en_shadowed_21_re = addr_hit[93] & reg_re & !reg_error; + assign alert_en_shadowed_21_we = addr_hit[93] & reg_we & !reg_error; assign alert_en_shadowed_21_wd = reg_wdata[0]; - assign alert_en_shadowed_22_re = addr_hit[93] & reg_re & !reg_error; - assign alert_en_shadowed_22_we = addr_hit[93] & reg_we & !reg_error; + assign alert_en_shadowed_22_re = addr_hit[94] & reg_re & !reg_error; + assign alert_en_shadowed_22_we = addr_hit[94] & reg_we & !reg_error; assign alert_en_shadowed_22_wd = reg_wdata[0]; - assign alert_en_shadowed_23_re = addr_hit[94] & reg_re & !reg_error; - assign alert_en_shadowed_23_we = addr_hit[94] & reg_we & !reg_error; + assign alert_en_shadowed_23_re = addr_hit[95] & reg_re & !reg_error; + assign alert_en_shadowed_23_we = addr_hit[95] & reg_we & !reg_error; assign alert_en_shadowed_23_wd = reg_wdata[0]; - assign alert_en_shadowed_24_re = addr_hit[95] & reg_re & !reg_error; - assign alert_en_shadowed_24_we = addr_hit[95] & reg_we & !reg_error; + assign alert_en_shadowed_24_re = addr_hit[96] & reg_re & !reg_error; + assign alert_en_shadowed_24_we = addr_hit[96] & reg_we & !reg_error; assign alert_en_shadowed_24_wd = reg_wdata[0]; - assign alert_en_shadowed_25_re = addr_hit[96] & reg_re & !reg_error; - assign alert_en_shadowed_25_we = addr_hit[96] & reg_we & !reg_error; + assign alert_en_shadowed_25_re = addr_hit[97] & reg_re & !reg_error; + assign alert_en_shadowed_25_we = addr_hit[97] & reg_we & !reg_error; assign alert_en_shadowed_25_wd = reg_wdata[0]; - assign alert_en_shadowed_26_re = addr_hit[97] & reg_re & !reg_error; - assign alert_en_shadowed_26_we = addr_hit[97] & reg_we & !reg_error; + assign alert_en_shadowed_26_re = addr_hit[98] & reg_re & !reg_error; + assign alert_en_shadowed_26_we = addr_hit[98] & reg_we & !reg_error; assign alert_en_shadowed_26_wd = reg_wdata[0]; - assign alert_en_shadowed_27_re = addr_hit[98] & reg_re & !reg_error; - assign alert_en_shadowed_27_we = addr_hit[98] & reg_we & !reg_error; + assign alert_en_shadowed_27_re = addr_hit[99] & reg_re & !reg_error; + assign alert_en_shadowed_27_we = addr_hit[99] & reg_we & !reg_error; assign alert_en_shadowed_27_wd = reg_wdata[0]; - assign alert_en_shadowed_28_re = addr_hit[99] & reg_re & !reg_error; - assign alert_en_shadowed_28_we = addr_hit[99] & reg_we & !reg_error; + assign alert_en_shadowed_28_re = addr_hit[100] & reg_re & !reg_error; + assign alert_en_shadowed_28_we = addr_hit[100] & reg_we & !reg_error; assign alert_en_shadowed_28_wd = reg_wdata[0]; - assign alert_en_shadowed_29_re = addr_hit[100] & reg_re & !reg_error; - assign alert_en_shadowed_29_we = addr_hit[100] & reg_we & !reg_error; + assign alert_en_shadowed_29_re = addr_hit[101] & reg_re & !reg_error; + assign alert_en_shadowed_29_we = addr_hit[101] & reg_we & !reg_error; assign alert_en_shadowed_29_wd = reg_wdata[0]; - assign alert_en_shadowed_30_re = addr_hit[101] & reg_re & !reg_error; - assign alert_en_shadowed_30_we = addr_hit[101] & reg_we & !reg_error; + assign alert_en_shadowed_30_re = addr_hit[102] & reg_re & !reg_error; + assign alert_en_shadowed_30_we = addr_hit[102] & reg_we & !reg_error; assign alert_en_shadowed_30_wd = reg_wdata[0]; - assign alert_en_shadowed_31_re = addr_hit[102] & reg_re & !reg_error; - assign alert_en_shadowed_31_we = addr_hit[102] & reg_we & !reg_error; + assign alert_en_shadowed_31_re = addr_hit[103] & reg_re & !reg_error; + assign alert_en_shadowed_31_we = addr_hit[103] & reg_we & !reg_error; assign alert_en_shadowed_31_wd = reg_wdata[0]; - assign alert_en_shadowed_32_re = addr_hit[103] & reg_re & !reg_error; - assign alert_en_shadowed_32_we = addr_hit[103] & reg_we & !reg_error; + assign alert_en_shadowed_32_re = addr_hit[104] & reg_re & !reg_error; + assign alert_en_shadowed_32_we = addr_hit[104] & reg_we & !reg_error; assign alert_en_shadowed_32_wd = reg_wdata[0]; - assign alert_en_shadowed_33_re = addr_hit[104] & reg_re & !reg_error; - assign alert_en_shadowed_33_we = addr_hit[104] & reg_we & !reg_error; + assign alert_en_shadowed_33_re = addr_hit[105] & reg_re & !reg_error; + assign alert_en_shadowed_33_we = addr_hit[105] & reg_we & !reg_error; assign alert_en_shadowed_33_wd = reg_wdata[0]; - assign alert_en_shadowed_34_re = addr_hit[105] & reg_re & !reg_error; - assign alert_en_shadowed_34_we = addr_hit[105] & reg_we & !reg_error; + assign alert_en_shadowed_34_re = addr_hit[106] & reg_re & !reg_error; + assign alert_en_shadowed_34_we = addr_hit[106] & reg_we & !reg_error; assign alert_en_shadowed_34_wd = reg_wdata[0]; - assign alert_en_shadowed_35_re = addr_hit[106] & reg_re & !reg_error; - assign alert_en_shadowed_35_we = addr_hit[106] & reg_we & !reg_error; + assign alert_en_shadowed_35_re = addr_hit[107] & reg_re & !reg_error; + assign alert_en_shadowed_35_we = addr_hit[107] & reg_we & !reg_error; assign alert_en_shadowed_35_wd = reg_wdata[0]; - assign alert_en_shadowed_36_re = addr_hit[107] & reg_re & !reg_error; - assign alert_en_shadowed_36_we = addr_hit[107] & reg_we & !reg_error; + assign alert_en_shadowed_36_re = addr_hit[108] & reg_re & !reg_error; + assign alert_en_shadowed_36_we = addr_hit[108] & reg_we & !reg_error; assign alert_en_shadowed_36_wd = reg_wdata[0]; - assign alert_en_shadowed_37_re = addr_hit[108] & reg_re & !reg_error; - assign alert_en_shadowed_37_we = addr_hit[108] & reg_we & !reg_error; + assign alert_en_shadowed_37_re = addr_hit[109] & reg_re & !reg_error; + assign alert_en_shadowed_37_we = addr_hit[109] & reg_we & !reg_error; assign alert_en_shadowed_37_wd = reg_wdata[0]; - assign alert_en_shadowed_38_re = addr_hit[109] & reg_re & !reg_error; - assign alert_en_shadowed_38_we = addr_hit[109] & reg_we & !reg_error; + assign alert_en_shadowed_38_re = addr_hit[110] & reg_re & !reg_error; + assign alert_en_shadowed_38_we = addr_hit[110] & reg_we & !reg_error; assign alert_en_shadowed_38_wd = reg_wdata[0]; - assign alert_en_shadowed_39_re = addr_hit[110] & reg_re & !reg_error; - assign alert_en_shadowed_39_we = addr_hit[110] & reg_we & !reg_error; + assign alert_en_shadowed_39_re = addr_hit[111] & reg_re & !reg_error; + assign alert_en_shadowed_39_we = addr_hit[111] & reg_we & !reg_error; assign alert_en_shadowed_39_wd = reg_wdata[0]; - assign alert_en_shadowed_40_re = addr_hit[111] & reg_re & !reg_error; - assign alert_en_shadowed_40_we = addr_hit[111] & reg_we & !reg_error; + assign alert_en_shadowed_40_re = addr_hit[112] & reg_re & !reg_error; + assign alert_en_shadowed_40_we = addr_hit[112] & reg_we & !reg_error; assign alert_en_shadowed_40_wd = reg_wdata[0]; - assign alert_en_shadowed_41_re = addr_hit[112] & reg_re & !reg_error; - assign alert_en_shadowed_41_we = addr_hit[112] & reg_we & !reg_error; + assign alert_en_shadowed_41_re = addr_hit[113] & reg_re & !reg_error; + assign alert_en_shadowed_41_we = addr_hit[113] & reg_we & !reg_error; assign alert_en_shadowed_41_wd = reg_wdata[0]; - assign alert_en_shadowed_42_re = addr_hit[113] & reg_re & !reg_error; - assign alert_en_shadowed_42_we = addr_hit[113] & reg_we & !reg_error; + assign alert_en_shadowed_42_re = addr_hit[114] & reg_re & !reg_error; + assign alert_en_shadowed_42_we = addr_hit[114] & reg_we & !reg_error; assign alert_en_shadowed_42_wd = reg_wdata[0]; - assign alert_en_shadowed_43_re = addr_hit[114] & reg_re & !reg_error; - assign alert_en_shadowed_43_we = addr_hit[114] & reg_we & !reg_error; + assign alert_en_shadowed_43_re = addr_hit[115] & reg_re & !reg_error; + assign alert_en_shadowed_43_we = addr_hit[115] & reg_we & !reg_error; assign alert_en_shadowed_43_wd = reg_wdata[0]; - assign alert_en_shadowed_44_re = addr_hit[115] & reg_re & !reg_error; - assign alert_en_shadowed_44_we = addr_hit[115] & reg_we & !reg_error; + assign alert_en_shadowed_44_re = addr_hit[116] & reg_re & !reg_error; + assign alert_en_shadowed_44_we = addr_hit[116] & reg_we & !reg_error; assign alert_en_shadowed_44_wd = reg_wdata[0]; - assign alert_en_shadowed_45_re = addr_hit[116] & reg_re & !reg_error; - assign alert_en_shadowed_45_we = addr_hit[116] & reg_we & !reg_error; + assign alert_en_shadowed_45_re = addr_hit[117] & reg_re & !reg_error; + assign alert_en_shadowed_45_we = addr_hit[117] & reg_we & !reg_error; assign alert_en_shadowed_45_wd = reg_wdata[0]; - assign alert_en_shadowed_46_re = addr_hit[117] & reg_re & !reg_error; - assign alert_en_shadowed_46_we = addr_hit[117] & reg_we & !reg_error; + assign alert_en_shadowed_46_re = addr_hit[118] & reg_re & !reg_error; + assign alert_en_shadowed_46_we = addr_hit[118] & reg_we & !reg_error; assign alert_en_shadowed_46_wd = reg_wdata[0]; - assign alert_en_shadowed_47_re = addr_hit[118] & reg_re & !reg_error; - assign alert_en_shadowed_47_we = addr_hit[118] & reg_we & !reg_error; + assign alert_en_shadowed_47_re = addr_hit[119] & reg_re & !reg_error; + assign alert_en_shadowed_47_we = addr_hit[119] & reg_we & !reg_error; assign alert_en_shadowed_47_wd = reg_wdata[0]; - assign alert_en_shadowed_48_re = addr_hit[119] & reg_re & !reg_error; - assign alert_en_shadowed_48_we = addr_hit[119] & reg_we & !reg_error; + assign alert_en_shadowed_48_re = addr_hit[120] & reg_re & !reg_error; + assign alert_en_shadowed_48_we = addr_hit[120] & reg_we & !reg_error; assign alert_en_shadowed_48_wd = reg_wdata[0]; - assign alert_en_shadowed_49_re = addr_hit[120] & reg_re & !reg_error; - assign alert_en_shadowed_49_we = addr_hit[120] & reg_we & !reg_error; + assign alert_en_shadowed_49_re = addr_hit[121] & reg_re & !reg_error; + assign alert_en_shadowed_49_we = addr_hit[121] & reg_we & !reg_error; assign alert_en_shadowed_49_wd = reg_wdata[0]; - assign alert_en_shadowed_50_re = addr_hit[121] & reg_re & !reg_error; - assign alert_en_shadowed_50_we = addr_hit[121] & reg_we & !reg_error; + assign alert_en_shadowed_50_re = addr_hit[122] & reg_re & !reg_error; + assign alert_en_shadowed_50_we = addr_hit[122] & reg_we & !reg_error; assign alert_en_shadowed_50_wd = reg_wdata[0]; - assign alert_en_shadowed_51_re = addr_hit[122] & reg_re & !reg_error; - assign alert_en_shadowed_51_we = addr_hit[122] & reg_we & !reg_error; + assign alert_en_shadowed_51_re = addr_hit[123] & reg_re & !reg_error; + assign alert_en_shadowed_51_we = addr_hit[123] & reg_we & !reg_error; assign alert_en_shadowed_51_wd = reg_wdata[0]; - assign alert_en_shadowed_52_re = addr_hit[123] & reg_re & !reg_error; - assign alert_en_shadowed_52_we = addr_hit[123] & reg_we & !reg_error; + assign alert_en_shadowed_52_re = addr_hit[124] & reg_re & !reg_error; + assign alert_en_shadowed_52_we = addr_hit[124] & reg_we & !reg_error; assign alert_en_shadowed_52_wd = reg_wdata[0]; - assign alert_en_shadowed_53_re = addr_hit[124] & reg_re & !reg_error; - assign alert_en_shadowed_53_we = addr_hit[124] & reg_we & !reg_error; + assign alert_en_shadowed_53_re = addr_hit[125] & reg_re & !reg_error; + assign alert_en_shadowed_53_we = addr_hit[125] & reg_we & !reg_error; assign alert_en_shadowed_53_wd = reg_wdata[0]; - assign alert_en_shadowed_54_re = addr_hit[125] & reg_re & !reg_error; - assign alert_en_shadowed_54_we = addr_hit[125] & reg_we & !reg_error; + assign alert_en_shadowed_54_re = addr_hit[126] & reg_re & !reg_error; + assign alert_en_shadowed_54_we = addr_hit[126] & reg_we & !reg_error; assign alert_en_shadowed_54_wd = reg_wdata[0]; - assign alert_en_shadowed_55_re = addr_hit[126] & reg_re & !reg_error; - assign alert_en_shadowed_55_we = addr_hit[126] & reg_we & !reg_error; + assign alert_en_shadowed_55_re = addr_hit[127] & reg_re & !reg_error; + assign alert_en_shadowed_55_we = addr_hit[127] & reg_we & !reg_error; assign alert_en_shadowed_55_wd = reg_wdata[0]; - assign alert_en_shadowed_56_re = addr_hit[127] & reg_re & !reg_error; - assign alert_en_shadowed_56_we = addr_hit[127] & reg_we & !reg_error; + assign alert_en_shadowed_56_re = addr_hit[128] & reg_re & !reg_error; + assign alert_en_shadowed_56_we = addr_hit[128] & reg_we & !reg_error; assign alert_en_shadowed_56_wd = reg_wdata[0]; - assign alert_en_shadowed_57_re = addr_hit[128] & reg_re & !reg_error; - assign alert_en_shadowed_57_we = addr_hit[128] & reg_we & !reg_error; + assign alert_en_shadowed_57_re = addr_hit[129] & reg_re & !reg_error; + assign alert_en_shadowed_57_we = addr_hit[129] & reg_we & !reg_error; assign alert_en_shadowed_57_wd = reg_wdata[0]; - assign alert_en_shadowed_58_re = addr_hit[129] & reg_re & !reg_error; - assign alert_en_shadowed_58_we = addr_hit[129] & reg_we & !reg_error; + assign alert_en_shadowed_58_re = addr_hit[130] & reg_re & !reg_error; + assign alert_en_shadowed_58_we = addr_hit[130] & reg_we & !reg_error; assign alert_en_shadowed_58_wd = reg_wdata[0]; - assign alert_en_shadowed_59_re = addr_hit[130] & reg_re & !reg_error; - assign alert_en_shadowed_59_we = addr_hit[130] & reg_we & !reg_error; + assign alert_en_shadowed_59_re = addr_hit[131] & reg_re & !reg_error; + assign alert_en_shadowed_59_we = addr_hit[131] & reg_we & !reg_error; assign alert_en_shadowed_59_wd = reg_wdata[0]; - assign alert_en_shadowed_60_re = addr_hit[131] & reg_re & !reg_error; - assign alert_en_shadowed_60_we = addr_hit[131] & reg_we & !reg_error; + assign alert_en_shadowed_60_re = addr_hit[132] & reg_re & !reg_error; + assign alert_en_shadowed_60_we = addr_hit[132] & reg_we & !reg_error; assign alert_en_shadowed_60_wd = reg_wdata[0]; - assign alert_en_shadowed_61_re = addr_hit[132] & reg_re & !reg_error; - assign alert_en_shadowed_61_we = addr_hit[132] & reg_we & !reg_error; + assign alert_en_shadowed_61_re = addr_hit[133] & reg_re & !reg_error; + assign alert_en_shadowed_61_we = addr_hit[133] & reg_we & !reg_error; assign alert_en_shadowed_61_wd = reg_wdata[0]; - assign alert_en_shadowed_62_re = addr_hit[133] & reg_re & !reg_error; - assign alert_en_shadowed_62_we = addr_hit[133] & reg_we & !reg_error; + assign alert_en_shadowed_62_re = addr_hit[134] & reg_re & !reg_error; + assign alert_en_shadowed_62_we = addr_hit[134] & reg_we & !reg_error; assign alert_en_shadowed_62_wd = reg_wdata[0]; - assign alert_en_shadowed_63_re = addr_hit[134] & reg_re & !reg_error; - assign alert_en_shadowed_63_we = addr_hit[134] & reg_we & !reg_error; + assign alert_en_shadowed_63_re = addr_hit[135] & reg_re & !reg_error; + assign alert_en_shadowed_63_we = addr_hit[135] & reg_we & !reg_error; assign alert_en_shadowed_63_wd = reg_wdata[0]; - assign alert_en_shadowed_64_re = addr_hit[135] & reg_re & !reg_error; - assign alert_en_shadowed_64_we = addr_hit[135] & reg_we & !reg_error; + assign alert_en_shadowed_64_re = addr_hit[136] & reg_re & !reg_error; + assign alert_en_shadowed_64_we = addr_hit[136] & reg_we & !reg_error; assign alert_en_shadowed_64_wd = reg_wdata[0]; - assign alert_class_shadowed_0_re = addr_hit[136] & reg_re & !reg_error; - assign alert_class_shadowed_0_we = addr_hit[136] & reg_we & !reg_error; + assign alert_en_shadowed_65_re = addr_hit[137] & reg_re & !reg_error; + assign alert_en_shadowed_65_we = addr_hit[137] & reg_we & !reg_error; + + assign alert_en_shadowed_65_wd = reg_wdata[0]; + assign alert_class_shadowed_0_re = addr_hit[138] & reg_re & !reg_error; + assign alert_class_shadowed_0_we = addr_hit[138] & reg_we & !reg_error; assign alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign alert_class_shadowed_1_re = addr_hit[137] & reg_re & !reg_error; - assign alert_class_shadowed_1_we = addr_hit[137] & reg_we & !reg_error; + assign alert_class_shadowed_1_re = addr_hit[139] & reg_re & !reg_error; + assign alert_class_shadowed_1_we = addr_hit[139] & reg_we & !reg_error; assign alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign alert_class_shadowed_2_re = addr_hit[138] & reg_re & !reg_error; - assign alert_class_shadowed_2_we = addr_hit[138] & reg_we & !reg_error; + assign alert_class_shadowed_2_re = addr_hit[140] & reg_re & !reg_error; + assign alert_class_shadowed_2_we = addr_hit[140] & reg_we & !reg_error; assign alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign alert_class_shadowed_3_re = addr_hit[139] & reg_re & !reg_error; - assign alert_class_shadowed_3_we = addr_hit[139] & reg_we & !reg_error; + assign alert_class_shadowed_3_re = addr_hit[141] & reg_re & !reg_error; + assign alert_class_shadowed_3_we = addr_hit[141] & reg_we & !reg_error; assign alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign alert_class_shadowed_4_re = addr_hit[140] & reg_re & !reg_error; - assign alert_class_shadowed_4_we = addr_hit[140] & reg_we & !reg_error; + assign alert_class_shadowed_4_re = addr_hit[142] & reg_re & !reg_error; + assign alert_class_shadowed_4_we = addr_hit[142] & reg_we & !reg_error; assign alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign alert_class_shadowed_5_re = addr_hit[141] & reg_re & !reg_error; - assign alert_class_shadowed_5_we = addr_hit[141] & reg_we & !reg_error; + assign alert_class_shadowed_5_re = addr_hit[143] & reg_re & !reg_error; + assign alert_class_shadowed_5_we = addr_hit[143] & reg_we & !reg_error; assign alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign alert_class_shadowed_6_re = addr_hit[142] & reg_re & !reg_error; - assign alert_class_shadowed_6_we = addr_hit[142] & reg_we & !reg_error; + assign alert_class_shadowed_6_re = addr_hit[144] & reg_re & !reg_error; + assign alert_class_shadowed_6_we = addr_hit[144] & reg_we & !reg_error; assign alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign alert_class_shadowed_7_re = addr_hit[143] & reg_re & !reg_error; - assign alert_class_shadowed_7_we = addr_hit[143] & reg_we & !reg_error; + assign alert_class_shadowed_7_re = addr_hit[145] & reg_re & !reg_error; + assign alert_class_shadowed_7_we = addr_hit[145] & reg_we & !reg_error; assign alert_class_shadowed_7_wd = reg_wdata[1:0]; - assign alert_class_shadowed_8_re = addr_hit[144] & reg_re & !reg_error; - assign alert_class_shadowed_8_we = addr_hit[144] & reg_we & !reg_error; + assign alert_class_shadowed_8_re = addr_hit[146] & reg_re & !reg_error; + assign alert_class_shadowed_8_we = addr_hit[146] & reg_we & !reg_error; assign alert_class_shadowed_8_wd = reg_wdata[1:0]; - assign alert_class_shadowed_9_re = addr_hit[145] & reg_re & !reg_error; - assign alert_class_shadowed_9_we = addr_hit[145] & reg_we & !reg_error; + assign alert_class_shadowed_9_re = addr_hit[147] & reg_re & !reg_error; + assign alert_class_shadowed_9_we = addr_hit[147] & reg_we & !reg_error; assign alert_class_shadowed_9_wd = reg_wdata[1:0]; - assign alert_class_shadowed_10_re = addr_hit[146] & reg_re & !reg_error; - assign alert_class_shadowed_10_we = addr_hit[146] & reg_we & !reg_error; + assign alert_class_shadowed_10_re = addr_hit[148] & reg_re & !reg_error; + assign alert_class_shadowed_10_we = addr_hit[148] & reg_we & !reg_error; assign alert_class_shadowed_10_wd = reg_wdata[1:0]; - assign alert_class_shadowed_11_re = addr_hit[147] & reg_re & !reg_error; - assign alert_class_shadowed_11_we = addr_hit[147] & reg_we & !reg_error; + assign alert_class_shadowed_11_re = addr_hit[149] & reg_re & !reg_error; + assign alert_class_shadowed_11_we = addr_hit[149] & reg_we & !reg_error; assign alert_class_shadowed_11_wd = reg_wdata[1:0]; - assign alert_class_shadowed_12_re = addr_hit[148] & reg_re & !reg_error; - assign alert_class_shadowed_12_we = addr_hit[148] & reg_we & !reg_error; + assign alert_class_shadowed_12_re = addr_hit[150] & reg_re & !reg_error; + assign alert_class_shadowed_12_we = addr_hit[150] & reg_we & !reg_error; assign alert_class_shadowed_12_wd = reg_wdata[1:0]; - assign alert_class_shadowed_13_re = addr_hit[149] & reg_re & !reg_error; - assign alert_class_shadowed_13_we = addr_hit[149] & reg_we & !reg_error; + assign alert_class_shadowed_13_re = addr_hit[151] & reg_re & !reg_error; + assign alert_class_shadowed_13_we = addr_hit[151] & reg_we & !reg_error; assign alert_class_shadowed_13_wd = reg_wdata[1:0]; - assign alert_class_shadowed_14_re = addr_hit[150] & reg_re & !reg_error; - assign alert_class_shadowed_14_we = addr_hit[150] & reg_we & !reg_error; + assign alert_class_shadowed_14_re = addr_hit[152] & reg_re & !reg_error; + assign alert_class_shadowed_14_we = addr_hit[152] & reg_we & !reg_error; assign alert_class_shadowed_14_wd = reg_wdata[1:0]; - assign alert_class_shadowed_15_re = addr_hit[151] & reg_re & !reg_error; - assign alert_class_shadowed_15_we = addr_hit[151] & reg_we & !reg_error; + assign alert_class_shadowed_15_re = addr_hit[153] & reg_re & !reg_error; + assign alert_class_shadowed_15_we = addr_hit[153] & reg_we & !reg_error; assign alert_class_shadowed_15_wd = reg_wdata[1:0]; - assign alert_class_shadowed_16_re = addr_hit[152] & reg_re & !reg_error; - assign alert_class_shadowed_16_we = addr_hit[152] & reg_we & !reg_error; + assign alert_class_shadowed_16_re = addr_hit[154] & reg_re & !reg_error; + assign alert_class_shadowed_16_we = addr_hit[154] & reg_we & !reg_error; assign alert_class_shadowed_16_wd = reg_wdata[1:0]; - assign alert_class_shadowed_17_re = addr_hit[153] & reg_re & !reg_error; - assign alert_class_shadowed_17_we = addr_hit[153] & reg_we & !reg_error; + assign alert_class_shadowed_17_re = addr_hit[155] & reg_re & !reg_error; + assign alert_class_shadowed_17_we = addr_hit[155] & reg_we & !reg_error; assign alert_class_shadowed_17_wd = reg_wdata[1:0]; - assign alert_class_shadowed_18_re = addr_hit[154] & reg_re & !reg_error; - assign alert_class_shadowed_18_we = addr_hit[154] & reg_we & !reg_error; + assign alert_class_shadowed_18_re = addr_hit[156] & reg_re & !reg_error; + assign alert_class_shadowed_18_we = addr_hit[156] & reg_we & !reg_error; assign alert_class_shadowed_18_wd = reg_wdata[1:0]; - assign alert_class_shadowed_19_re = addr_hit[155] & reg_re & !reg_error; - assign alert_class_shadowed_19_we = addr_hit[155] & reg_we & !reg_error; + assign alert_class_shadowed_19_re = addr_hit[157] & reg_re & !reg_error; + assign alert_class_shadowed_19_we = addr_hit[157] & reg_we & !reg_error; assign alert_class_shadowed_19_wd = reg_wdata[1:0]; - assign alert_class_shadowed_20_re = addr_hit[156] & reg_re & !reg_error; - assign alert_class_shadowed_20_we = addr_hit[156] & reg_we & !reg_error; + assign alert_class_shadowed_20_re = addr_hit[158] & reg_re & !reg_error; + assign alert_class_shadowed_20_we = addr_hit[158] & reg_we & !reg_error; assign alert_class_shadowed_20_wd = reg_wdata[1:0]; - assign alert_class_shadowed_21_re = addr_hit[157] & reg_re & !reg_error; - assign alert_class_shadowed_21_we = addr_hit[157] & reg_we & !reg_error; + assign alert_class_shadowed_21_re = addr_hit[159] & reg_re & !reg_error; + assign alert_class_shadowed_21_we = addr_hit[159] & reg_we & !reg_error; assign alert_class_shadowed_21_wd = reg_wdata[1:0]; - assign alert_class_shadowed_22_re = addr_hit[158] & reg_re & !reg_error; - assign alert_class_shadowed_22_we = addr_hit[158] & reg_we & !reg_error; + assign alert_class_shadowed_22_re = addr_hit[160] & reg_re & !reg_error; + assign alert_class_shadowed_22_we = addr_hit[160] & reg_we & !reg_error; assign alert_class_shadowed_22_wd = reg_wdata[1:0]; - assign alert_class_shadowed_23_re = addr_hit[159] & reg_re & !reg_error; - assign alert_class_shadowed_23_we = addr_hit[159] & reg_we & !reg_error; + assign alert_class_shadowed_23_re = addr_hit[161] & reg_re & !reg_error; + assign alert_class_shadowed_23_we = addr_hit[161] & reg_we & !reg_error; assign alert_class_shadowed_23_wd = reg_wdata[1:0]; - assign alert_class_shadowed_24_re = addr_hit[160] & reg_re & !reg_error; - assign alert_class_shadowed_24_we = addr_hit[160] & reg_we & !reg_error; + assign alert_class_shadowed_24_re = addr_hit[162] & reg_re & !reg_error; + assign alert_class_shadowed_24_we = addr_hit[162] & reg_we & !reg_error; assign alert_class_shadowed_24_wd = reg_wdata[1:0]; - assign alert_class_shadowed_25_re = addr_hit[161] & reg_re & !reg_error; - assign alert_class_shadowed_25_we = addr_hit[161] & reg_we & !reg_error; + assign alert_class_shadowed_25_re = addr_hit[163] & reg_re & !reg_error; + assign alert_class_shadowed_25_we = addr_hit[163] & reg_we & !reg_error; assign alert_class_shadowed_25_wd = reg_wdata[1:0]; - assign alert_class_shadowed_26_re = addr_hit[162] & reg_re & !reg_error; - assign alert_class_shadowed_26_we = addr_hit[162] & reg_we & !reg_error; + assign alert_class_shadowed_26_re = addr_hit[164] & reg_re & !reg_error; + assign alert_class_shadowed_26_we = addr_hit[164] & reg_we & !reg_error; assign alert_class_shadowed_26_wd = reg_wdata[1:0]; - assign alert_class_shadowed_27_re = addr_hit[163] & reg_re & !reg_error; - assign alert_class_shadowed_27_we = addr_hit[163] & reg_we & !reg_error; + assign alert_class_shadowed_27_re = addr_hit[165] & reg_re & !reg_error; + assign alert_class_shadowed_27_we = addr_hit[165] & reg_we & !reg_error; assign alert_class_shadowed_27_wd = reg_wdata[1:0]; - assign alert_class_shadowed_28_re = addr_hit[164] & reg_re & !reg_error; - assign alert_class_shadowed_28_we = addr_hit[164] & reg_we & !reg_error; + assign alert_class_shadowed_28_re = addr_hit[166] & reg_re & !reg_error; + assign alert_class_shadowed_28_we = addr_hit[166] & reg_we & !reg_error; assign alert_class_shadowed_28_wd = reg_wdata[1:0]; - assign alert_class_shadowed_29_re = addr_hit[165] & reg_re & !reg_error; - assign alert_class_shadowed_29_we = addr_hit[165] & reg_we & !reg_error; + assign alert_class_shadowed_29_re = addr_hit[167] & reg_re & !reg_error; + assign alert_class_shadowed_29_we = addr_hit[167] & reg_we & !reg_error; assign alert_class_shadowed_29_wd = reg_wdata[1:0]; - assign alert_class_shadowed_30_re = addr_hit[166] & reg_re & !reg_error; - assign alert_class_shadowed_30_we = addr_hit[166] & reg_we & !reg_error; + assign alert_class_shadowed_30_re = addr_hit[168] & reg_re & !reg_error; + assign alert_class_shadowed_30_we = addr_hit[168] & reg_we & !reg_error; assign alert_class_shadowed_30_wd = reg_wdata[1:0]; - assign alert_class_shadowed_31_re = addr_hit[167] & reg_re & !reg_error; - assign alert_class_shadowed_31_we = addr_hit[167] & reg_we & !reg_error; + assign alert_class_shadowed_31_re = addr_hit[169] & reg_re & !reg_error; + assign alert_class_shadowed_31_we = addr_hit[169] & reg_we & !reg_error; assign alert_class_shadowed_31_wd = reg_wdata[1:0]; - assign alert_class_shadowed_32_re = addr_hit[168] & reg_re & !reg_error; - assign alert_class_shadowed_32_we = addr_hit[168] & reg_we & !reg_error; + assign alert_class_shadowed_32_re = addr_hit[170] & reg_re & !reg_error; + assign alert_class_shadowed_32_we = addr_hit[170] & reg_we & !reg_error; assign alert_class_shadowed_32_wd = reg_wdata[1:0]; - assign alert_class_shadowed_33_re = addr_hit[169] & reg_re & !reg_error; - assign alert_class_shadowed_33_we = addr_hit[169] & reg_we & !reg_error; + assign alert_class_shadowed_33_re = addr_hit[171] & reg_re & !reg_error; + assign alert_class_shadowed_33_we = addr_hit[171] & reg_we & !reg_error; assign alert_class_shadowed_33_wd = reg_wdata[1:0]; - assign alert_class_shadowed_34_re = addr_hit[170] & reg_re & !reg_error; - assign alert_class_shadowed_34_we = addr_hit[170] & reg_we & !reg_error; + assign alert_class_shadowed_34_re = addr_hit[172] & reg_re & !reg_error; + assign alert_class_shadowed_34_we = addr_hit[172] & reg_we & !reg_error; assign alert_class_shadowed_34_wd = reg_wdata[1:0]; - assign alert_class_shadowed_35_re = addr_hit[171] & reg_re & !reg_error; - assign alert_class_shadowed_35_we = addr_hit[171] & reg_we & !reg_error; + assign alert_class_shadowed_35_re = addr_hit[173] & reg_re & !reg_error; + assign alert_class_shadowed_35_we = addr_hit[173] & reg_we & !reg_error; assign alert_class_shadowed_35_wd = reg_wdata[1:0]; - assign alert_class_shadowed_36_re = addr_hit[172] & reg_re & !reg_error; - assign alert_class_shadowed_36_we = addr_hit[172] & reg_we & !reg_error; + assign alert_class_shadowed_36_re = addr_hit[174] & reg_re & !reg_error; + assign alert_class_shadowed_36_we = addr_hit[174] & reg_we & !reg_error; assign alert_class_shadowed_36_wd = reg_wdata[1:0]; - assign alert_class_shadowed_37_re = addr_hit[173] & reg_re & !reg_error; - assign alert_class_shadowed_37_we = addr_hit[173] & reg_we & !reg_error; + assign alert_class_shadowed_37_re = addr_hit[175] & reg_re & !reg_error; + assign alert_class_shadowed_37_we = addr_hit[175] & reg_we & !reg_error; assign alert_class_shadowed_37_wd = reg_wdata[1:0]; - assign alert_class_shadowed_38_re = addr_hit[174] & reg_re & !reg_error; - assign alert_class_shadowed_38_we = addr_hit[174] & reg_we & !reg_error; + assign alert_class_shadowed_38_re = addr_hit[176] & reg_re & !reg_error; + assign alert_class_shadowed_38_we = addr_hit[176] & reg_we & !reg_error; assign alert_class_shadowed_38_wd = reg_wdata[1:0]; - assign alert_class_shadowed_39_re = addr_hit[175] & reg_re & !reg_error; - assign alert_class_shadowed_39_we = addr_hit[175] & reg_we & !reg_error; + assign alert_class_shadowed_39_re = addr_hit[177] & reg_re & !reg_error; + assign alert_class_shadowed_39_we = addr_hit[177] & reg_we & !reg_error; assign alert_class_shadowed_39_wd = reg_wdata[1:0]; - assign alert_class_shadowed_40_re = addr_hit[176] & reg_re & !reg_error; - assign alert_class_shadowed_40_we = addr_hit[176] & reg_we & !reg_error; + assign alert_class_shadowed_40_re = addr_hit[178] & reg_re & !reg_error; + assign alert_class_shadowed_40_we = addr_hit[178] & reg_we & !reg_error; assign alert_class_shadowed_40_wd = reg_wdata[1:0]; - assign alert_class_shadowed_41_re = addr_hit[177] & reg_re & !reg_error; - assign alert_class_shadowed_41_we = addr_hit[177] & reg_we & !reg_error; + assign alert_class_shadowed_41_re = addr_hit[179] & reg_re & !reg_error; + assign alert_class_shadowed_41_we = addr_hit[179] & reg_we & !reg_error; assign alert_class_shadowed_41_wd = reg_wdata[1:0]; - assign alert_class_shadowed_42_re = addr_hit[178] & reg_re & !reg_error; - assign alert_class_shadowed_42_we = addr_hit[178] & reg_we & !reg_error; + assign alert_class_shadowed_42_re = addr_hit[180] & reg_re & !reg_error; + assign alert_class_shadowed_42_we = addr_hit[180] & reg_we & !reg_error; assign alert_class_shadowed_42_wd = reg_wdata[1:0]; - assign alert_class_shadowed_43_re = addr_hit[179] & reg_re & !reg_error; - assign alert_class_shadowed_43_we = addr_hit[179] & reg_we & !reg_error; + assign alert_class_shadowed_43_re = addr_hit[181] & reg_re & !reg_error; + assign alert_class_shadowed_43_we = addr_hit[181] & reg_we & !reg_error; assign alert_class_shadowed_43_wd = reg_wdata[1:0]; - assign alert_class_shadowed_44_re = addr_hit[180] & reg_re & !reg_error; - assign alert_class_shadowed_44_we = addr_hit[180] & reg_we & !reg_error; + assign alert_class_shadowed_44_re = addr_hit[182] & reg_re & !reg_error; + assign alert_class_shadowed_44_we = addr_hit[182] & reg_we & !reg_error; assign alert_class_shadowed_44_wd = reg_wdata[1:0]; - assign alert_class_shadowed_45_re = addr_hit[181] & reg_re & !reg_error; - assign alert_class_shadowed_45_we = addr_hit[181] & reg_we & !reg_error; + assign alert_class_shadowed_45_re = addr_hit[183] & reg_re & !reg_error; + assign alert_class_shadowed_45_we = addr_hit[183] & reg_we & !reg_error; assign alert_class_shadowed_45_wd = reg_wdata[1:0]; - assign alert_class_shadowed_46_re = addr_hit[182] & reg_re & !reg_error; - assign alert_class_shadowed_46_we = addr_hit[182] & reg_we & !reg_error; + assign alert_class_shadowed_46_re = addr_hit[184] & reg_re & !reg_error; + assign alert_class_shadowed_46_we = addr_hit[184] & reg_we & !reg_error; assign alert_class_shadowed_46_wd = reg_wdata[1:0]; - assign alert_class_shadowed_47_re = addr_hit[183] & reg_re & !reg_error; - assign alert_class_shadowed_47_we = addr_hit[183] & reg_we & !reg_error; + assign alert_class_shadowed_47_re = addr_hit[185] & reg_re & !reg_error; + assign alert_class_shadowed_47_we = addr_hit[185] & reg_we & !reg_error; assign alert_class_shadowed_47_wd = reg_wdata[1:0]; - assign alert_class_shadowed_48_re = addr_hit[184] & reg_re & !reg_error; - assign alert_class_shadowed_48_we = addr_hit[184] & reg_we & !reg_error; + assign alert_class_shadowed_48_re = addr_hit[186] & reg_re & !reg_error; + assign alert_class_shadowed_48_we = addr_hit[186] & reg_we & !reg_error; assign alert_class_shadowed_48_wd = reg_wdata[1:0]; - assign alert_class_shadowed_49_re = addr_hit[185] & reg_re & !reg_error; - assign alert_class_shadowed_49_we = addr_hit[185] & reg_we & !reg_error; + assign alert_class_shadowed_49_re = addr_hit[187] & reg_re & !reg_error; + assign alert_class_shadowed_49_we = addr_hit[187] & reg_we & !reg_error; assign alert_class_shadowed_49_wd = reg_wdata[1:0]; - assign alert_class_shadowed_50_re = addr_hit[186] & reg_re & !reg_error; - assign alert_class_shadowed_50_we = addr_hit[186] & reg_we & !reg_error; + assign alert_class_shadowed_50_re = addr_hit[188] & reg_re & !reg_error; + assign alert_class_shadowed_50_we = addr_hit[188] & reg_we & !reg_error; assign alert_class_shadowed_50_wd = reg_wdata[1:0]; - assign alert_class_shadowed_51_re = addr_hit[187] & reg_re & !reg_error; - assign alert_class_shadowed_51_we = addr_hit[187] & reg_we & !reg_error; + assign alert_class_shadowed_51_re = addr_hit[189] & reg_re & !reg_error; + assign alert_class_shadowed_51_we = addr_hit[189] & reg_we & !reg_error; assign alert_class_shadowed_51_wd = reg_wdata[1:0]; - assign alert_class_shadowed_52_re = addr_hit[188] & reg_re & !reg_error; - assign alert_class_shadowed_52_we = addr_hit[188] & reg_we & !reg_error; + assign alert_class_shadowed_52_re = addr_hit[190] & reg_re & !reg_error; + assign alert_class_shadowed_52_we = addr_hit[190] & reg_we & !reg_error; assign alert_class_shadowed_52_wd = reg_wdata[1:0]; - assign alert_class_shadowed_53_re = addr_hit[189] & reg_re & !reg_error; - assign alert_class_shadowed_53_we = addr_hit[189] & reg_we & !reg_error; + assign alert_class_shadowed_53_re = addr_hit[191] & reg_re & !reg_error; + assign alert_class_shadowed_53_we = addr_hit[191] & reg_we & !reg_error; assign alert_class_shadowed_53_wd = reg_wdata[1:0]; - assign alert_class_shadowed_54_re = addr_hit[190] & reg_re & !reg_error; - assign alert_class_shadowed_54_we = addr_hit[190] & reg_we & !reg_error; + assign alert_class_shadowed_54_re = addr_hit[192] & reg_re & !reg_error; + assign alert_class_shadowed_54_we = addr_hit[192] & reg_we & !reg_error; assign alert_class_shadowed_54_wd = reg_wdata[1:0]; - assign alert_class_shadowed_55_re = addr_hit[191] & reg_re & !reg_error; - assign alert_class_shadowed_55_we = addr_hit[191] & reg_we & !reg_error; + assign alert_class_shadowed_55_re = addr_hit[193] & reg_re & !reg_error; + assign alert_class_shadowed_55_we = addr_hit[193] & reg_we & !reg_error; assign alert_class_shadowed_55_wd = reg_wdata[1:0]; - assign alert_class_shadowed_56_re = addr_hit[192] & reg_re & !reg_error; - assign alert_class_shadowed_56_we = addr_hit[192] & reg_we & !reg_error; + assign alert_class_shadowed_56_re = addr_hit[194] & reg_re & !reg_error; + assign alert_class_shadowed_56_we = addr_hit[194] & reg_we & !reg_error; assign alert_class_shadowed_56_wd = reg_wdata[1:0]; - assign alert_class_shadowed_57_re = addr_hit[193] & reg_re & !reg_error; - assign alert_class_shadowed_57_we = addr_hit[193] & reg_we & !reg_error; + assign alert_class_shadowed_57_re = addr_hit[195] & reg_re & !reg_error; + assign alert_class_shadowed_57_we = addr_hit[195] & reg_we & !reg_error; assign alert_class_shadowed_57_wd = reg_wdata[1:0]; - assign alert_class_shadowed_58_re = addr_hit[194] & reg_re & !reg_error; - assign alert_class_shadowed_58_we = addr_hit[194] & reg_we & !reg_error; + assign alert_class_shadowed_58_re = addr_hit[196] & reg_re & !reg_error; + assign alert_class_shadowed_58_we = addr_hit[196] & reg_we & !reg_error; assign alert_class_shadowed_58_wd = reg_wdata[1:0]; - assign alert_class_shadowed_59_re = addr_hit[195] & reg_re & !reg_error; - assign alert_class_shadowed_59_we = addr_hit[195] & reg_we & !reg_error; + assign alert_class_shadowed_59_re = addr_hit[197] & reg_re & !reg_error; + assign alert_class_shadowed_59_we = addr_hit[197] & reg_we & !reg_error; assign alert_class_shadowed_59_wd = reg_wdata[1:0]; - assign alert_class_shadowed_60_re = addr_hit[196] & reg_re & !reg_error; - assign alert_class_shadowed_60_we = addr_hit[196] & reg_we & !reg_error; + assign alert_class_shadowed_60_re = addr_hit[198] & reg_re & !reg_error; + assign alert_class_shadowed_60_we = addr_hit[198] & reg_we & !reg_error; assign alert_class_shadowed_60_wd = reg_wdata[1:0]; - assign alert_class_shadowed_61_re = addr_hit[197] & reg_re & !reg_error; - assign alert_class_shadowed_61_we = addr_hit[197] & reg_we & !reg_error; + assign alert_class_shadowed_61_re = addr_hit[199] & reg_re & !reg_error; + assign alert_class_shadowed_61_we = addr_hit[199] & reg_we & !reg_error; assign alert_class_shadowed_61_wd = reg_wdata[1:0]; - assign alert_class_shadowed_62_re = addr_hit[198] & reg_re & !reg_error; - assign alert_class_shadowed_62_we = addr_hit[198] & reg_we & !reg_error; + assign alert_class_shadowed_62_re = addr_hit[200] & reg_re & !reg_error; + assign alert_class_shadowed_62_we = addr_hit[200] & reg_we & !reg_error; assign alert_class_shadowed_62_wd = reg_wdata[1:0]; - assign alert_class_shadowed_63_re = addr_hit[199] & reg_re & !reg_error; - assign alert_class_shadowed_63_we = addr_hit[199] & reg_we & !reg_error; + assign alert_class_shadowed_63_re = addr_hit[201] & reg_re & !reg_error; + assign alert_class_shadowed_63_we = addr_hit[201] & reg_we & !reg_error; assign alert_class_shadowed_63_wd = reg_wdata[1:0]; - assign alert_class_shadowed_64_re = addr_hit[200] & reg_re & !reg_error; - assign alert_class_shadowed_64_we = addr_hit[200] & reg_we & !reg_error; + assign alert_class_shadowed_64_re = addr_hit[202] & reg_re & !reg_error; + assign alert_class_shadowed_64_we = addr_hit[202] & reg_we & !reg_error; assign alert_class_shadowed_64_wd = reg_wdata[1:0]; - assign alert_cause_0_we = addr_hit[201] & reg_we & !reg_error; + assign alert_class_shadowed_65_re = addr_hit[203] & reg_re & !reg_error; + assign alert_class_shadowed_65_we = addr_hit[203] & reg_we & !reg_error; + + assign alert_class_shadowed_65_wd = reg_wdata[1:0]; + assign alert_cause_0_we = addr_hit[204] & reg_we & !reg_error; assign alert_cause_0_wd = reg_wdata[0]; - assign alert_cause_1_we = addr_hit[202] & reg_we & !reg_error; + assign alert_cause_1_we = addr_hit[205] & reg_we & !reg_error; assign alert_cause_1_wd = reg_wdata[0]; - assign alert_cause_2_we = addr_hit[203] & reg_we & !reg_error; + assign alert_cause_2_we = addr_hit[206] & reg_we & !reg_error; assign alert_cause_2_wd = reg_wdata[0]; - assign alert_cause_3_we = addr_hit[204] & reg_we & !reg_error; + assign alert_cause_3_we = addr_hit[207] & reg_we & !reg_error; assign alert_cause_3_wd = reg_wdata[0]; - assign alert_cause_4_we = addr_hit[205] & reg_we & !reg_error; + assign alert_cause_4_we = addr_hit[208] & reg_we & !reg_error; assign alert_cause_4_wd = reg_wdata[0]; - assign alert_cause_5_we = addr_hit[206] & reg_we & !reg_error; + assign alert_cause_5_we = addr_hit[209] & reg_we & !reg_error; assign alert_cause_5_wd = reg_wdata[0]; - assign alert_cause_6_we = addr_hit[207] & reg_we & !reg_error; + assign alert_cause_6_we = addr_hit[210] & reg_we & !reg_error; assign alert_cause_6_wd = reg_wdata[0]; - assign alert_cause_7_we = addr_hit[208] & reg_we & !reg_error; + assign alert_cause_7_we = addr_hit[211] & reg_we & !reg_error; assign alert_cause_7_wd = reg_wdata[0]; - assign alert_cause_8_we = addr_hit[209] & reg_we & !reg_error; + assign alert_cause_8_we = addr_hit[212] & reg_we & !reg_error; assign alert_cause_8_wd = reg_wdata[0]; - assign alert_cause_9_we = addr_hit[210] & reg_we & !reg_error; + assign alert_cause_9_we = addr_hit[213] & reg_we & !reg_error; assign alert_cause_9_wd = reg_wdata[0]; - assign alert_cause_10_we = addr_hit[211] & reg_we & !reg_error; + assign alert_cause_10_we = addr_hit[214] & reg_we & !reg_error; assign alert_cause_10_wd = reg_wdata[0]; - assign alert_cause_11_we = addr_hit[212] & reg_we & !reg_error; + assign alert_cause_11_we = addr_hit[215] & reg_we & !reg_error; assign alert_cause_11_wd = reg_wdata[0]; - assign alert_cause_12_we = addr_hit[213] & reg_we & !reg_error; + assign alert_cause_12_we = addr_hit[216] & reg_we & !reg_error; assign alert_cause_12_wd = reg_wdata[0]; - assign alert_cause_13_we = addr_hit[214] & reg_we & !reg_error; + assign alert_cause_13_we = addr_hit[217] & reg_we & !reg_error; assign alert_cause_13_wd = reg_wdata[0]; - assign alert_cause_14_we = addr_hit[215] & reg_we & !reg_error; + assign alert_cause_14_we = addr_hit[218] & reg_we & !reg_error; assign alert_cause_14_wd = reg_wdata[0]; - assign alert_cause_15_we = addr_hit[216] & reg_we & !reg_error; + assign alert_cause_15_we = addr_hit[219] & reg_we & !reg_error; assign alert_cause_15_wd = reg_wdata[0]; - assign alert_cause_16_we = addr_hit[217] & reg_we & !reg_error; + assign alert_cause_16_we = addr_hit[220] & reg_we & !reg_error; assign alert_cause_16_wd = reg_wdata[0]; - assign alert_cause_17_we = addr_hit[218] & reg_we & !reg_error; + assign alert_cause_17_we = addr_hit[221] & reg_we & !reg_error; assign alert_cause_17_wd = reg_wdata[0]; - assign alert_cause_18_we = addr_hit[219] & reg_we & !reg_error; + assign alert_cause_18_we = addr_hit[222] & reg_we & !reg_error; assign alert_cause_18_wd = reg_wdata[0]; - assign alert_cause_19_we = addr_hit[220] & reg_we & !reg_error; + assign alert_cause_19_we = addr_hit[223] & reg_we & !reg_error; assign alert_cause_19_wd = reg_wdata[0]; - assign alert_cause_20_we = addr_hit[221] & reg_we & !reg_error; + assign alert_cause_20_we = addr_hit[224] & reg_we & !reg_error; assign alert_cause_20_wd = reg_wdata[0]; - assign alert_cause_21_we = addr_hit[222] & reg_we & !reg_error; + assign alert_cause_21_we = addr_hit[225] & reg_we & !reg_error; assign alert_cause_21_wd = reg_wdata[0]; - assign alert_cause_22_we = addr_hit[223] & reg_we & !reg_error; + assign alert_cause_22_we = addr_hit[226] & reg_we & !reg_error; assign alert_cause_22_wd = reg_wdata[0]; - assign alert_cause_23_we = addr_hit[224] & reg_we & !reg_error; + assign alert_cause_23_we = addr_hit[227] & reg_we & !reg_error; assign alert_cause_23_wd = reg_wdata[0]; - assign alert_cause_24_we = addr_hit[225] & reg_we & !reg_error; + assign alert_cause_24_we = addr_hit[228] & reg_we & !reg_error; assign alert_cause_24_wd = reg_wdata[0]; - assign alert_cause_25_we = addr_hit[226] & reg_we & !reg_error; + assign alert_cause_25_we = addr_hit[229] & reg_we & !reg_error; assign alert_cause_25_wd = reg_wdata[0]; - assign alert_cause_26_we = addr_hit[227] & reg_we & !reg_error; + assign alert_cause_26_we = addr_hit[230] & reg_we & !reg_error; assign alert_cause_26_wd = reg_wdata[0]; - assign alert_cause_27_we = addr_hit[228] & reg_we & !reg_error; + assign alert_cause_27_we = addr_hit[231] & reg_we & !reg_error; assign alert_cause_27_wd = reg_wdata[0]; - assign alert_cause_28_we = addr_hit[229] & reg_we & !reg_error; + assign alert_cause_28_we = addr_hit[232] & reg_we & !reg_error; assign alert_cause_28_wd = reg_wdata[0]; - assign alert_cause_29_we = addr_hit[230] & reg_we & !reg_error; + assign alert_cause_29_we = addr_hit[233] & reg_we & !reg_error; assign alert_cause_29_wd = reg_wdata[0]; - assign alert_cause_30_we = addr_hit[231] & reg_we & !reg_error; + assign alert_cause_30_we = addr_hit[234] & reg_we & !reg_error; assign alert_cause_30_wd = reg_wdata[0]; - assign alert_cause_31_we = addr_hit[232] & reg_we & !reg_error; + assign alert_cause_31_we = addr_hit[235] & reg_we & !reg_error; assign alert_cause_31_wd = reg_wdata[0]; - assign alert_cause_32_we = addr_hit[233] & reg_we & !reg_error; + assign alert_cause_32_we = addr_hit[236] & reg_we & !reg_error; assign alert_cause_32_wd = reg_wdata[0]; - assign alert_cause_33_we = addr_hit[234] & reg_we & !reg_error; + assign alert_cause_33_we = addr_hit[237] & reg_we & !reg_error; assign alert_cause_33_wd = reg_wdata[0]; - assign alert_cause_34_we = addr_hit[235] & reg_we & !reg_error; + assign alert_cause_34_we = addr_hit[238] & reg_we & !reg_error; assign alert_cause_34_wd = reg_wdata[0]; - assign alert_cause_35_we = addr_hit[236] & reg_we & !reg_error; + assign alert_cause_35_we = addr_hit[239] & reg_we & !reg_error; assign alert_cause_35_wd = reg_wdata[0]; - assign alert_cause_36_we = addr_hit[237] & reg_we & !reg_error; + assign alert_cause_36_we = addr_hit[240] & reg_we & !reg_error; assign alert_cause_36_wd = reg_wdata[0]; - assign alert_cause_37_we = addr_hit[238] & reg_we & !reg_error; + assign alert_cause_37_we = addr_hit[241] & reg_we & !reg_error; assign alert_cause_37_wd = reg_wdata[0]; - assign alert_cause_38_we = addr_hit[239] & reg_we & !reg_error; + assign alert_cause_38_we = addr_hit[242] & reg_we & !reg_error; assign alert_cause_38_wd = reg_wdata[0]; - assign alert_cause_39_we = addr_hit[240] & reg_we & !reg_error; + assign alert_cause_39_we = addr_hit[243] & reg_we & !reg_error; assign alert_cause_39_wd = reg_wdata[0]; - assign alert_cause_40_we = addr_hit[241] & reg_we & !reg_error; + assign alert_cause_40_we = addr_hit[244] & reg_we & !reg_error; assign alert_cause_40_wd = reg_wdata[0]; - assign alert_cause_41_we = addr_hit[242] & reg_we & !reg_error; + assign alert_cause_41_we = addr_hit[245] & reg_we & !reg_error; assign alert_cause_41_wd = reg_wdata[0]; - assign alert_cause_42_we = addr_hit[243] & reg_we & !reg_error; + assign alert_cause_42_we = addr_hit[246] & reg_we & !reg_error; assign alert_cause_42_wd = reg_wdata[0]; - assign alert_cause_43_we = addr_hit[244] & reg_we & !reg_error; + assign alert_cause_43_we = addr_hit[247] & reg_we & !reg_error; assign alert_cause_43_wd = reg_wdata[0]; - assign alert_cause_44_we = addr_hit[245] & reg_we & !reg_error; + assign alert_cause_44_we = addr_hit[248] & reg_we & !reg_error; assign alert_cause_44_wd = reg_wdata[0]; - assign alert_cause_45_we = addr_hit[246] & reg_we & !reg_error; + assign alert_cause_45_we = addr_hit[249] & reg_we & !reg_error; assign alert_cause_45_wd = reg_wdata[0]; - assign alert_cause_46_we = addr_hit[247] & reg_we & !reg_error; + assign alert_cause_46_we = addr_hit[250] & reg_we & !reg_error; assign alert_cause_46_wd = reg_wdata[0]; - assign alert_cause_47_we = addr_hit[248] & reg_we & !reg_error; + assign alert_cause_47_we = addr_hit[251] & reg_we & !reg_error; assign alert_cause_47_wd = reg_wdata[0]; - assign alert_cause_48_we = addr_hit[249] & reg_we & !reg_error; + assign alert_cause_48_we = addr_hit[252] & reg_we & !reg_error; assign alert_cause_48_wd = reg_wdata[0]; - assign alert_cause_49_we = addr_hit[250] & reg_we & !reg_error; + assign alert_cause_49_we = addr_hit[253] & reg_we & !reg_error; assign alert_cause_49_wd = reg_wdata[0]; - assign alert_cause_50_we = addr_hit[251] & reg_we & !reg_error; + assign alert_cause_50_we = addr_hit[254] & reg_we & !reg_error; assign alert_cause_50_wd = reg_wdata[0]; - assign alert_cause_51_we = addr_hit[252] & reg_we & !reg_error; + assign alert_cause_51_we = addr_hit[255] & reg_we & !reg_error; assign alert_cause_51_wd = reg_wdata[0]; - assign alert_cause_52_we = addr_hit[253] & reg_we & !reg_error; + assign alert_cause_52_we = addr_hit[256] & reg_we & !reg_error; assign alert_cause_52_wd = reg_wdata[0]; - assign alert_cause_53_we = addr_hit[254] & reg_we & !reg_error; + assign alert_cause_53_we = addr_hit[257] & reg_we & !reg_error; assign alert_cause_53_wd = reg_wdata[0]; - assign alert_cause_54_we = addr_hit[255] & reg_we & !reg_error; + assign alert_cause_54_we = addr_hit[258] & reg_we & !reg_error; assign alert_cause_54_wd = reg_wdata[0]; - assign alert_cause_55_we = addr_hit[256] & reg_we & !reg_error; + assign alert_cause_55_we = addr_hit[259] & reg_we & !reg_error; assign alert_cause_55_wd = reg_wdata[0]; - assign alert_cause_56_we = addr_hit[257] & reg_we & !reg_error; + assign alert_cause_56_we = addr_hit[260] & reg_we & !reg_error; assign alert_cause_56_wd = reg_wdata[0]; - assign alert_cause_57_we = addr_hit[258] & reg_we & !reg_error; + assign alert_cause_57_we = addr_hit[261] & reg_we & !reg_error; assign alert_cause_57_wd = reg_wdata[0]; - assign alert_cause_58_we = addr_hit[259] & reg_we & !reg_error; + assign alert_cause_58_we = addr_hit[262] & reg_we & !reg_error; assign alert_cause_58_wd = reg_wdata[0]; - assign alert_cause_59_we = addr_hit[260] & reg_we & !reg_error; + assign alert_cause_59_we = addr_hit[263] & reg_we & !reg_error; assign alert_cause_59_wd = reg_wdata[0]; - assign alert_cause_60_we = addr_hit[261] & reg_we & !reg_error; + assign alert_cause_60_we = addr_hit[264] & reg_we & !reg_error; assign alert_cause_60_wd = reg_wdata[0]; - assign alert_cause_61_we = addr_hit[262] & reg_we & !reg_error; + assign alert_cause_61_we = addr_hit[265] & reg_we & !reg_error; assign alert_cause_61_wd = reg_wdata[0]; - assign alert_cause_62_we = addr_hit[263] & reg_we & !reg_error; + assign alert_cause_62_we = addr_hit[266] & reg_we & !reg_error; assign alert_cause_62_wd = reg_wdata[0]; - assign alert_cause_63_we = addr_hit[264] & reg_we & !reg_error; + assign alert_cause_63_we = addr_hit[267] & reg_we & !reg_error; assign alert_cause_63_wd = reg_wdata[0]; - assign alert_cause_64_we = addr_hit[265] & reg_we & !reg_error; + assign alert_cause_64_we = addr_hit[268] & reg_we & !reg_error; assign alert_cause_64_wd = reg_wdata[0]; - assign loc_alert_regwen_0_we = addr_hit[266] & reg_we & !reg_error; + assign alert_cause_65_we = addr_hit[269] & reg_we & !reg_error; + + assign alert_cause_65_wd = reg_wdata[0]; + assign loc_alert_regwen_0_we = addr_hit[270] & reg_we & !reg_error; assign loc_alert_regwen_0_wd = reg_wdata[0]; - assign loc_alert_regwen_1_we = addr_hit[267] & reg_we & !reg_error; + assign loc_alert_regwen_1_we = addr_hit[271] & reg_we & !reg_error; assign loc_alert_regwen_1_wd = reg_wdata[0]; - assign loc_alert_regwen_2_we = addr_hit[268] & reg_we & !reg_error; + assign loc_alert_regwen_2_we = addr_hit[272] & reg_we & !reg_error; assign loc_alert_regwen_2_wd = reg_wdata[0]; - assign loc_alert_regwen_3_we = addr_hit[269] & reg_we & !reg_error; + assign loc_alert_regwen_3_we = addr_hit[273] & reg_we & !reg_error; assign loc_alert_regwen_3_wd = reg_wdata[0]; - assign loc_alert_regwen_4_we = addr_hit[270] & reg_we & !reg_error; + assign loc_alert_regwen_4_we = addr_hit[274] & reg_we & !reg_error; assign loc_alert_regwen_4_wd = reg_wdata[0]; - assign loc_alert_regwen_5_we = addr_hit[271] & reg_we & !reg_error; + assign loc_alert_regwen_5_we = addr_hit[275] & reg_we & !reg_error; assign loc_alert_regwen_5_wd = reg_wdata[0]; - assign loc_alert_regwen_6_we = addr_hit[272] & reg_we & !reg_error; + assign loc_alert_regwen_6_we = addr_hit[276] & reg_we & !reg_error; assign loc_alert_regwen_6_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_0_re = addr_hit[273] & reg_re & !reg_error; - assign loc_alert_en_shadowed_0_we = addr_hit[273] & reg_we & !reg_error; + assign loc_alert_en_shadowed_0_re = addr_hit[277] & reg_re & !reg_error; + assign loc_alert_en_shadowed_0_we = addr_hit[277] & reg_we & !reg_error; assign loc_alert_en_shadowed_0_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_1_re = addr_hit[274] & reg_re & !reg_error; - assign loc_alert_en_shadowed_1_we = addr_hit[274] & reg_we & !reg_error; + assign loc_alert_en_shadowed_1_re = addr_hit[278] & reg_re & !reg_error; + assign loc_alert_en_shadowed_1_we = addr_hit[278] & reg_we & !reg_error; assign loc_alert_en_shadowed_1_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_2_re = addr_hit[275] & reg_re & !reg_error; - assign loc_alert_en_shadowed_2_we = addr_hit[275] & reg_we & !reg_error; + assign loc_alert_en_shadowed_2_re = addr_hit[279] & reg_re & !reg_error; + assign loc_alert_en_shadowed_2_we = addr_hit[279] & reg_we & !reg_error; assign loc_alert_en_shadowed_2_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_3_re = addr_hit[276] & reg_re & !reg_error; - assign loc_alert_en_shadowed_3_we = addr_hit[276] & reg_we & !reg_error; + assign loc_alert_en_shadowed_3_re = addr_hit[280] & reg_re & !reg_error; + assign loc_alert_en_shadowed_3_we = addr_hit[280] & reg_we & !reg_error; assign loc_alert_en_shadowed_3_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_4_re = addr_hit[277] & reg_re & !reg_error; - assign loc_alert_en_shadowed_4_we = addr_hit[277] & reg_we & !reg_error; + assign loc_alert_en_shadowed_4_re = addr_hit[281] & reg_re & !reg_error; + assign loc_alert_en_shadowed_4_we = addr_hit[281] & reg_we & !reg_error; assign loc_alert_en_shadowed_4_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_5_re = addr_hit[278] & reg_re & !reg_error; - assign loc_alert_en_shadowed_5_we = addr_hit[278] & reg_we & !reg_error; + assign loc_alert_en_shadowed_5_re = addr_hit[282] & reg_re & !reg_error; + assign loc_alert_en_shadowed_5_we = addr_hit[282] & reg_we & !reg_error; assign loc_alert_en_shadowed_5_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_6_re = addr_hit[279] & reg_re & !reg_error; - assign loc_alert_en_shadowed_6_we = addr_hit[279] & reg_we & !reg_error; + assign loc_alert_en_shadowed_6_re = addr_hit[283] & reg_re & !reg_error; + assign loc_alert_en_shadowed_6_we = addr_hit[283] & reg_we & !reg_error; assign loc_alert_en_shadowed_6_wd = reg_wdata[0]; - assign loc_alert_class_shadowed_0_re = addr_hit[280] & reg_re & !reg_error; - assign loc_alert_class_shadowed_0_we = addr_hit[280] & reg_we & !reg_error; + assign loc_alert_class_shadowed_0_re = addr_hit[284] & reg_re & !reg_error; + assign loc_alert_class_shadowed_0_we = addr_hit[284] & reg_we & !reg_error; assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_1_re = addr_hit[281] & reg_re & !reg_error; - assign loc_alert_class_shadowed_1_we = addr_hit[281] & reg_we & !reg_error; + assign loc_alert_class_shadowed_1_re = addr_hit[285] & reg_re & !reg_error; + assign loc_alert_class_shadowed_1_we = addr_hit[285] & reg_we & !reg_error; assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_2_re = addr_hit[282] & reg_re & !reg_error; - assign loc_alert_class_shadowed_2_we = addr_hit[282] & reg_we & !reg_error; + assign loc_alert_class_shadowed_2_re = addr_hit[286] & reg_re & !reg_error; + assign loc_alert_class_shadowed_2_we = addr_hit[286] & reg_we & !reg_error; assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_3_re = addr_hit[283] & reg_re & !reg_error; - assign loc_alert_class_shadowed_3_we = addr_hit[283] & reg_we & !reg_error; + assign loc_alert_class_shadowed_3_re = addr_hit[287] & reg_re & !reg_error; + assign loc_alert_class_shadowed_3_we = addr_hit[287] & reg_we & !reg_error; assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_4_re = addr_hit[284] & reg_re & !reg_error; - assign loc_alert_class_shadowed_4_we = addr_hit[284] & reg_we & !reg_error; + assign loc_alert_class_shadowed_4_re = addr_hit[288] & reg_re & !reg_error; + assign loc_alert_class_shadowed_4_we = addr_hit[288] & reg_we & !reg_error; assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_5_re = addr_hit[285] & reg_re & !reg_error; - assign loc_alert_class_shadowed_5_we = addr_hit[285] & reg_we & !reg_error; + assign loc_alert_class_shadowed_5_re = addr_hit[289] & reg_re & !reg_error; + assign loc_alert_class_shadowed_5_we = addr_hit[289] & reg_we & !reg_error; assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_6_re = addr_hit[286] & reg_re & !reg_error; - assign loc_alert_class_shadowed_6_we = addr_hit[286] & reg_we & !reg_error; + assign loc_alert_class_shadowed_6_re = addr_hit[290] & reg_re & !reg_error; + assign loc_alert_class_shadowed_6_we = addr_hit[290] & reg_we & !reg_error; assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign loc_alert_cause_0_we = addr_hit[287] & reg_we & !reg_error; + assign loc_alert_cause_0_we = addr_hit[291] & reg_we & !reg_error; assign loc_alert_cause_0_wd = reg_wdata[0]; - assign loc_alert_cause_1_we = addr_hit[288] & reg_we & !reg_error; + assign loc_alert_cause_1_we = addr_hit[292] & reg_we & !reg_error; assign loc_alert_cause_1_wd = reg_wdata[0]; - assign loc_alert_cause_2_we = addr_hit[289] & reg_we & !reg_error; + assign loc_alert_cause_2_we = addr_hit[293] & reg_we & !reg_error; assign loc_alert_cause_2_wd = reg_wdata[0]; - assign loc_alert_cause_3_we = addr_hit[290] & reg_we & !reg_error; + assign loc_alert_cause_3_we = addr_hit[294] & reg_we & !reg_error; assign loc_alert_cause_3_wd = reg_wdata[0]; - assign loc_alert_cause_4_we = addr_hit[291] & reg_we & !reg_error; + assign loc_alert_cause_4_we = addr_hit[295] & reg_we & !reg_error; assign loc_alert_cause_4_wd = reg_wdata[0]; - assign loc_alert_cause_5_we = addr_hit[292] & reg_we & !reg_error; + assign loc_alert_cause_5_we = addr_hit[296] & reg_we & !reg_error; assign loc_alert_cause_5_wd = reg_wdata[0]; - assign loc_alert_cause_6_we = addr_hit[293] & reg_we & !reg_error; + assign loc_alert_cause_6_we = addr_hit[297] & reg_we & !reg_error; assign loc_alert_cause_6_wd = reg_wdata[0]; - assign classa_regwen_we = addr_hit[294] & reg_we & !reg_error; + assign classa_regwen_we = addr_hit[298] & reg_we & !reg_error; assign classa_regwen_wd = reg_wdata[0]; - assign classa_ctrl_shadowed_re = addr_hit[295] & reg_re & !reg_error; - assign classa_ctrl_shadowed_we = addr_hit[295] & reg_we & !reg_error; + assign classa_ctrl_shadowed_re = addr_hit[299] & reg_re & !reg_error; + assign classa_ctrl_shadowed_we = addr_hit[299] & reg_we & !reg_error; assign classa_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17346,49 +17526,49 @@ module alert_handler_reg_top ( assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classa_clr_regwen_we = addr_hit[296] & reg_we & !reg_error; + assign classa_clr_regwen_we = addr_hit[300] & reg_we & !reg_error; assign classa_clr_regwen_wd = reg_wdata[0]; - assign classa_clr_shadowed_re = addr_hit[297] & reg_re & !reg_error; - assign classa_clr_shadowed_we = addr_hit[297] & reg_we & !reg_error; + assign classa_clr_shadowed_re = addr_hit[301] & reg_re & !reg_error; + assign classa_clr_shadowed_we = addr_hit[301] & reg_we & !reg_error; assign classa_clr_shadowed_wd = reg_wdata[0]; - assign classa_accum_cnt_re = addr_hit[298] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_re = addr_hit[299] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_we = addr_hit[299] & reg_we & !reg_error; + assign classa_accum_cnt_re = addr_hit[302] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_re = addr_hit[303] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_we = addr_hit[303] & reg_we & !reg_error; assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classa_timeout_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error; - assign classa_timeout_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error; + assign classa_timeout_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error; + assign classa_timeout_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error; assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_crashdump_trigger_shadowed_re = addr_hit[301] & reg_re & !reg_error; - assign classa_crashdump_trigger_shadowed_we = addr_hit[301] & reg_we & !reg_error; + assign classa_crashdump_trigger_shadowed_re = addr_hit[305] & reg_re & !reg_error; + assign classa_crashdump_trigger_shadowed_we = addr_hit[305] & reg_we & !reg_error; assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classa_phase0_cyc_shadowed_re = addr_hit[302] & reg_re & !reg_error; - assign classa_phase0_cyc_shadowed_we = addr_hit[302] & reg_we & !reg_error; + assign classa_phase0_cyc_shadowed_re = addr_hit[306] & reg_re & !reg_error; + assign classa_phase0_cyc_shadowed_we = addr_hit[306] & reg_we & !reg_error; assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase1_cyc_shadowed_re = addr_hit[303] & reg_re & !reg_error; - assign classa_phase1_cyc_shadowed_we = addr_hit[303] & reg_we & !reg_error; + assign classa_phase1_cyc_shadowed_re = addr_hit[307] & reg_re & !reg_error; + assign classa_phase1_cyc_shadowed_we = addr_hit[307] & reg_we & !reg_error; assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase2_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error; - assign classa_phase2_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error; + assign classa_phase2_cyc_shadowed_re = addr_hit[308] & reg_re & !reg_error; + assign classa_phase2_cyc_shadowed_we = addr_hit[308] & reg_we & !reg_error; assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase3_cyc_shadowed_re = addr_hit[305] & reg_re & !reg_error; - assign classa_phase3_cyc_shadowed_we = addr_hit[305] & reg_we & !reg_error; + assign classa_phase3_cyc_shadowed_re = addr_hit[309] & reg_re & !reg_error; + assign classa_phase3_cyc_shadowed_we = addr_hit[309] & reg_we & !reg_error; assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_esc_cnt_re = addr_hit[306] & reg_re & !reg_error; - assign classa_state_re = addr_hit[307] & reg_re & !reg_error; - assign classb_regwen_we = addr_hit[308] & reg_we & !reg_error; + assign classa_esc_cnt_re = addr_hit[310] & reg_re & !reg_error; + assign classa_state_re = addr_hit[311] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[312] & reg_we & !reg_error; assign classb_regwen_wd = reg_wdata[0]; - assign classb_ctrl_shadowed_re = addr_hit[309] & reg_re & !reg_error; - assign classb_ctrl_shadowed_we = addr_hit[309] & reg_we & !reg_error; + assign classb_ctrl_shadowed_re = addr_hit[313] & reg_re & !reg_error; + assign classb_ctrl_shadowed_we = addr_hit[313] & reg_we & !reg_error; assign classb_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17409,49 +17589,49 @@ module alert_handler_reg_top ( assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classb_clr_regwen_we = addr_hit[310] & reg_we & !reg_error; + assign classb_clr_regwen_we = addr_hit[314] & reg_we & !reg_error; assign classb_clr_regwen_wd = reg_wdata[0]; - assign classb_clr_shadowed_re = addr_hit[311] & reg_re & !reg_error; - assign classb_clr_shadowed_we = addr_hit[311] & reg_we & !reg_error; + assign classb_clr_shadowed_re = addr_hit[315] & reg_re & !reg_error; + assign classb_clr_shadowed_we = addr_hit[315] & reg_we & !reg_error; assign classb_clr_shadowed_wd = reg_wdata[0]; - assign classb_accum_cnt_re = addr_hit[312] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_re = addr_hit[313] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_we = addr_hit[313] & reg_we & !reg_error; + assign classb_accum_cnt_re = addr_hit[316] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_re = addr_hit[317] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_we = addr_hit[317] & reg_we & !reg_error; assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classb_timeout_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error; - assign classb_timeout_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error; + assign classb_timeout_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error; + assign classb_timeout_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error; assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_crashdump_trigger_shadowed_re = addr_hit[315] & reg_re & !reg_error; - assign classb_crashdump_trigger_shadowed_we = addr_hit[315] & reg_we & !reg_error; + assign classb_crashdump_trigger_shadowed_re = addr_hit[319] & reg_re & !reg_error; + assign classb_crashdump_trigger_shadowed_we = addr_hit[319] & reg_we & !reg_error; assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classb_phase0_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error; - assign classb_phase0_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error; + assign classb_phase0_cyc_shadowed_re = addr_hit[320] & reg_re & !reg_error; + assign classb_phase0_cyc_shadowed_we = addr_hit[320] & reg_we & !reg_error; assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase1_cyc_shadowed_re = addr_hit[317] & reg_re & !reg_error; - assign classb_phase1_cyc_shadowed_we = addr_hit[317] & reg_we & !reg_error; + assign classb_phase1_cyc_shadowed_re = addr_hit[321] & reg_re & !reg_error; + assign classb_phase1_cyc_shadowed_we = addr_hit[321] & reg_we & !reg_error; assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase2_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error; - assign classb_phase2_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error; + assign classb_phase2_cyc_shadowed_re = addr_hit[322] & reg_re & !reg_error; + assign classb_phase2_cyc_shadowed_we = addr_hit[322] & reg_we & !reg_error; assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase3_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error; - assign classb_phase3_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error; + assign classb_phase3_cyc_shadowed_re = addr_hit[323] & reg_re & !reg_error; + assign classb_phase3_cyc_shadowed_we = addr_hit[323] & reg_we & !reg_error; assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_esc_cnt_re = addr_hit[320] & reg_re & !reg_error; - assign classb_state_re = addr_hit[321] & reg_re & !reg_error; - assign classc_regwen_we = addr_hit[322] & reg_we & !reg_error; + assign classb_esc_cnt_re = addr_hit[324] & reg_re & !reg_error; + assign classb_state_re = addr_hit[325] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[326] & reg_we & !reg_error; assign classc_regwen_wd = reg_wdata[0]; - assign classc_ctrl_shadowed_re = addr_hit[323] & reg_re & !reg_error; - assign classc_ctrl_shadowed_we = addr_hit[323] & reg_we & !reg_error; + assign classc_ctrl_shadowed_re = addr_hit[327] & reg_re & !reg_error; + assign classc_ctrl_shadowed_we = addr_hit[327] & reg_we & !reg_error; assign classc_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17472,49 +17652,49 @@ module alert_handler_reg_top ( assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classc_clr_regwen_we = addr_hit[324] & reg_we & !reg_error; + assign classc_clr_regwen_we = addr_hit[328] & reg_we & !reg_error; assign classc_clr_regwen_wd = reg_wdata[0]; - assign classc_clr_shadowed_re = addr_hit[325] & reg_re & !reg_error; - assign classc_clr_shadowed_we = addr_hit[325] & reg_we & !reg_error; + assign classc_clr_shadowed_re = addr_hit[329] & reg_re & !reg_error; + assign classc_clr_shadowed_we = addr_hit[329] & reg_we & !reg_error; assign classc_clr_shadowed_wd = reg_wdata[0]; - assign classc_accum_cnt_re = addr_hit[326] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_re = addr_hit[327] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_we = addr_hit[327] & reg_we & !reg_error; + assign classc_accum_cnt_re = addr_hit[330] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_re = addr_hit[331] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_we = addr_hit[331] & reg_we & !reg_error; assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classc_timeout_cyc_shadowed_re = addr_hit[328] & reg_re & !reg_error; - assign classc_timeout_cyc_shadowed_we = addr_hit[328] & reg_we & !reg_error; + assign classc_timeout_cyc_shadowed_re = addr_hit[332] & reg_re & !reg_error; + assign classc_timeout_cyc_shadowed_we = addr_hit[332] & reg_we & !reg_error; assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_crashdump_trigger_shadowed_re = addr_hit[329] & reg_re & !reg_error; - assign classc_crashdump_trigger_shadowed_we = addr_hit[329] & reg_we & !reg_error; + assign classc_crashdump_trigger_shadowed_re = addr_hit[333] & reg_re & !reg_error; + assign classc_crashdump_trigger_shadowed_we = addr_hit[333] & reg_we & !reg_error; assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classc_phase0_cyc_shadowed_re = addr_hit[330] & reg_re & !reg_error; - assign classc_phase0_cyc_shadowed_we = addr_hit[330] & reg_we & !reg_error; + assign classc_phase0_cyc_shadowed_re = addr_hit[334] & reg_re & !reg_error; + assign classc_phase0_cyc_shadowed_we = addr_hit[334] & reg_we & !reg_error; assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase1_cyc_shadowed_re = addr_hit[331] & reg_re & !reg_error; - assign classc_phase1_cyc_shadowed_we = addr_hit[331] & reg_we & !reg_error; + assign classc_phase1_cyc_shadowed_re = addr_hit[335] & reg_re & !reg_error; + assign classc_phase1_cyc_shadowed_we = addr_hit[335] & reg_we & !reg_error; assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase2_cyc_shadowed_re = addr_hit[332] & reg_re & !reg_error; - assign classc_phase2_cyc_shadowed_we = addr_hit[332] & reg_we & !reg_error; + assign classc_phase2_cyc_shadowed_re = addr_hit[336] & reg_re & !reg_error; + assign classc_phase2_cyc_shadowed_we = addr_hit[336] & reg_we & !reg_error; assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase3_cyc_shadowed_re = addr_hit[333] & reg_re & !reg_error; - assign classc_phase3_cyc_shadowed_we = addr_hit[333] & reg_we & !reg_error; + assign classc_phase3_cyc_shadowed_re = addr_hit[337] & reg_re & !reg_error; + assign classc_phase3_cyc_shadowed_we = addr_hit[337] & reg_we & !reg_error; assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_esc_cnt_re = addr_hit[334] & reg_re & !reg_error; - assign classc_state_re = addr_hit[335] & reg_re & !reg_error; - assign classd_regwen_we = addr_hit[336] & reg_we & !reg_error; + assign classc_esc_cnt_re = addr_hit[338] & reg_re & !reg_error; + assign classc_state_re = addr_hit[339] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[340] & reg_we & !reg_error; assign classd_regwen_wd = reg_wdata[0]; - assign classd_ctrl_shadowed_re = addr_hit[337] & reg_re & !reg_error; - assign classd_ctrl_shadowed_we = addr_hit[337] & reg_we & !reg_error; + assign classd_ctrl_shadowed_re = addr_hit[341] & reg_re & !reg_error; + assign classd_ctrl_shadowed_we = addr_hit[341] & reg_we & !reg_error; assign classd_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17535,44 +17715,44 @@ module alert_handler_reg_top ( assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classd_clr_regwen_we = addr_hit[338] & reg_we & !reg_error; + assign classd_clr_regwen_we = addr_hit[342] & reg_we & !reg_error; assign classd_clr_regwen_wd = reg_wdata[0]; - assign classd_clr_shadowed_re = addr_hit[339] & reg_re & !reg_error; - assign classd_clr_shadowed_we = addr_hit[339] & reg_we & !reg_error; + assign classd_clr_shadowed_re = addr_hit[343] & reg_re & !reg_error; + assign classd_clr_shadowed_we = addr_hit[343] & reg_we & !reg_error; assign classd_clr_shadowed_wd = reg_wdata[0]; - assign classd_accum_cnt_re = addr_hit[340] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_re = addr_hit[341] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_we = addr_hit[341] & reg_we & !reg_error; + assign classd_accum_cnt_re = addr_hit[344] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_re = addr_hit[345] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_we = addr_hit[345] & reg_we & !reg_error; assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classd_timeout_cyc_shadowed_re = addr_hit[342] & reg_re & !reg_error; - assign classd_timeout_cyc_shadowed_we = addr_hit[342] & reg_we & !reg_error; + assign classd_timeout_cyc_shadowed_re = addr_hit[346] & reg_re & !reg_error; + assign classd_timeout_cyc_shadowed_we = addr_hit[346] & reg_we & !reg_error; assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_crashdump_trigger_shadowed_re = addr_hit[343] & reg_re & !reg_error; - assign classd_crashdump_trigger_shadowed_we = addr_hit[343] & reg_we & !reg_error; + assign classd_crashdump_trigger_shadowed_re = addr_hit[347] & reg_re & !reg_error; + assign classd_crashdump_trigger_shadowed_we = addr_hit[347] & reg_we & !reg_error; assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classd_phase0_cyc_shadowed_re = addr_hit[344] & reg_re & !reg_error; - assign classd_phase0_cyc_shadowed_we = addr_hit[344] & reg_we & !reg_error; + assign classd_phase0_cyc_shadowed_re = addr_hit[348] & reg_re & !reg_error; + assign classd_phase0_cyc_shadowed_we = addr_hit[348] & reg_we & !reg_error; assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase1_cyc_shadowed_re = addr_hit[345] & reg_re & !reg_error; - assign classd_phase1_cyc_shadowed_we = addr_hit[345] & reg_we & !reg_error; + assign classd_phase1_cyc_shadowed_re = addr_hit[349] & reg_re & !reg_error; + assign classd_phase1_cyc_shadowed_we = addr_hit[349] & reg_we & !reg_error; assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase2_cyc_shadowed_re = addr_hit[346] & reg_re & !reg_error; - assign classd_phase2_cyc_shadowed_we = addr_hit[346] & reg_we & !reg_error; + assign classd_phase2_cyc_shadowed_re = addr_hit[350] & reg_re & !reg_error; + assign classd_phase2_cyc_shadowed_we = addr_hit[350] & reg_we & !reg_error; assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase3_cyc_shadowed_re = addr_hit[347] & reg_re & !reg_error; - assign classd_phase3_cyc_shadowed_we = addr_hit[347] & reg_we & !reg_error; + assign classd_phase3_cyc_shadowed_re = addr_hit[351] & reg_re & !reg_error; + assign classd_phase3_cyc_shadowed_we = addr_hit[351] & reg_we & !reg_error; assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_esc_cnt_re = addr_hit[348] & reg_re & !reg_error; - assign classd_state_re = addr_hit[349] & reg_re & !reg_error; + assign classd_esc_cnt_re = addr_hit[352] & reg_re & !reg_error; + assign classd_state_re = addr_hit[353] & reg_re & !reg_error; // Assign write-enables to checker logic vector. always_comb begin @@ -17648,285 +17828,289 @@ module alert_handler_reg_top ( reg_we_check[68] = alert_regwen_62_we; reg_we_check[69] = alert_regwen_63_we; reg_we_check[70] = alert_regwen_64_we; - reg_we_check[71] = alert_en_shadowed_0_gated_we; - reg_we_check[72] = alert_en_shadowed_1_gated_we; - reg_we_check[73] = alert_en_shadowed_2_gated_we; - reg_we_check[74] = alert_en_shadowed_3_gated_we; - reg_we_check[75] = alert_en_shadowed_4_gated_we; - reg_we_check[76] = alert_en_shadowed_5_gated_we; - reg_we_check[77] = alert_en_shadowed_6_gated_we; - reg_we_check[78] = alert_en_shadowed_7_gated_we; - reg_we_check[79] = alert_en_shadowed_8_gated_we; - reg_we_check[80] = alert_en_shadowed_9_gated_we; - reg_we_check[81] = alert_en_shadowed_10_gated_we; - reg_we_check[82] = alert_en_shadowed_11_gated_we; - reg_we_check[83] = alert_en_shadowed_12_gated_we; - reg_we_check[84] = alert_en_shadowed_13_gated_we; - reg_we_check[85] = alert_en_shadowed_14_gated_we; - reg_we_check[86] = alert_en_shadowed_15_gated_we; - reg_we_check[87] = alert_en_shadowed_16_gated_we; - reg_we_check[88] = alert_en_shadowed_17_gated_we; - reg_we_check[89] = alert_en_shadowed_18_gated_we; - reg_we_check[90] = alert_en_shadowed_19_gated_we; - reg_we_check[91] = alert_en_shadowed_20_gated_we; - reg_we_check[92] = alert_en_shadowed_21_gated_we; - reg_we_check[93] = alert_en_shadowed_22_gated_we; - reg_we_check[94] = alert_en_shadowed_23_gated_we; - reg_we_check[95] = alert_en_shadowed_24_gated_we; - reg_we_check[96] = alert_en_shadowed_25_gated_we; - reg_we_check[97] = alert_en_shadowed_26_gated_we; - reg_we_check[98] = alert_en_shadowed_27_gated_we; - reg_we_check[99] = alert_en_shadowed_28_gated_we; - reg_we_check[100] = alert_en_shadowed_29_gated_we; - reg_we_check[101] = alert_en_shadowed_30_gated_we; - reg_we_check[102] = alert_en_shadowed_31_gated_we; - reg_we_check[103] = alert_en_shadowed_32_gated_we; - reg_we_check[104] = alert_en_shadowed_33_gated_we; - reg_we_check[105] = alert_en_shadowed_34_gated_we; - reg_we_check[106] = alert_en_shadowed_35_gated_we; - reg_we_check[107] = alert_en_shadowed_36_gated_we; - reg_we_check[108] = alert_en_shadowed_37_gated_we; - reg_we_check[109] = alert_en_shadowed_38_gated_we; - reg_we_check[110] = alert_en_shadowed_39_gated_we; - reg_we_check[111] = alert_en_shadowed_40_gated_we; - reg_we_check[112] = alert_en_shadowed_41_gated_we; - reg_we_check[113] = alert_en_shadowed_42_gated_we; - reg_we_check[114] = alert_en_shadowed_43_gated_we; - reg_we_check[115] = alert_en_shadowed_44_gated_we; - reg_we_check[116] = alert_en_shadowed_45_gated_we; - reg_we_check[117] = alert_en_shadowed_46_gated_we; - reg_we_check[118] = alert_en_shadowed_47_gated_we; - reg_we_check[119] = alert_en_shadowed_48_gated_we; - reg_we_check[120] = alert_en_shadowed_49_gated_we; - reg_we_check[121] = alert_en_shadowed_50_gated_we; - reg_we_check[122] = alert_en_shadowed_51_gated_we; - reg_we_check[123] = alert_en_shadowed_52_gated_we; - reg_we_check[124] = alert_en_shadowed_53_gated_we; - reg_we_check[125] = alert_en_shadowed_54_gated_we; - reg_we_check[126] = alert_en_shadowed_55_gated_we; - reg_we_check[127] = alert_en_shadowed_56_gated_we; - reg_we_check[128] = alert_en_shadowed_57_gated_we; - reg_we_check[129] = alert_en_shadowed_58_gated_we; - reg_we_check[130] = alert_en_shadowed_59_gated_we; - reg_we_check[131] = alert_en_shadowed_60_gated_we; - reg_we_check[132] = alert_en_shadowed_61_gated_we; - reg_we_check[133] = alert_en_shadowed_62_gated_we; - reg_we_check[134] = alert_en_shadowed_63_gated_we; - reg_we_check[135] = alert_en_shadowed_64_gated_we; - reg_we_check[136] = alert_class_shadowed_0_gated_we; - reg_we_check[137] = alert_class_shadowed_1_gated_we; - reg_we_check[138] = alert_class_shadowed_2_gated_we; - reg_we_check[139] = alert_class_shadowed_3_gated_we; - reg_we_check[140] = alert_class_shadowed_4_gated_we; - reg_we_check[141] = alert_class_shadowed_5_gated_we; - reg_we_check[142] = alert_class_shadowed_6_gated_we; - reg_we_check[143] = alert_class_shadowed_7_gated_we; - reg_we_check[144] = alert_class_shadowed_8_gated_we; - reg_we_check[145] = alert_class_shadowed_9_gated_we; - reg_we_check[146] = alert_class_shadowed_10_gated_we; - reg_we_check[147] = alert_class_shadowed_11_gated_we; - reg_we_check[148] = alert_class_shadowed_12_gated_we; - reg_we_check[149] = alert_class_shadowed_13_gated_we; - reg_we_check[150] = alert_class_shadowed_14_gated_we; - reg_we_check[151] = alert_class_shadowed_15_gated_we; - reg_we_check[152] = alert_class_shadowed_16_gated_we; - reg_we_check[153] = alert_class_shadowed_17_gated_we; - reg_we_check[154] = alert_class_shadowed_18_gated_we; - reg_we_check[155] = alert_class_shadowed_19_gated_we; - reg_we_check[156] = alert_class_shadowed_20_gated_we; - reg_we_check[157] = alert_class_shadowed_21_gated_we; - reg_we_check[158] = alert_class_shadowed_22_gated_we; - reg_we_check[159] = alert_class_shadowed_23_gated_we; - reg_we_check[160] = alert_class_shadowed_24_gated_we; - reg_we_check[161] = alert_class_shadowed_25_gated_we; - reg_we_check[162] = alert_class_shadowed_26_gated_we; - reg_we_check[163] = alert_class_shadowed_27_gated_we; - reg_we_check[164] = alert_class_shadowed_28_gated_we; - reg_we_check[165] = alert_class_shadowed_29_gated_we; - reg_we_check[166] = alert_class_shadowed_30_gated_we; - reg_we_check[167] = alert_class_shadowed_31_gated_we; - reg_we_check[168] = alert_class_shadowed_32_gated_we; - reg_we_check[169] = alert_class_shadowed_33_gated_we; - reg_we_check[170] = alert_class_shadowed_34_gated_we; - reg_we_check[171] = alert_class_shadowed_35_gated_we; - reg_we_check[172] = alert_class_shadowed_36_gated_we; - reg_we_check[173] = alert_class_shadowed_37_gated_we; - reg_we_check[174] = alert_class_shadowed_38_gated_we; - reg_we_check[175] = alert_class_shadowed_39_gated_we; - reg_we_check[176] = alert_class_shadowed_40_gated_we; - reg_we_check[177] = alert_class_shadowed_41_gated_we; - reg_we_check[178] = alert_class_shadowed_42_gated_we; - reg_we_check[179] = alert_class_shadowed_43_gated_we; - reg_we_check[180] = alert_class_shadowed_44_gated_we; - reg_we_check[181] = alert_class_shadowed_45_gated_we; - reg_we_check[182] = alert_class_shadowed_46_gated_we; - reg_we_check[183] = alert_class_shadowed_47_gated_we; - reg_we_check[184] = alert_class_shadowed_48_gated_we; - reg_we_check[185] = alert_class_shadowed_49_gated_we; - reg_we_check[186] = alert_class_shadowed_50_gated_we; - reg_we_check[187] = alert_class_shadowed_51_gated_we; - reg_we_check[188] = alert_class_shadowed_52_gated_we; - reg_we_check[189] = alert_class_shadowed_53_gated_we; - reg_we_check[190] = alert_class_shadowed_54_gated_we; - reg_we_check[191] = alert_class_shadowed_55_gated_we; - reg_we_check[192] = alert_class_shadowed_56_gated_we; - reg_we_check[193] = alert_class_shadowed_57_gated_we; - reg_we_check[194] = alert_class_shadowed_58_gated_we; - reg_we_check[195] = alert_class_shadowed_59_gated_we; - reg_we_check[196] = alert_class_shadowed_60_gated_we; - reg_we_check[197] = alert_class_shadowed_61_gated_we; - reg_we_check[198] = alert_class_shadowed_62_gated_we; - reg_we_check[199] = alert_class_shadowed_63_gated_we; - reg_we_check[200] = alert_class_shadowed_64_gated_we; - reg_we_check[201] = alert_cause_0_we; - reg_we_check[202] = alert_cause_1_we; - reg_we_check[203] = alert_cause_2_we; - reg_we_check[204] = alert_cause_3_we; - reg_we_check[205] = alert_cause_4_we; - reg_we_check[206] = alert_cause_5_we; - reg_we_check[207] = alert_cause_6_we; - reg_we_check[208] = alert_cause_7_we; - reg_we_check[209] = alert_cause_8_we; - reg_we_check[210] = alert_cause_9_we; - reg_we_check[211] = alert_cause_10_we; - reg_we_check[212] = alert_cause_11_we; - reg_we_check[213] = alert_cause_12_we; - reg_we_check[214] = alert_cause_13_we; - reg_we_check[215] = alert_cause_14_we; - reg_we_check[216] = alert_cause_15_we; - reg_we_check[217] = alert_cause_16_we; - reg_we_check[218] = alert_cause_17_we; - reg_we_check[219] = alert_cause_18_we; - reg_we_check[220] = alert_cause_19_we; - reg_we_check[221] = alert_cause_20_we; - reg_we_check[222] = alert_cause_21_we; - reg_we_check[223] = alert_cause_22_we; - reg_we_check[224] = alert_cause_23_we; - reg_we_check[225] = alert_cause_24_we; - reg_we_check[226] = alert_cause_25_we; - reg_we_check[227] = alert_cause_26_we; - reg_we_check[228] = alert_cause_27_we; - reg_we_check[229] = alert_cause_28_we; - reg_we_check[230] = alert_cause_29_we; - reg_we_check[231] = alert_cause_30_we; - reg_we_check[232] = alert_cause_31_we; - reg_we_check[233] = alert_cause_32_we; - reg_we_check[234] = alert_cause_33_we; - reg_we_check[235] = alert_cause_34_we; - reg_we_check[236] = alert_cause_35_we; - reg_we_check[237] = alert_cause_36_we; - reg_we_check[238] = alert_cause_37_we; - reg_we_check[239] = alert_cause_38_we; - reg_we_check[240] = alert_cause_39_we; - reg_we_check[241] = alert_cause_40_we; - reg_we_check[242] = alert_cause_41_we; - reg_we_check[243] = alert_cause_42_we; - reg_we_check[244] = alert_cause_43_we; - reg_we_check[245] = alert_cause_44_we; - reg_we_check[246] = alert_cause_45_we; - reg_we_check[247] = alert_cause_46_we; - reg_we_check[248] = alert_cause_47_we; - reg_we_check[249] = alert_cause_48_we; - reg_we_check[250] = alert_cause_49_we; - reg_we_check[251] = alert_cause_50_we; - reg_we_check[252] = alert_cause_51_we; - reg_we_check[253] = alert_cause_52_we; - reg_we_check[254] = alert_cause_53_we; - reg_we_check[255] = alert_cause_54_we; - reg_we_check[256] = alert_cause_55_we; - reg_we_check[257] = alert_cause_56_we; - reg_we_check[258] = alert_cause_57_we; - reg_we_check[259] = alert_cause_58_we; - reg_we_check[260] = alert_cause_59_we; - reg_we_check[261] = alert_cause_60_we; - reg_we_check[262] = alert_cause_61_we; - reg_we_check[263] = alert_cause_62_we; - reg_we_check[264] = alert_cause_63_we; - reg_we_check[265] = alert_cause_64_we; - reg_we_check[266] = loc_alert_regwen_0_we; - reg_we_check[267] = loc_alert_regwen_1_we; - reg_we_check[268] = loc_alert_regwen_2_we; - reg_we_check[269] = loc_alert_regwen_3_we; - reg_we_check[270] = loc_alert_regwen_4_we; - reg_we_check[271] = loc_alert_regwen_5_we; - reg_we_check[272] = loc_alert_regwen_6_we; - reg_we_check[273] = loc_alert_en_shadowed_0_gated_we; - reg_we_check[274] = loc_alert_en_shadowed_1_gated_we; - reg_we_check[275] = loc_alert_en_shadowed_2_gated_we; - reg_we_check[276] = loc_alert_en_shadowed_3_gated_we; - reg_we_check[277] = loc_alert_en_shadowed_4_gated_we; - reg_we_check[278] = loc_alert_en_shadowed_5_gated_we; - reg_we_check[279] = loc_alert_en_shadowed_6_gated_we; - reg_we_check[280] = loc_alert_class_shadowed_0_gated_we; - reg_we_check[281] = loc_alert_class_shadowed_1_gated_we; - reg_we_check[282] = loc_alert_class_shadowed_2_gated_we; - reg_we_check[283] = loc_alert_class_shadowed_3_gated_we; - reg_we_check[284] = loc_alert_class_shadowed_4_gated_we; - reg_we_check[285] = loc_alert_class_shadowed_5_gated_we; - reg_we_check[286] = loc_alert_class_shadowed_6_gated_we; - reg_we_check[287] = loc_alert_cause_0_we; - reg_we_check[288] = loc_alert_cause_1_we; - reg_we_check[289] = loc_alert_cause_2_we; - reg_we_check[290] = loc_alert_cause_3_we; - reg_we_check[291] = loc_alert_cause_4_we; - reg_we_check[292] = loc_alert_cause_5_we; - reg_we_check[293] = loc_alert_cause_6_we; - reg_we_check[294] = classa_regwen_we; - reg_we_check[295] = classa_ctrl_shadowed_gated_we; - reg_we_check[296] = classa_clr_regwen_we; - reg_we_check[297] = classa_clr_shadowed_gated_we; - reg_we_check[298] = 1'b0; - reg_we_check[299] = classa_accum_thresh_shadowed_gated_we; - reg_we_check[300] = classa_timeout_cyc_shadowed_gated_we; - reg_we_check[301] = classa_crashdump_trigger_shadowed_gated_we; - reg_we_check[302] = classa_phase0_cyc_shadowed_gated_we; - reg_we_check[303] = classa_phase1_cyc_shadowed_gated_we; - reg_we_check[304] = classa_phase2_cyc_shadowed_gated_we; - reg_we_check[305] = classa_phase3_cyc_shadowed_gated_we; - reg_we_check[306] = 1'b0; - reg_we_check[307] = 1'b0; - reg_we_check[308] = classb_regwen_we; - reg_we_check[309] = classb_ctrl_shadowed_gated_we; - reg_we_check[310] = classb_clr_regwen_we; - reg_we_check[311] = classb_clr_shadowed_gated_we; - reg_we_check[312] = 1'b0; - reg_we_check[313] = classb_accum_thresh_shadowed_gated_we; - reg_we_check[314] = classb_timeout_cyc_shadowed_gated_we; - reg_we_check[315] = classb_crashdump_trigger_shadowed_gated_we; - reg_we_check[316] = classb_phase0_cyc_shadowed_gated_we; - reg_we_check[317] = classb_phase1_cyc_shadowed_gated_we; - reg_we_check[318] = classb_phase2_cyc_shadowed_gated_we; - reg_we_check[319] = classb_phase3_cyc_shadowed_gated_we; - reg_we_check[320] = 1'b0; - reg_we_check[321] = 1'b0; - reg_we_check[322] = classc_regwen_we; - reg_we_check[323] = classc_ctrl_shadowed_gated_we; - reg_we_check[324] = classc_clr_regwen_we; - reg_we_check[325] = classc_clr_shadowed_gated_we; - reg_we_check[326] = 1'b0; - reg_we_check[327] = classc_accum_thresh_shadowed_gated_we; - reg_we_check[328] = classc_timeout_cyc_shadowed_gated_we; - reg_we_check[329] = classc_crashdump_trigger_shadowed_gated_we; - reg_we_check[330] = classc_phase0_cyc_shadowed_gated_we; - reg_we_check[331] = classc_phase1_cyc_shadowed_gated_we; - reg_we_check[332] = classc_phase2_cyc_shadowed_gated_we; - reg_we_check[333] = classc_phase3_cyc_shadowed_gated_we; - reg_we_check[334] = 1'b0; - reg_we_check[335] = 1'b0; - reg_we_check[336] = classd_regwen_we; - reg_we_check[337] = classd_ctrl_shadowed_gated_we; - reg_we_check[338] = classd_clr_regwen_we; - reg_we_check[339] = classd_clr_shadowed_gated_we; - reg_we_check[340] = 1'b0; - reg_we_check[341] = classd_accum_thresh_shadowed_gated_we; - reg_we_check[342] = classd_timeout_cyc_shadowed_gated_we; - reg_we_check[343] = classd_crashdump_trigger_shadowed_gated_we; - reg_we_check[344] = classd_phase0_cyc_shadowed_gated_we; - reg_we_check[345] = classd_phase1_cyc_shadowed_gated_we; - reg_we_check[346] = classd_phase2_cyc_shadowed_gated_we; - reg_we_check[347] = classd_phase3_cyc_shadowed_gated_we; - reg_we_check[348] = 1'b0; - reg_we_check[349] = 1'b0; + reg_we_check[71] = alert_regwen_65_we; + reg_we_check[72] = alert_en_shadowed_0_gated_we; + reg_we_check[73] = alert_en_shadowed_1_gated_we; + reg_we_check[74] = alert_en_shadowed_2_gated_we; + reg_we_check[75] = alert_en_shadowed_3_gated_we; + reg_we_check[76] = alert_en_shadowed_4_gated_we; + reg_we_check[77] = alert_en_shadowed_5_gated_we; + reg_we_check[78] = alert_en_shadowed_6_gated_we; + reg_we_check[79] = alert_en_shadowed_7_gated_we; + reg_we_check[80] = alert_en_shadowed_8_gated_we; + reg_we_check[81] = alert_en_shadowed_9_gated_we; + reg_we_check[82] = alert_en_shadowed_10_gated_we; + reg_we_check[83] = alert_en_shadowed_11_gated_we; + reg_we_check[84] = alert_en_shadowed_12_gated_we; + reg_we_check[85] = alert_en_shadowed_13_gated_we; + reg_we_check[86] = alert_en_shadowed_14_gated_we; + reg_we_check[87] = alert_en_shadowed_15_gated_we; + reg_we_check[88] = alert_en_shadowed_16_gated_we; + reg_we_check[89] = alert_en_shadowed_17_gated_we; + reg_we_check[90] = alert_en_shadowed_18_gated_we; + reg_we_check[91] = alert_en_shadowed_19_gated_we; + reg_we_check[92] = alert_en_shadowed_20_gated_we; + reg_we_check[93] = alert_en_shadowed_21_gated_we; + reg_we_check[94] = alert_en_shadowed_22_gated_we; + reg_we_check[95] = alert_en_shadowed_23_gated_we; + reg_we_check[96] = alert_en_shadowed_24_gated_we; + reg_we_check[97] = alert_en_shadowed_25_gated_we; + reg_we_check[98] = alert_en_shadowed_26_gated_we; + reg_we_check[99] = alert_en_shadowed_27_gated_we; + reg_we_check[100] = alert_en_shadowed_28_gated_we; + reg_we_check[101] = alert_en_shadowed_29_gated_we; + reg_we_check[102] = alert_en_shadowed_30_gated_we; + reg_we_check[103] = alert_en_shadowed_31_gated_we; + reg_we_check[104] = alert_en_shadowed_32_gated_we; + reg_we_check[105] = alert_en_shadowed_33_gated_we; + reg_we_check[106] = alert_en_shadowed_34_gated_we; + reg_we_check[107] = alert_en_shadowed_35_gated_we; + reg_we_check[108] = alert_en_shadowed_36_gated_we; + reg_we_check[109] = alert_en_shadowed_37_gated_we; + reg_we_check[110] = alert_en_shadowed_38_gated_we; + reg_we_check[111] = alert_en_shadowed_39_gated_we; + reg_we_check[112] = alert_en_shadowed_40_gated_we; + reg_we_check[113] = alert_en_shadowed_41_gated_we; + reg_we_check[114] = alert_en_shadowed_42_gated_we; + reg_we_check[115] = alert_en_shadowed_43_gated_we; + reg_we_check[116] = alert_en_shadowed_44_gated_we; + reg_we_check[117] = alert_en_shadowed_45_gated_we; + reg_we_check[118] = alert_en_shadowed_46_gated_we; + reg_we_check[119] = alert_en_shadowed_47_gated_we; + reg_we_check[120] = alert_en_shadowed_48_gated_we; + reg_we_check[121] = alert_en_shadowed_49_gated_we; + reg_we_check[122] = alert_en_shadowed_50_gated_we; + reg_we_check[123] = alert_en_shadowed_51_gated_we; + reg_we_check[124] = alert_en_shadowed_52_gated_we; + reg_we_check[125] = alert_en_shadowed_53_gated_we; + reg_we_check[126] = alert_en_shadowed_54_gated_we; + reg_we_check[127] = alert_en_shadowed_55_gated_we; + reg_we_check[128] = alert_en_shadowed_56_gated_we; + reg_we_check[129] = alert_en_shadowed_57_gated_we; + reg_we_check[130] = alert_en_shadowed_58_gated_we; + reg_we_check[131] = alert_en_shadowed_59_gated_we; + reg_we_check[132] = alert_en_shadowed_60_gated_we; + reg_we_check[133] = alert_en_shadowed_61_gated_we; + reg_we_check[134] = alert_en_shadowed_62_gated_we; + reg_we_check[135] = alert_en_shadowed_63_gated_we; + reg_we_check[136] = alert_en_shadowed_64_gated_we; + reg_we_check[137] = alert_en_shadowed_65_gated_we; + reg_we_check[138] = alert_class_shadowed_0_gated_we; + reg_we_check[139] = alert_class_shadowed_1_gated_we; + reg_we_check[140] = alert_class_shadowed_2_gated_we; + reg_we_check[141] = alert_class_shadowed_3_gated_we; + reg_we_check[142] = alert_class_shadowed_4_gated_we; + reg_we_check[143] = alert_class_shadowed_5_gated_we; + reg_we_check[144] = alert_class_shadowed_6_gated_we; + reg_we_check[145] = alert_class_shadowed_7_gated_we; + reg_we_check[146] = alert_class_shadowed_8_gated_we; + reg_we_check[147] = alert_class_shadowed_9_gated_we; + reg_we_check[148] = alert_class_shadowed_10_gated_we; + reg_we_check[149] = alert_class_shadowed_11_gated_we; + reg_we_check[150] = alert_class_shadowed_12_gated_we; + reg_we_check[151] = alert_class_shadowed_13_gated_we; + reg_we_check[152] = alert_class_shadowed_14_gated_we; + reg_we_check[153] = alert_class_shadowed_15_gated_we; + reg_we_check[154] = alert_class_shadowed_16_gated_we; + reg_we_check[155] = alert_class_shadowed_17_gated_we; + reg_we_check[156] = alert_class_shadowed_18_gated_we; + reg_we_check[157] = alert_class_shadowed_19_gated_we; + reg_we_check[158] = alert_class_shadowed_20_gated_we; + reg_we_check[159] = alert_class_shadowed_21_gated_we; + reg_we_check[160] = alert_class_shadowed_22_gated_we; + reg_we_check[161] = alert_class_shadowed_23_gated_we; + reg_we_check[162] = alert_class_shadowed_24_gated_we; + reg_we_check[163] = alert_class_shadowed_25_gated_we; + reg_we_check[164] = alert_class_shadowed_26_gated_we; + reg_we_check[165] = alert_class_shadowed_27_gated_we; + reg_we_check[166] = alert_class_shadowed_28_gated_we; + reg_we_check[167] = alert_class_shadowed_29_gated_we; + reg_we_check[168] = alert_class_shadowed_30_gated_we; + reg_we_check[169] = alert_class_shadowed_31_gated_we; + reg_we_check[170] = alert_class_shadowed_32_gated_we; + reg_we_check[171] = alert_class_shadowed_33_gated_we; + reg_we_check[172] = alert_class_shadowed_34_gated_we; + reg_we_check[173] = alert_class_shadowed_35_gated_we; + reg_we_check[174] = alert_class_shadowed_36_gated_we; + reg_we_check[175] = alert_class_shadowed_37_gated_we; + reg_we_check[176] = alert_class_shadowed_38_gated_we; + reg_we_check[177] = alert_class_shadowed_39_gated_we; + reg_we_check[178] = alert_class_shadowed_40_gated_we; + reg_we_check[179] = alert_class_shadowed_41_gated_we; + reg_we_check[180] = alert_class_shadowed_42_gated_we; + reg_we_check[181] = alert_class_shadowed_43_gated_we; + reg_we_check[182] = alert_class_shadowed_44_gated_we; + reg_we_check[183] = alert_class_shadowed_45_gated_we; + reg_we_check[184] = alert_class_shadowed_46_gated_we; + reg_we_check[185] = alert_class_shadowed_47_gated_we; + reg_we_check[186] = alert_class_shadowed_48_gated_we; + reg_we_check[187] = alert_class_shadowed_49_gated_we; + reg_we_check[188] = alert_class_shadowed_50_gated_we; + reg_we_check[189] = alert_class_shadowed_51_gated_we; + reg_we_check[190] = alert_class_shadowed_52_gated_we; + reg_we_check[191] = alert_class_shadowed_53_gated_we; + reg_we_check[192] = alert_class_shadowed_54_gated_we; + reg_we_check[193] = alert_class_shadowed_55_gated_we; + reg_we_check[194] = alert_class_shadowed_56_gated_we; + reg_we_check[195] = alert_class_shadowed_57_gated_we; + reg_we_check[196] = alert_class_shadowed_58_gated_we; + reg_we_check[197] = alert_class_shadowed_59_gated_we; + reg_we_check[198] = alert_class_shadowed_60_gated_we; + reg_we_check[199] = alert_class_shadowed_61_gated_we; + reg_we_check[200] = alert_class_shadowed_62_gated_we; + reg_we_check[201] = alert_class_shadowed_63_gated_we; + reg_we_check[202] = alert_class_shadowed_64_gated_we; + reg_we_check[203] = alert_class_shadowed_65_gated_we; + reg_we_check[204] = alert_cause_0_we; + reg_we_check[205] = alert_cause_1_we; + reg_we_check[206] = alert_cause_2_we; + reg_we_check[207] = alert_cause_3_we; + reg_we_check[208] = alert_cause_4_we; + reg_we_check[209] = alert_cause_5_we; + reg_we_check[210] = alert_cause_6_we; + reg_we_check[211] = alert_cause_7_we; + reg_we_check[212] = alert_cause_8_we; + reg_we_check[213] = alert_cause_9_we; + reg_we_check[214] = alert_cause_10_we; + reg_we_check[215] = alert_cause_11_we; + reg_we_check[216] = alert_cause_12_we; + reg_we_check[217] = alert_cause_13_we; + reg_we_check[218] = alert_cause_14_we; + reg_we_check[219] = alert_cause_15_we; + reg_we_check[220] = alert_cause_16_we; + reg_we_check[221] = alert_cause_17_we; + reg_we_check[222] = alert_cause_18_we; + reg_we_check[223] = alert_cause_19_we; + reg_we_check[224] = alert_cause_20_we; + reg_we_check[225] = alert_cause_21_we; + reg_we_check[226] = alert_cause_22_we; + reg_we_check[227] = alert_cause_23_we; + reg_we_check[228] = alert_cause_24_we; + reg_we_check[229] = alert_cause_25_we; + reg_we_check[230] = alert_cause_26_we; + reg_we_check[231] = alert_cause_27_we; + reg_we_check[232] = alert_cause_28_we; + reg_we_check[233] = alert_cause_29_we; + reg_we_check[234] = alert_cause_30_we; + reg_we_check[235] = alert_cause_31_we; + reg_we_check[236] = alert_cause_32_we; + reg_we_check[237] = alert_cause_33_we; + reg_we_check[238] = alert_cause_34_we; + reg_we_check[239] = alert_cause_35_we; + reg_we_check[240] = alert_cause_36_we; + reg_we_check[241] = alert_cause_37_we; + reg_we_check[242] = alert_cause_38_we; + reg_we_check[243] = alert_cause_39_we; + reg_we_check[244] = alert_cause_40_we; + reg_we_check[245] = alert_cause_41_we; + reg_we_check[246] = alert_cause_42_we; + reg_we_check[247] = alert_cause_43_we; + reg_we_check[248] = alert_cause_44_we; + reg_we_check[249] = alert_cause_45_we; + reg_we_check[250] = alert_cause_46_we; + reg_we_check[251] = alert_cause_47_we; + reg_we_check[252] = alert_cause_48_we; + reg_we_check[253] = alert_cause_49_we; + reg_we_check[254] = alert_cause_50_we; + reg_we_check[255] = alert_cause_51_we; + reg_we_check[256] = alert_cause_52_we; + reg_we_check[257] = alert_cause_53_we; + reg_we_check[258] = alert_cause_54_we; + reg_we_check[259] = alert_cause_55_we; + reg_we_check[260] = alert_cause_56_we; + reg_we_check[261] = alert_cause_57_we; + reg_we_check[262] = alert_cause_58_we; + reg_we_check[263] = alert_cause_59_we; + reg_we_check[264] = alert_cause_60_we; + reg_we_check[265] = alert_cause_61_we; + reg_we_check[266] = alert_cause_62_we; + reg_we_check[267] = alert_cause_63_we; + reg_we_check[268] = alert_cause_64_we; + reg_we_check[269] = alert_cause_65_we; + reg_we_check[270] = loc_alert_regwen_0_we; + reg_we_check[271] = loc_alert_regwen_1_we; + reg_we_check[272] = loc_alert_regwen_2_we; + reg_we_check[273] = loc_alert_regwen_3_we; + reg_we_check[274] = loc_alert_regwen_4_we; + reg_we_check[275] = loc_alert_regwen_5_we; + reg_we_check[276] = loc_alert_regwen_6_we; + reg_we_check[277] = loc_alert_en_shadowed_0_gated_we; + reg_we_check[278] = loc_alert_en_shadowed_1_gated_we; + reg_we_check[279] = loc_alert_en_shadowed_2_gated_we; + reg_we_check[280] = loc_alert_en_shadowed_3_gated_we; + reg_we_check[281] = loc_alert_en_shadowed_4_gated_we; + reg_we_check[282] = loc_alert_en_shadowed_5_gated_we; + reg_we_check[283] = loc_alert_en_shadowed_6_gated_we; + reg_we_check[284] = loc_alert_class_shadowed_0_gated_we; + reg_we_check[285] = loc_alert_class_shadowed_1_gated_we; + reg_we_check[286] = loc_alert_class_shadowed_2_gated_we; + reg_we_check[287] = loc_alert_class_shadowed_3_gated_we; + reg_we_check[288] = loc_alert_class_shadowed_4_gated_we; + reg_we_check[289] = loc_alert_class_shadowed_5_gated_we; + reg_we_check[290] = loc_alert_class_shadowed_6_gated_we; + reg_we_check[291] = loc_alert_cause_0_we; + reg_we_check[292] = loc_alert_cause_1_we; + reg_we_check[293] = loc_alert_cause_2_we; + reg_we_check[294] = loc_alert_cause_3_we; + reg_we_check[295] = loc_alert_cause_4_we; + reg_we_check[296] = loc_alert_cause_5_we; + reg_we_check[297] = loc_alert_cause_6_we; + reg_we_check[298] = classa_regwen_we; + reg_we_check[299] = classa_ctrl_shadowed_gated_we; + reg_we_check[300] = classa_clr_regwen_we; + reg_we_check[301] = classa_clr_shadowed_gated_we; + reg_we_check[302] = 1'b0; + reg_we_check[303] = classa_accum_thresh_shadowed_gated_we; + reg_we_check[304] = classa_timeout_cyc_shadowed_gated_we; + reg_we_check[305] = classa_crashdump_trigger_shadowed_gated_we; + reg_we_check[306] = classa_phase0_cyc_shadowed_gated_we; + reg_we_check[307] = classa_phase1_cyc_shadowed_gated_we; + reg_we_check[308] = classa_phase2_cyc_shadowed_gated_we; + reg_we_check[309] = classa_phase3_cyc_shadowed_gated_we; + reg_we_check[310] = 1'b0; + reg_we_check[311] = 1'b0; + reg_we_check[312] = classb_regwen_we; + reg_we_check[313] = classb_ctrl_shadowed_gated_we; + reg_we_check[314] = classb_clr_regwen_we; + reg_we_check[315] = classb_clr_shadowed_gated_we; + reg_we_check[316] = 1'b0; + reg_we_check[317] = classb_accum_thresh_shadowed_gated_we; + reg_we_check[318] = classb_timeout_cyc_shadowed_gated_we; + reg_we_check[319] = classb_crashdump_trigger_shadowed_gated_we; + reg_we_check[320] = classb_phase0_cyc_shadowed_gated_we; + reg_we_check[321] = classb_phase1_cyc_shadowed_gated_we; + reg_we_check[322] = classb_phase2_cyc_shadowed_gated_we; + reg_we_check[323] = classb_phase3_cyc_shadowed_gated_we; + reg_we_check[324] = 1'b0; + reg_we_check[325] = 1'b0; + reg_we_check[326] = classc_regwen_we; + reg_we_check[327] = classc_ctrl_shadowed_gated_we; + reg_we_check[328] = classc_clr_regwen_we; + reg_we_check[329] = classc_clr_shadowed_gated_we; + reg_we_check[330] = 1'b0; + reg_we_check[331] = classc_accum_thresh_shadowed_gated_we; + reg_we_check[332] = classc_timeout_cyc_shadowed_gated_we; + reg_we_check[333] = classc_crashdump_trigger_shadowed_gated_we; + reg_we_check[334] = classc_phase0_cyc_shadowed_gated_we; + reg_we_check[335] = classc_phase1_cyc_shadowed_gated_we; + reg_we_check[336] = classc_phase2_cyc_shadowed_gated_we; + reg_we_check[337] = classc_phase3_cyc_shadowed_gated_we; + reg_we_check[338] = 1'b0; + reg_we_check[339] = 1'b0; + reg_we_check[340] = classd_regwen_we; + reg_we_check[341] = classd_ctrl_shadowed_gated_we; + reg_we_check[342] = classd_clr_regwen_we; + reg_we_check[343] = classd_clr_shadowed_gated_we; + reg_we_check[344] = 1'b0; + reg_we_check[345] = classd_accum_thresh_shadowed_gated_we; + reg_we_check[346] = classd_timeout_cyc_shadowed_gated_we; + reg_we_check[347] = classd_crashdump_trigger_shadowed_gated_we; + reg_we_check[348] = classd_phase0_cyc_shadowed_gated_we; + reg_we_check[349] = classd_phase1_cyc_shadowed_gated_we; + reg_we_check[350] = classd_phase2_cyc_shadowed_gated_we; + reg_we_check[351] = classd_phase3_cyc_shadowed_gated_we; + reg_we_check[352] = 1'b0; + reg_we_check[353] = 1'b0; end // Read data return @@ -18227,902 +18411,918 @@ module alert_handler_reg_top ( end addr_hit[71]: begin - reg_rdata_next[0] = alert_en_shadowed_0_qs; + reg_rdata_next[0] = alert_regwen_65_qs; end addr_hit[72]: begin - reg_rdata_next[0] = alert_en_shadowed_1_qs; + reg_rdata_next[0] = alert_en_shadowed_0_qs; end addr_hit[73]: begin - reg_rdata_next[0] = alert_en_shadowed_2_qs; + reg_rdata_next[0] = alert_en_shadowed_1_qs; end addr_hit[74]: begin - reg_rdata_next[0] = alert_en_shadowed_3_qs; + reg_rdata_next[0] = alert_en_shadowed_2_qs; end addr_hit[75]: begin - reg_rdata_next[0] = alert_en_shadowed_4_qs; + reg_rdata_next[0] = alert_en_shadowed_3_qs; end addr_hit[76]: begin - reg_rdata_next[0] = alert_en_shadowed_5_qs; + reg_rdata_next[0] = alert_en_shadowed_4_qs; end addr_hit[77]: begin - reg_rdata_next[0] = alert_en_shadowed_6_qs; + reg_rdata_next[0] = alert_en_shadowed_5_qs; end addr_hit[78]: begin - reg_rdata_next[0] = alert_en_shadowed_7_qs; + reg_rdata_next[0] = alert_en_shadowed_6_qs; end addr_hit[79]: begin - reg_rdata_next[0] = alert_en_shadowed_8_qs; + reg_rdata_next[0] = alert_en_shadowed_7_qs; end addr_hit[80]: begin - reg_rdata_next[0] = alert_en_shadowed_9_qs; + reg_rdata_next[0] = alert_en_shadowed_8_qs; end addr_hit[81]: begin - reg_rdata_next[0] = alert_en_shadowed_10_qs; + reg_rdata_next[0] = alert_en_shadowed_9_qs; end addr_hit[82]: begin - reg_rdata_next[0] = alert_en_shadowed_11_qs; + reg_rdata_next[0] = alert_en_shadowed_10_qs; end addr_hit[83]: begin - reg_rdata_next[0] = alert_en_shadowed_12_qs; + reg_rdata_next[0] = alert_en_shadowed_11_qs; end addr_hit[84]: begin - reg_rdata_next[0] = alert_en_shadowed_13_qs; + reg_rdata_next[0] = alert_en_shadowed_12_qs; end addr_hit[85]: begin - reg_rdata_next[0] = alert_en_shadowed_14_qs; + reg_rdata_next[0] = alert_en_shadowed_13_qs; end addr_hit[86]: begin - reg_rdata_next[0] = alert_en_shadowed_15_qs; + reg_rdata_next[0] = alert_en_shadowed_14_qs; end addr_hit[87]: begin - reg_rdata_next[0] = alert_en_shadowed_16_qs; + reg_rdata_next[0] = alert_en_shadowed_15_qs; end addr_hit[88]: begin - reg_rdata_next[0] = alert_en_shadowed_17_qs; + reg_rdata_next[0] = alert_en_shadowed_16_qs; end addr_hit[89]: begin - reg_rdata_next[0] = alert_en_shadowed_18_qs; + reg_rdata_next[0] = alert_en_shadowed_17_qs; end addr_hit[90]: begin - reg_rdata_next[0] = alert_en_shadowed_19_qs; + reg_rdata_next[0] = alert_en_shadowed_18_qs; end addr_hit[91]: begin - reg_rdata_next[0] = alert_en_shadowed_20_qs; + reg_rdata_next[0] = alert_en_shadowed_19_qs; end addr_hit[92]: begin - reg_rdata_next[0] = alert_en_shadowed_21_qs; + reg_rdata_next[0] = alert_en_shadowed_20_qs; end addr_hit[93]: begin - reg_rdata_next[0] = alert_en_shadowed_22_qs; + reg_rdata_next[0] = alert_en_shadowed_21_qs; end addr_hit[94]: begin - reg_rdata_next[0] = alert_en_shadowed_23_qs; + reg_rdata_next[0] = alert_en_shadowed_22_qs; end addr_hit[95]: begin - reg_rdata_next[0] = alert_en_shadowed_24_qs; + reg_rdata_next[0] = alert_en_shadowed_23_qs; end addr_hit[96]: begin - reg_rdata_next[0] = alert_en_shadowed_25_qs; + reg_rdata_next[0] = alert_en_shadowed_24_qs; end addr_hit[97]: begin - reg_rdata_next[0] = alert_en_shadowed_26_qs; + reg_rdata_next[0] = alert_en_shadowed_25_qs; end addr_hit[98]: begin - reg_rdata_next[0] = alert_en_shadowed_27_qs; + reg_rdata_next[0] = alert_en_shadowed_26_qs; end addr_hit[99]: begin - reg_rdata_next[0] = alert_en_shadowed_28_qs; + reg_rdata_next[0] = alert_en_shadowed_27_qs; end addr_hit[100]: begin - reg_rdata_next[0] = alert_en_shadowed_29_qs; + reg_rdata_next[0] = alert_en_shadowed_28_qs; end addr_hit[101]: begin - reg_rdata_next[0] = alert_en_shadowed_30_qs; + reg_rdata_next[0] = alert_en_shadowed_29_qs; end addr_hit[102]: begin - reg_rdata_next[0] = alert_en_shadowed_31_qs; + reg_rdata_next[0] = alert_en_shadowed_30_qs; end addr_hit[103]: begin - reg_rdata_next[0] = alert_en_shadowed_32_qs; + reg_rdata_next[0] = alert_en_shadowed_31_qs; end addr_hit[104]: begin - reg_rdata_next[0] = alert_en_shadowed_33_qs; + reg_rdata_next[0] = alert_en_shadowed_32_qs; end addr_hit[105]: begin - reg_rdata_next[0] = alert_en_shadowed_34_qs; + reg_rdata_next[0] = alert_en_shadowed_33_qs; end addr_hit[106]: begin - reg_rdata_next[0] = alert_en_shadowed_35_qs; + reg_rdata_next[0] = alert_en_shadowed_34_qs; end addr_hit[107]: begin - reg_rdata_next[0] = alert_en_shadowed_36_qs; + reg_rdata_next[0] = alert_en_shadowed_35_qs; end addr_hit[108]: begin - reg_rdata_next[0] = alert_en_shadowed_37_qs; + reg_rdata_next[0] = alert_en_shadowed_36_qs; end addr_hit[109]: begin - reg_rdata_next[0] = alert_en_shadowed_38_qs; + reg_rdata_next[0] = alert_en_shadowed_37_qs; end addr_hit[110]: begin - reg_rdata_next[0] = alert_en_shadowed_39_qs; + reg_rdata_next[0] = alert_en_shadowed_38_qs; end addr_hit[111]: begin - reg_rdata_next[0] = alert_en_shadowed_40_qs; + reg_rdata_next[0] = alert_en_shadowed_39_qs; end addr_hit[112]: begin - reg_rdata_next[0] = alert_en_shadowed_41_qs; + reg_rdata_next[0] = alert_en_shadowed_40_qs; end addr_hit[113]: begin - reg_rdata_next[0] = alert_en_shadowed_42_qs; + reg_rdata_next[0] = alert_en_shadowed_41_qs; end addr_hit[114]: begin - reg_rdata_next[0] = alert_en_shadowed_43_qs; + reg_rdata_next[0] = alert_en_shadowed_42_qs; end addr_hit[115]: begin - reg_rdata_next[0] = alert_en_shadowed_44_qs; + reg_rdata_next[0] = alert_en_shadowed_43_qs; end addr_hit[116]: begin - reg_rdata_next[0] = alert_en_shadowed_45_qs; + reg_rdata_next[0] = alert_en_shadowed_44_qs; end addr_hit[117]: begin - reg_rdata_next[0] = alert_en_shadowed_46_qs; + reg_rdata_next[0] = alert_en_shadowed_45_qs; end addr_hit[118]: begin - reg_rdata_next[0] = alert_en_shadowed_47_qs; + reg_rdata_next[0] = alert_en_shadowed_46_qs; end addr_hit[119]: begin - reg_rdata_next[0] = alert_en_shadowed_48_qs; + reg_rdata_next[0] = alert_en_shadowed_47_qs; end addr_hit[120]: begin - reg_rdata_next[0] = alert_en_shadowed_49_qs; + reg_rdata_next[0] = alert_en_shadowed_48_qs; end addr_hit[121]: begin - reg_rdata_next[0] = alert_en_shadowed_50_qs; + reg_rdata_next[0] = alert_en_shadowed_49_qs; end addr_hit[122]: begin - reg_rdata_next[0] = alert_en_shadowed_51_qs; + reg_rdata_next[0] = alert_en_shadowed_50_qs; end addr_hit[123]: begin - reg_rdata_next[0] = alert_en_shadowed_52_qs; + reg_rdata_next[0] = alert_en_shadowed_51_qs; end addr_hit[124]: begin - reg_rdata_next[0] = alert_en_shadowed_53_qs; + reg_rdata_next[0] = alert_en_shadowed_52_qs; end addr_hit[125]: begin - reg_rdata_next[0] = alert_en_shadowed_54_qs; + reg_rdata_next[0] = alert_en_shadowed_53_qs; end addr_hit[126]: begin - reg_rdata_next[0] = alert_en_shadowed_55_qs; + reg_rdata_next[0] = alert_en_shadowed_54_qs; end addr_hit[127]: begin - reg_rdata_next[0] = alert_en_shadowed_56_qs; + reg_rdata_next[0] = alert_en_shadowed_55_qs; end addr_hit[128]: begin - reg_rdata_next[0] = alert_en_shadowed_57_qs; + reg_rdata_next[0] = alert_en_shadowed_56_qs; end addr_hit[129]: begin - reg_rdata_next[0] = alert_en_shadowed_58_qs; + reg_rdata_next[0] = alert_en_shadowed_57_qs; end addr_hit[130]: begin - reg_rdata_next[0] = alert_en_shadowed_59_qs; + reg_rdata_next[0] = alert_en_shadowed_58_qs; end addr_hit[131]: begin - reg_rdata_next[0] = alert_en_shadowed_60_qs; + reg_rdata_next[0] = alert_en_shadowed_59_qs; end addr_hit[132]: begin - reg_rdata_next[0] = alert_en_shadowed_61_qs; + reg_rdata_next[0] = alert_en_shadowed_60_qs; end addr_hit[133]: begin - reg_rdata_next[0] = alert_en_shadowed_62_qs; + reg_rdata_next[0] = alert_en_shadowed_61_qs; end addr_hit[134]: begin - reg_rdata_next[0] = alert_en_shadowed_63_qs; + reg_rdata_next[0] = alert_en_shadowed_62_qs; end addr_hit[135]: begin - reg_rdata_next[0] = alert_en_shadowed_64_qs; + reg_rdata_next[0] = alert_en_shadowed_63_qs; end addr_hit[136]: begin - reg_rdata_next[1:0] = alert_class_shadowed_0_qs; + reg_rdata_next[0] = alert_en_shadowed_64_qs; end addr_hit[137]: begin - reg_rdata_next[1:0] = alert_class_shadowed_1_qs; + reg_rdata_next[0] = alert_en_shadowed_65_qs; end addr_hit[138]: begin - reg_rdata_next[1:0] = alert_class_shadowed_2_qs; + reg_rdata_next[1:0] = alert_class_shadowed_0_qs; end addr_hit[139]: begin - reg_rdata_next[1:0] = alert_class_shadowed_3_qs; + reg_rdata_next[1:0] = alert_class_shadowed_1_qs; end addr_hit[140]: begin - reg_rdata_next[1:0] = alert_class_shadowed_4_qs; + reg_rdata_next[1:0] = alert_class_shadowed_2_qs; end addr_hit[141]: begin - reg_rdata_next[1:0] = alert_class_shadowed_5_qs; + reg_rdata_next[1:0] = alert_class_shadowed_3_qs; end addr_hit[142]: begin - reg_rdata_next[1:0] = alert_class_shadowed_6_qs; + reg_rdata_next[1:0] = alert_class_shadowed_4_qs; end addr_hit[143]: begin - reg_rdata_next[1:0] = alert_class_shadowed_7_qs; + reg_rdata_next[1:0] = alert_class_shadowed_5_qs; end addr_hit[144]: begin - reg_rdata_next[1:0] = alert_class_shadowed_8_qs; + reg_rdata_next[1:0] = alert_class_shadowed_6_qs; end addr_hit[145]: begin - reg_rdata_next[1:0] = alert_class_shadowed_9_qs; + reg_rdata_next[1:0] = alert_class_shadowed_7_qs; end addr_hit[146]: begin - reg_rdata_next[1:0] = alert_class_shadowed_10_qs; + reg_rdata_next[1:0] = alert_class_shadowed_8_qs; end addr_hit[147]: begin - reg_rdata_next[1:0] = alert_class_shadowed_11_qs; + reg_rdata_next[1:0] = alert_class_shadowed_9_qs; end addr_hit[148]: begin - reg_rdata_next[1:0] = alert_class_shadowed_12_qs; + reg_rdata_next[1:0] = alert_class_shadowed_10_qs; end addr_hit[149]: begin - reg_rdata_next[1:0] = alert_class_shadowed_13_qs; + reg_rdata_next[1:0] = alert_class_shadowed_11_qs; end addr_hit[150]: begin - reg_rdata_next[1:0] = alert_class_shadowed_14_qs; + reg_rdata_next[1:0] = alert_class_shadowed_12_qs; end addr_hit[151]: begin - reg_rdata_next[1:0] = alert_class_shadowed_15_qs; + reg_rdata_next[1:0] = alert_class_shadowed_13_qs; end addr_hit[152]: begin - reg_rdata_next[1:0] = alert_class_shadowed_16_qs; + reg_rdata_next[1:0] = alert_class_shadowed_14_qs; end addr_hit[153]: begin - reg_rdata_next[1:0] = alert_class_shadowed_17_qs; + reg_rdata_next[1:0] = alert_class_shadowed_15_qs; end addr_hit[154]: begin - reg_rdata_next[1:0] = alert_class_shadowed_18_qs; + reg_rdata_next[1:0] = alert_class_shadowed_16_qs; end addr_hit[155]: begin - reg_rdata_next[1:0] = alert_class_shadowed_19_qs; + reg_rdata_next[1:0] = alert_class_shadowed_17_qs; end addr_hit[156]: begin - reg_rdata_next[1:0] = alert_class_shadowed_20_qs; + reg_rdata_next[1:0] = alert_class_shadowed_18_qs; end addr_hit[157]: begin - reg_rdata_next[1:0] = alert_class_shadowed_21_qs; + reg_rdata_next[1:0] = alert_class_shadowed_19_qs; end addr_hit[158]: begin - reg_rdata_next[1:0] = alert_class_shadowed_22_qs; + reg_rdata_next[1:0] = alert_class_shadowed_20_qs; end addr_hit[159]: begin - reg_rdata_next[1:0] = alert_class_shadowed_23_qs; + reg_rdata_next[1:0] = alert_class_shadowed_21_qs; end addr_hit[160]: begin - reg_rdata_next[1:0] = alert_class_shadowed_24_qs; + reg_rdata_next[1:0] = alert_class_shadowed_22_qs; end addr_hit[161]: begin - reg_rdata_next[1:0] = alert_class_shadowed_25_qs; + reg_rdata_next[1:0] = alert_class_shadowed_23_qs; end addr_hit[162]: begin - reg_rdata_next[1:0] = alert_class_shadowed_26_qs; + reg_rdata_next[1:0] = alert_class_shadowed_24_qs; end addr_hit[163]: begin - reg_rdata_next[1:0] = alert_class_shadowed_27_qs; + reg_rdata_next[1:0] = alert_class_shadowed_25_qs; end addr_hit[164]: begin - reg_rdata_next[1:0] = alert_class_shadowed_28_qs; + reg_rdata_next[1:0] = alert_class_shadowed_26_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = alert_class_shadowed_29_qs; + reg_rdata_next[1:0] = alert_class_shadowed_27_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = alert_class_shadowed_30_qs; + reg_rdata_next[1:0] = alert_class_shadowed_28_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = alert_class_shadowed_31_qs; + reg_rdata_next[1:0] = alert_class_shadowed_29_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = alert_class_shadowed_32_qs; + reg_rdata_next[1:0] = alert_class_shadowed_30_qs; end addr_hit[169]: begin - reg_rdata_next[1:0] = alert_class_shadowed_33_qs; + reg_rdata_next[1:0] = alert_class_shadowed_31_qs; end addr_hit[170]: begin - reg_rdata_next[1:0] = alert_class_shadowed_34_qs; + reg_rdata_next[1:0] = alert_class_shadowed_32_qs; end addr_hit[171]: begin - reg_rdata_next[1:0] = alert_class_shadowed_35_qs; + reg_rdata_next[1:0] = alert_class_shadowed_33_qs; end addr_hit[172]: begin - reg_rdata_next[1:0] = alert_class_shadowed_36_qs; + reg_rdata_next[1:0] = alert_class_shadowed_34_qs; end addr_hit[173]: begin - reg_rdata_next[1:0] = alert_class_shadowed_37_qs; + reg_rdata_next[1:0] = alert_class_shadowed_35_qs; end addr_hit[174]: begin - reg_rdata_next[1:0] = alert_class_shadowed_38_qs; + reg_rdata_next[1:0] = alert_class_shadowed_36_qs; end addr_hit[175]: begin - reg_rdata_next[1:0] = alert_class_shadowed_39_qs; + reg_rdata_next[1:0] = alert_class_shadowed_37_qs; end addr_hit[176]: begin - reg_rdata_next[1:0] = alert_class_shadowed_40_qs; + reg_rdata_next[1:0] = alert_class_shadowed_38_qs; end addr_hit[177]: begin - reg_rdata_next[1:0] = alert_class_shadowed_41_qs; + reg_rdata_next[1:0] = alert_class_shadowed_39_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = alert_class_shadowed_42_qs; + reg_rdata_next[1:0] = alert_class_shadowed_40_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = alert_class_shadowed_43_qs; + reg_rdata_next[1:0] = alert_class_shadowed_41_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = alert_class_shadowed_44_qs; + reg_rdata_next[1:0] = alert_class_shadowed_42_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = alert_class_shadowed_45_qs; + reg_rdata_next[1:0] = alert_class_shadowed_43_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = alert_class_shadowed_46_qs; + reg_rdata_next[1:0] = alert_class_shadowed_44_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = alert_class_shadowed_47_qs; + reg_rdata_next[1:0] = alert_class_shadowed_45_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = alert_class_shadowed_48_qs; + reg_rdata_next[1:0] = alert_class_shadowed_46_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = alert_class_shadowed_49_qs; + reg_rdata_next[1:0] = alert_class_shadowed_47_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = alert_class_shadowed_50_qs; + reg_rdata_next[1:0] = alert_class_shadowed_48_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = alert_class_shadowed_51_qs; + reg_rdata_next[1:0] = alert_class_shadowed_49_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = alert_class_shadowed_52_qs; + reg_rdata_next[1:0] = alert_class_shadowed_50_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = alert_class_shadowed_53_qs; + reg_rdata_next[1:0] = alert_class_shadowed_51_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = alert_class_shadowed_54_qs; + reg_rdata_next[1:0] = alert_class_shadowed_52_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = alert_class_shadowed_55_qs; + reg_rdata_next[1:0] = alert_class_shadowed_53_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = alert_class_shadowed_56_qs; + reg_rdata_next[1:0] = alert_class_shadowed_54_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = alert_class_shadowed_57_qs; + reg_rdata_next[1:0] = alert_class_shadowed_55_qs; end addr_hit[194]: begin - reg_rdata_next[1:0] = alert_class_shadowed_58_qs; + reg_rdata_next[1:0] = alert_class_shadowed_56_qs; end addr_hit[195]: begin - reg_rdata_next[1:0] = alert_class_shadowed_59_qs; + reg_rdata_next[1:0] = alert_class_shadowed_57_qs; end addr_hit[196]: begin - reg_rdata_next[1:0] = alert_class_shadowed_60_qs; + reg_rdata_next[1:0] = alert_class_shadowed_58_qs; end addr_hit[197]: begin - reg_rdata_next[1:0] = alert_class_shadowed_61_qs; + reg_rdata_next[1:0] = alert_class_shadowed_59_qs; end addr_hit[198]: begin - reg_rdata_next[1:0] = alert_class_shadowed_62_qs; + reg_rdata_next[1:0] = alert_class_shadowed_60_qs; end addr_hit[199]: begin - reg_rdata_next[1:0] = alert_class_shadowed_63_qs; + reg_rdata_next[1:0] = alert_class_shadowed_61_qs; end addr_hit[200]: begin - reg_rdata_next[1:0] = alert_class_shadowed_64_qs; + reg_rdata_next[1:0] = alert_class_shadowed_62_qs; end addr_hit[201]: begin - reg_rdata_next[0] = alert_cause_0_qs; + reg_rdata_next[1:0] = alert_class_shadowed_63_qs; end addr_hit[202]: begin - reg_rdata_next[0] = alert_cause_1_qs; + reg_rdata_next[1:0] = alert_class_shadowed_64_qs; end addr_hit[203]: begin - reg_rdata_next[0] = alert_cause_2_qs; + reg_rdata_next[1:0] = alert_class_shadowed_65_qs; end addr_hit[204]: begin - reg_rdata_next[0] = alert_cause_3_qs; + reg_rdata_next[0] = alert_cause_0_qs; end addr_hit[205]: begin - reg_rdata_next[0] = alert_cause_4_qs; + reg_rdata_next[0] = alert_cause_1_qs; end addr_hit[206]: begin - reg_rdata_next[0] = alert_cause_5_qs; + reg_rdata_next[0] = alert_cause_2_qs; end addr_hit[207]: begin - reg_rdata_next[0] = alert_cause_6_qs; + reg_rdata_next[0] = alert_cause_3_qs; end addr_hit[208]: begin - reg_rdata_next[0] = alert_cause_7_qs; + reg_rdata_next[0] = alert_cause_4_qs; end addr_hit[209]: begin - reg_rdata_next[0] = alert_cause_8_qs; + reg_rdata_next[0] = alert_cause_5_qs; end addr_hit[210]: begin - reg_rdata_next[0] = alert_cause_9_qs; + reg_rdata_next[0] = alert_cause_6_qs; end addr_hit[211]: begin - reg_rdata_next[0] = alert_cause_10_qs; + reg_rdata_next[0] = alert_cause_7_qs; end addr_hit[212]: begin - reg_rdata_next[0] = alert_cause_11_qs; + reg_rdata_next[0] = alert_cause_8_qs; end addr_hit[213]: begin - reg_rdata_next[0] = alert_cause_12_qs; + reg_rdata_next[0] = alert_cause_9_qs; end addr_hit[214]: begin - reg_rdata_next[0] = alert_cause_13_qs; + reg_rdata_next[0] = alert_cause_10_qs; end addr_hit[215]: begin - reg_rdata_next[0] = alert_cause_14_qs; + reg_rdata_next[0] = alert_cause_11_qs; end addr_hit[216]: begin - reg_rdata_next[0] = alert_cause_15_qs; + reg_rdata_next[0] = alert_cause_12_qs; end addr_hit[217]: begin - reg_rdata_next[0] = alert_cause_16_qs; + reg_rdata_next[0] = alert_cause_13_qs; end addr_hit[218]: begin - reg_rdata_next[0] = alert_cause_17_qs; + reg_rdata_next[0] = alert_cause_14_qs; end addr_hit[219]: begin - reg_rdata_next[0] = alert_cause_18_qs; + reg_rdata_next[0] = alert_cause_15_qs; end addr_hit[220]: begin - reg_rdata_next[0] = alert_cause_19_qs; + reg_rdata_next[0] = alert_cause_16_qs; end addr_hit[221]: begin - reg_rdata_next[0] = alert_cause_20_qs; + reg_rdata_next[0] = alert_cause_17_qs; end addr_hit[222]: begin - reg_rdata_next[0] = alert_cause_21_qs; + reg_rdata_next[0] = alert_cause_18_qs; end addr_hit[223]: begin - reg_rdata_next[0] = alert_cause_22_qs; + reg_rdata_next[0] = alert_cause_19_qs; end addr_hit[224]: begin - reg_rdata_next[0] = alert_cause_23_qs; + reg_rdata_next[0] = alert_cause_20_qs; end addr_hit[225]: begin - reg_rdata_next[0] = alert_cause_24_qs; + reg_rdata_next[0] = alert_cause_21_qs; end addr_hit[226]: begin - reg_rdata_next[0] = alert_cause_25_qs; + reg_rdata_next[0] = alert_cause_22_qs; end addr_hit[227]: begin - reg_rdata_next[0] = alert_cause_26_qs; + reg_rdata_next[0] = alert_cause_23_qs; end addr_hit[228]: begin - reg_rdata_next[0] = alert_cause_27_qs; + reg_rdata_next[0] = alert_cause_24_qs; end addr_hit[229]: begin - reg_rdata_next[0] = alert_cause_28_qs; + reg_rdata_next[0] = alert_cause_25_qs; end addr_hit[230]: begin - reg_rdata_next[0] = alert_cause_29_qs; + reg_rdata_next[0] = alert_cause_26_qs; end addr_hit[231]: begin - reg_rdata_next[0] = alert_cause_30_qs; + reg_rdata_next[0] = alert_cause_27_qs; end addr_hit[232]: begin - reg_rdata_next[0] = alert_cause_31_qs; + reg_rdata_next[0] = alert_cause_28_qs; end addr_hit[233]: begin - reg_rdata_next[0] = alert_cause_32_qs; + reg_rdata_next[0] = alert_cause_29_qs; end addr_hit[234]: begin - reg_rdata_next[0] = alert_cause_33_qs; + reg_rdata_next[0] = alert_cause_30_qs; end addr_hit[235]: begin - reg_rdata_next[0] = alert_cause_34_qs; + reg_rdata_next[0] = alert_cause_31_qs; end addr_hit[236]: begin - reg_rdata_next[0] = alert_cause_35_qs; + reg_rdata_next[0] = alert_cause_32_qs; end addr_hit[237]: begin - reg_rdata_next[0] = alert_cause_36_qs; + reg_rdata_next[0] = alert_cause_33_qs; end addr_hit[238]: begin - reg_rdata_next[0] = alert_cause_37_qs; + reg_rdata_next[0] = alert_cause_34_qs; end addr_hit[239]: begin - reg_rdata_next[0] = alert_cause_38_qs; + reg_rdata_next[0] = alert_cause_35_qs; end addr_hit[240]: begin - reg_rdata_next[0] = alert_cause_39_qs; + reg_rdata_next[0] = alert_cause_36_qs; end addr_hit[241]: begin - reg_rdata_next[0] = alert_cause_40_qs; + reg_rdata_next[0] = alert_cause_37_qs; end addr_hit[242]: begin - reg_rdata_next[0] = alert_cause_41_qs; + reg_rdata_next[0] = alert_cause_38_qs; end addr_hit[243]: begin - reg_rdata_next[0] = alert_cause_42_qs; + reg_rdata_next[0] = alert_cause_39_qs; end addr_hit[244]: begin - reg_rdata_next[0] = alert_cause_43_qs; + reg_rdata_next[0] = alert_cause_40_qs; end addr_hit[245]: begin - reg_rdata_next[0] = alert_cause_44_qs; + reg_rdata_next[0] = alert_cause_41_qs; end addr_hit[246]: begin - reg_rdata_next[0] = alert_cause_45_qs; + reg_rdata_next[0] = alert_cause_42_qs; end addr_hit[247]: begin - reg_rdata_next[0] = alert_cause_46_qs; + reg_rdata_next[0] = alert_cause_43_qs; end addr_hit[248]: begin - reg_rdata_next[0] = alert_cause_47_qs; + reg_rdata_next[0] = alert_cause_44_qs; end addr_hit[249]: begin - reg_rdata_next[0] = alert_cause_48_qs; + reg_rdata_next[0] = alert_cause_45_qs; end addr_hit[250]: begin - reg_rdata_next[0] = alert_cause_49_qs; + reg_rdata_next[0] = alert_cause_46_qs; end addr_hit[251]: begin - reg_rdata_next[0] = alert_cause_50_qs; + reg_rdata_next[0] = alert_cause_47_qs; end addr_hit[252]: begin - reg_rdata_next[0] = alert_cause_51_qs; + reg_rdata_next[0] = alert_cause_48_qs; end addr_hit[253]: begin - reg_rdata_next[0] = alert_cause_52_qs; + reg_rdata_next[0] = alert_cause_49_qs; end addr_hit[254]: begin - reg_rdata_next[0] = alert_cause_53_qs; + reg_rdata_next[0] = alert_cause_50_qs; end addr_hit[255]: begin - reg_rdata_next[0] = alert_cause_54_qs; + reg_rdata_next[0] = alert_cause_51_qs; end addr_hit[256]: begin - reg_rdata_next[0] = alert_cause_55_qs; + reg_rdata_next[0] = alert_cause_52_qs; end addr_hit[257]: begin - reg_rdata_next[0] = alert_cause_56_qs; + reg_rdata_next[0] = alert_cause_53_qs; end addr_hit[258]: begin - reg_rdata_next[0] = alert_cause_57_qs; + reg_rdata_next[0] = alert_cause_54_qs; end addr_hit[259]: begin - reg_rdata_next[0] = alert_cause_58_qs; + reg_rdata_next[0] = alert_cause_55_qs; end addr_hit[260]: begin - reg_rdata_next[0] = alert_cause_59_qs; + reg_rdata_next[0] = alert_cause_56_qs; end addr_hit[261]: begin - reg_rdata_next[0] = alert_cause_60_qs; + reg_rdata_next[0] = alert_cause_57_qs; end addr_hit[262]: begin - reg_rdata_next[0] = alert_cause_61_qs; + reg_rdata_next[0] = alert_cause_58_qs; end addr_hit[263]: begin - reg_rdata_next[0] = alert_cause_62_qs; + reg_rdata_next[0] = alert_cause_59_qs; end addr_hit[264]: begin - reg_rdata_next[0] = alert_cause_63_qs; + reg_rdata_next[0] = alert_cause_60_qs; end addr_hit[265]: begin - reg_rdata_next[0] = alert_cause_64_qs; + reg_rdata_next[0] = alert_cause_61_qs; end addr_hit[266]: begin - reg_rdata_next[0] = loc_alert_regwen_0_qs; + reg_rdata_next[0] = alert_cause_62_qs; end addr_hit[267]: begin - reg_rdata_next[0] = loc_alert_regwen_1_qs; + reg_rdata_next[0] = alert_cause_63_qs; end addr_hit[268]: begin - reg_rdata_next[0] = loc_alert_regwen_2_qs; + reg_rdata_next[0] = alert_cause_64_qs; end addr_hit[269]: begin - reg_rdata_next[0] = loc_alert_regwen_3_qs; + reg_rdata_next[0] = alert_cause_65_qs; end addr_hit[270]: begin - reg_rdata_next[0] = loc_alert_regwen_4_qs; + reg_rdata_next[0] = loc_alert_regwen_0_qs; end addr_hit[271]: begin - reg_rdata_next[0] = loc_alert_regwen_5_qs; + reg_rdata_next[0] = loc_alert_regwen_1_qs; end addr_hit[272]: begin - reg_rdata_next[0] = loc_alert_regwen_6_qs; + reg_rdata_next[0] = loc_alert_regwen_2_qs; end addr_hit[273]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; + reg_rdata_next[0] = loc_alert_regwen_3_qs; end addr_hit[274]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; + reg_rdata_next[0] = loc_alert_regwen_4_qs; end addr_hit[275]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; + reg_rdata_next[0] = loc_alert_regwen_5_qs; end addr_hit[276]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; + reg_rdata_next[0] = loc_alert_regwen_6_qs; end addr_hit[277]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; end addr_hit[278]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; end addr_hit[279]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; end addr_hit[280]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; end addr_hit[281]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; end addr_hit[282]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; end addr_hit[283]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; end addr_hit[284]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; end addr_hit[285]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; end addr_hit[286]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; end addr_hit[287]: begin - reg_rdata_next[0] = loc_alert_cause_0_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; end addr_hit[288]: begin - reg_rdata_next[0] = loc_alert_cause_1_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; end addr_hit[289]: begin - reg_rdata_next[0] = loc_alert_cause_2_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; end addr_hit[290]: begin - reg_rdata_next[0] = loc_alert_cause_3_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; end addr_hit[291]: begin - reg_rdata_next[0] = loc_alert_cause_4_qs; + reg_rdata_next[0] = loc_alert_cause_0_qs; end addr_hit[292]: begin - reg_rdata_next[0] = loc_alert_cause_5_qs; + reg_rdata_next[0] = loc_alert_cause_1_qs; end addr_hit[293]: begin - reg_rdata_next[0] = loc_alert_cause_6_qs; + reg_rdata_next[0] = loc_alert_cause_2_qs; end addr_hit[294]: begin - reg_rdata_next[0] = classa_regwen_qs; + reg_rdata_next[0] = loc_alert_cause_3_qs; end addr_hit[295]: begin + reg_rdata_next[0] = loc_alert_cause_4_qs; + end + + addr_hit[296]: begin + reg_rdata_next[0] = loc_alert_cause_5_qs; + end + + addr_hit[297]: begin + reg_rdata_next[0] = loc_alert_cause_6_qs; + end + + addr_hit[298]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[299]: begin reg_rdata_next[0] = classa_ctrl_shadowed_en_qs; reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs; @@ -19135,59 +19335,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs; end - addr_hit[296]: begin + addr_hit[300]: begin reg_rdata_next[0] = classa_clr_regwen_qs; end - addr_hit[297]: begin + addr_hit[301]: begin reg_rdata_next[0] = classa_clr_shadowed_qs; end - addr_hit[298]: begin + addr_hit[302]: begin reg_rdata_next[15:0] = classa_accum_cnt_qs; end - addr_hit[299]: begin + addr_hit[303]: begin reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs; end - addr_hit[300]: begin + addr_hit[304]: begin reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs; end - addr_hit[301]: begin + addr_hit[305]: begin reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs; end - addr_hit[302]: begin + addr_hit[306]: begin reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs; end - addr_hit[303]: begin + addr_hit[307]: begin reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs; end - addr_hit[304]: begin + addr_hit[308]: begin reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs; end - addr_hit[305]: begin + addr_hit[309]: begin reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs; end - addr_hit[306]: begin + addr_hit[310]: begin reg_rdata_next[31:0] = classa_esc_cnt_qs; end - addr_hit[307]: begin + addr_hit[311]: begin reg_rdata_next[2:0] = classa_state_qs; end - addr_hit[308]: begin + addr_hit[312]: begin reg_rdata_next[0] = classb_regwen_qs; end - addr_hit[309]: begin + addr_hit[313]: begin reg_rdata_next[0] = classb_ctrl_shadowed_en_qs; reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs; @@ -19200,59 +19400,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs; end - addr_hit[310]: begin + addr_hit[314]: begin reg_rdata_next[0] = classb_clr_regwen_qs; end - addr_hit[311]: begin + addr_hit[315]: begin reg_rdata_next[0] = classb_clr_shadowed_qs; end - addr_hit[312]: begin + addr_hit[316]: begin reg_rdata_next[15:0] = classb_accum_cnt_qs; end - addr_hit[313]: begin + addr_hit[317]: begin reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs; end - addr_hit[314]: begin + addr_hit[318]: begin reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs; end - addr_hit[315]: begin + addr_hit[319]: begin reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs; end - addr_hit[316]: begin + addr_hit[320]: begin reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs; end - addr_hit[317]: begin + addr_hit[321]: begin reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs; end - addr_hit[318]: begin + addr_hit[322]: begin reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs; end - addr_hit[319]: begin + addr_hit[323]: begin reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs; end - addr_hit[320]: begin + addr_hit[324]: begin reg_rdata_next[31:0] = classb_esc_cnt_qs; end - addr_hit[321]: begin + addr_hit[325]: begin reg_rdata_next[2:0] = classb_state_qs; end - addr_hit[322]: begin + addr_hit[326]: begin reg_rdata_next[0] = classc_regwen_qs; end - addr_hit[323]: begin + addr_hit[327]: begin reg_rdata_next[0] = classc_ctrl_shadowed_en_qs; reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs; @@ -19265,59 +19465,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs; end - addr_hit[324]: begin + addr_hit[328]: begin reg_rdata_next[0] = classc_clr_regwen_qs; end - addr_hit[325]: begin + addr_hit[329]: begin reg_rdata_next[0] = classc_clr_shadowed_qs; end - addr_hit[326]: begin + addr_hit[330]: begin reg_rdata_next[15:0] = classc_accum_cnt_qs; end - addr_hit[327]: begin + addr_hit[331]: begin reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs; end - addr_hit[328]: begin + addr_hit[332]: begin reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs; end - addr_hit[329]: begin + addr_hit[333]: begin reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs; end - addr_hit[330]: begin + addr_hit[334]: begin reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs; end - addr_hit[331]: begin + addr_hit[335]: begin reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs; end - addr_hit[332]: begin + addr_hit[336]: begin reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs; end - addr_hit[333]: begin + addr_hit[337]: begin reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs; end - addr_hit[334]: begin + addr_hit[338]: begin reg_rdata_next[31:0] = classc_esc_cnt_qs; end - addr_hit[335]: begin + addr_hit[339]: begin reg_rdata_next[2:0] = classc_state_qs; end - addr_hit[336]: begin + addr_hit[340]: begin reg_rdata_next[0] = classd_regwen_qs; end - addr_hit[337]: begin + addr_hit[341]: begin reg_rdata_next[0] = classd_ctrl_shadowed_en_qs; reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs; @@ -19330,51 +19530,51 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs; end - addr_hit[338]: begin + addr_hit[342]: begin reg_rdata_next[0] = classd_clr_regwen_qs; end - addr_hit[339]: begin + addr_hit[343]: begin reg_rdata_next[0] = classd_clr_shadowed_qs; end - addr_hit[340]: begin + addr_hit[344]: begin reg_rdata_next[15:0] = classd_accum_cnt_qs; end - addr_hit[341]: begin + addr_hit[345]: begin reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs; end - addr_hit[342]: begin + addr_hit[346]: begin reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs; end - addr_hit[343]: begin + addr_hit[347]: begin reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs; end - addr_hit[344]: begin + addr_hit[348]: begin reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs; end - addr_hit[345]: begin + addr_hit[349]: begin reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs; end - addr_hit[346]: begin + addr_hit[350]: begin reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs; end - addr_hit[347]: begin + addr_hit[351]: begin reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs; end - addr_hit[348]: begin + addr_hit[352]: begin reg_rdata_next[31:0] = classd_esc_cnt_qs; end - addr_hit[349]: begin + addr_hit[353]: begin reg_rdata_next[2:0] = classd_state_qs; end @@ -19476,6 +19676,7 @@ module alert_handler_reg_top ( alert_en_shadowed_62_storage_err, alert_en_shadowed_63_storage_err, alert_en_shadowed_64_storage_err, + alert_en_shadowed_65_storage_err, alert_class_shadowed_0_storage_err, alert_class_shadowed_1_storage_err, alert_class_shadowed_2_storage_err, @@ -19541,6 +19742,7 @@ module alert_handler_reg_top ( alert_class_shadowed_62_storage_err, alert_class_shadowed_63_storage_err, alert_class_shadowed_64_storage_err, + alert_class_shadowed_65_storage_err, loc_alert_en_shadowed_0_storage_err, loc_alert_en_shadowed_1_storage_err, loc_alert_en_shadowed_2_storage_err, @@ -19696,6 +19898,7 @@ module alert_handler_reg_top ( alert_en_shadowed_62_update_err, alert_en_shadowed_63_update_err, alert_en_shadowed_64_update_err, + alert_en_shadowed_65_update_err, alert_class_shadowed_0_update_err, alert_class_shadowed_1_update_err, alert_class_shadowed_2_update_err, @@ -19761,6 +19964,7 @@ module alert_handler_reg_top ( alert_class_shadowed_62_update_err, alert_class_shadowed_63_update_err, alert_class_shadowed_64_update_err, + alert_class_shadowed_65_update_err, loc_alert_en_shadowed_0_update_err, loc_alert_en_shadowed_1_update_err, loc_alert_en_shadowed_2_update_err, diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson index 208dc8aad61965..34600121cdce73 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson +++ b/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson @@ -110,7 +110,7 @@ { name: "NumSwResets", desc: "Number of software resets", type: "int", - default: "8", + default: "9", local: "true" }, @@ -194,6 +194,12 @@ { name: "RSTMGR.SW_RST.I2C2_ENABLE", desc: "Enable reset of I2C2 peripheral via CSR." } + { name: "RSTMGR.SW_RST.I2C3_REQUEST", + desc: "Trigger reset of I2C3 peripheral via CSR." + } + { name: "RSTMGR.SW_RST.I2C3_ENABLE", + desc: "Enable reset of I2C3 peripheral via CSR." + } { name: "RSTMGR.RESET_INFO.CAPTURE", desc: "Capture information about the causes of a reset." } diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson index c841329d6d3c24..9412af364c6fd3 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson @@ -69,6 +69,7 @@ i2c0 i2c1 i2c2 + i2c3 ] output_rsts: [ @@ -385,6 +386,20 @@ parent: lc_src clock: io_div4 } + { + name: i2c3 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c3_n + parent: lc_src + clock: io_div4 + } ] leaf_rsts: [ @@ -687,6 +702,20 @@ parent: lc_src clock: io_div4 } + { + name: i2c3 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c3_n + parent: lc_src + clock: io_div4 + } ] rst_ni: lc_io_div4 export_rsts: {} diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/doc/registers.md b/hw/top_earlgrey/ip_autogen/rstmgr/doc/registers.md index 4243b905b5a72c..f70e141d5cbc9f 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/doc/registers.md +++ b/hw/top_earlgrey/ip_autogen/rstmgr/doc/registers.md @@ -24,15 +24,17 @@ | rstmgr.[`SW_RST_REGWEN_5`](#sw_rst_regwen) | 0x40 | 4 | Register write enable for software controllable resets. | | rstmgr.[`SW_RST_REGWEN_6`](#sw_rst_regwen) | 0x44 | 4 | Register write enable for software controllable resets. | | rstmgr.[`SW_RST_REGWEN_7`](#sw_rst_regwen) | 0x48 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_0`](#sw_rst_ctrl_n) | 0x4c | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_1`](#sw_rst_ctrl_n) | 0x50 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_2`](#sw_rst_ctrl_n) | 0x54 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_3`](#sw_rst_ctrl_n) | 0x58 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_4`](#sw_rst_ctrl_n) | 0x5c | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_5`](#sw_rst_ctrl_n) | 0x60 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_6`](#sw_rst_ctrl_n) | 0x64 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_7`](#sw_rst_ctrl_n) | 0x68 | 4 | Software controllable resets. | -| rstmgr.[`ERR_CODE`](#err_code) | 0x6c | 4 | A bit vector of all the errors that have occurred in reset manager | +| rstmgr.[`SW_RST_REGWEN_8`](#sw_rst_regwen) | 0x4c | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_0`](#sw_rst_ctrl_n) | 0x50 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_1`](#sw_rst_ctrl_n) | 0x54 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_2`](#sw_rst_ctrl_n) | 0x58 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_3`](#sw_rst_ctrl_n) | 0x5c | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_4`](#sw_rst_ctrl_n) | 0x60 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_5`](#sw_rst_ctrl_n) | 0x64 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_6`](#sw_rst_ctrl_n) | 0x68 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_7`](#sw_rst_ctrl_n) | 0x6c | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_8`](#sw_rst_ctrl_n) | 0x70 | 4 | Software controllable resets. | +| rstmgr.[`ERR_CODE`](#err_code) | 0x74 | 4 | A bit vector of all the errors that have occurred in reset manager | ## ALERT_TEST Alert Test Register @@ -268,6 +270,7 @@ When a particular bit value is 1, the corresponding value in [`SW_RST_CTRL_N`](# | SW_RST_REGWEN_5 | 0x40 | | SW_RST_REGWEN_6 | 0x44 | | SW_RST_REGWEN_7 | 0x48 | +| SW_RST_REGWEN_8 | 0x4c | ### Fields @@ -292,14 +295,15 @@ When a particular bit value is 1, the corresponding module is not held in reset. | Name | Offset | |:----------------|:---------| -| SW_RST_CTRL_N_0 | 0x4c | -| SW_RST_CTRL_N_1 | 0x50 | -| SW_RST_CTRL_N_2 | 0x54 | -| SW_RST_CTRL_N_3 | 0x58 | -| SW_RST_CTRL_N_4 | 0x5c | -| SW_RST_CTRL_N_5 | 0x60 | -| SW_RST_CTRL_N_6 | 0x64 | -| SW_RST_CTRL_N_7 | 0x68 | +| SW_RST_CTRL_N_0 | 0x50 | +| SW_RST_CTRL_N_1 | 0x54 | +| SW_RST_CTRL_N_2 | 0x58 | +| SW_RST_CTRL_N_3 | 0x5c | +| SW_RST_CTRL_N_4 | 0x60 | +| SW_RST_CTRL_N_5 | 0x64 | +| SW_RST_CTRL_N_6 | 0x68 | +| SW_RST_CTRL_N_7 | 0x6c | +| SW_RST_CTRL_N_8 | 0x70 | ### Fields @@ -315,7 +319,7 @@ When a particular bit value is 1, the corresponding module is not held in reset. ## ERR_CODE A bit vector of all the errors that have occurred in reset manager -- Offset: `0x6c` +- Offset: `0x74` - Reset default: `0x0` - Reset mask: `0x7` diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el b/hw/top_earlgrey/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el index d262656329e919..7f62a02d0ba8df 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el @@ -15,6 +15,10 @@ CHECKSUM: "258095983 1288805244" INSTANCE: tb.dut ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c3_n [0] "logic resets_o.rst_i2c3_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c3_n [0] "logic resets_o.rst_i2c3_n[1:0]" +ANNOTATION: "VC_COV_UNR" Toggle 0to1 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" ANNOTATION: "VC_COV_UNR" Toggle 1to0 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv b/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv index 0a44cd8c83fba8..8da78ae40c4bf6 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv @@ -42,6 +42,7 @@ package rstmgr_env_pkg; "u_d0_i2c0", "u_d0_i2c1", "u_d0_i2c2", + "u_d0_i2c3", "u_d0_lc", "u_d0_lc_io", "u_d0_lc_io_div2", diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv b/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv index e39a53001b674e..2e59284d01839f 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv @@ -113,6 +113,7 @@ class rstmgr_scoreboard extends cip_base_scoreboard #( "5": blocked = `gmv(ral.sw_rst_regwen[5]) == 0; "6": blocked = `gmv(ral.sw_rst_regwen[6]) == 0; "7": blocked = `gmv(ral.sw_rst_regwen[7]) == 0; + "8": blocked = `gmv(ral.sw_rst_regwen[8]) == 0; default: `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", ral_name)) endcase diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv b/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv index babe8cac35e622..87932b75bbf524 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv @@ -49,6 +49,7 @@ module rstmgr_bind; .parent_rst_n(rst_sys_src_n[1]), .ctrl_ns(reg2hw.sw_rst_ctrl_n), .rst_ens({ + rst_en_o.i2c3[1] == prim_mubi_pkg::MuBi4True, rst_en_o.i2c2[1] == prim_mubi_pkg::MuBi4True, rst_en_o.i2c1[1] == prim_mubi_pkg::MuBi4True, rst_en_o.i2c0[1] == prim_mubi_pkg::MuBi4True, @@ -59,6 +60,7 @@ module rstmgr_bind; rst_en_o.spi_device[1] == prim_mubi_pkg::MuBi4True }), .rst_ns({ + resets_o.rst_i2c3_n[1], resets_o.rst_i2c2_n[1], resets_o.rst_i2c1_n[1], resets_o.rst_i2c0_n[1], diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv b/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv index a24d3b98c1c958..d14fdbe772a09f 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv @@ -383,4 +383,17 @@ interface rstmgr_rst_en_track_sva_if ( clk_io_div4_i, !rst_por_ni) + `ASSERT(D0RstI2c3EnTracksRstI2c3Active_A, + $fell(resets_i.rst_i2c3_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.i2c3[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstI2c3EnTracksRstI2c3Inactive_A, + $rose(resets_i.rst_i2c3_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_i2c3_n[Domain0Sel] || + reset_en_i.i2c3[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + endinterface diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr.sv b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr.sv index 04e665ddda86ce..1612e25ac402b0 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr.sv @@ -185,12 +185,12 @@ module rstmgr //////////////////////////////////////////////////// // consistency check errors - logic [20:0][PowerDomains-1:0] cnsty_chk_errs; - logic [20:0][PowerDomains-1:0] shadow_cnsty_chk_errs; + logic [21:0][PowerDomains-1:0] cnsty_chk_errs; + logic [21:0][PowerDomains-1:0] shadow_cnsty_chk_errs; // consistency sparse fsm errors - logic [20:0][PowerDomains-1:0] fsm_errs; - logic [20:0][PowerDomains-1:0] shadow_fsm_errs; + logic [21:0][PowerDomains-1:0] fsm_errs; + logic [21:0][PowerDomains-1:0] shadow_fsm_errs; assign hw2reg.err_code.reg_intg_err.d = 1'b1; assign hw2reg.err_code.reg_intg_err.de = reg_intg_err; @@ -1169,6 +1169,40 @@ module rstmgr assign shadow_cnsty_chk_errs[20] = '0; assign shadow_fsm_errs[20] = '0; + // Generating resets for i2c3 + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_i2c3_n[DomainAonSel] = '0; + assign cnsty_chk_errs[21][DomainAonSel] = '0; + assign fsm_errs[21][DomainAonSel] = '0; + assign rst_en_o.i2c3[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b1) + ) u_d0_i2c3 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C3].q), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.i2c3[Domain0Sel]), + .leaf_rst_o(resets_o.rst_i2c3_n[Domain0Sel]), + .err_o(cnsty_chk_errs[21][Domain0Sel]), + .fsm_err_o(fsm_errs[21][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_i2c3_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0I2c3FsmCheck_A, + u_d0_i2c3.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[21] = '0; + assign shadow_fsm_errs[21] = '0; + //////////////////////////////////////////////////// // Reset info construction // diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv index d5feb7ff9389bb..2f421d6ef19c68 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv @@ -22,6 +22,7 @@ package rstmgr_pkg; parameter int I2C0 = 5; parameter int I2C1 = 6; parameter int I2C2 = 7; + parameter int I2C3 = 8; // resets generated and broadcast // SEC_CM: LEAF.RST.SHADOW @@ -50,6 +51,7 @@ package rstmgr_pkg; logic [PowerDomains-1:0] rst_i2c0_n; logic [PowerDomains-1:0] rst_i2c1_n; logic [PowerDomains-1:0] rst_i2c2_n; + logic [PowerDomains-1:0] rst_i2c3_n; } rstmgr_out_t; // reset indication for alert handler @@ -78,9 +80,10 @@ package rstmgr_pkg; prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c0; prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c1; prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c2; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c3; } rstmgr_rst_en_t; - parameter int NumOutputRst = 24 * PowerDomains; + parameter int NumOutputRst = 25 * PowerDomains; // cpu reset requests and status typedef struct packed { diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv index b4481116d2a6e5..a2a1330d358155 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv @@ -10,7 +10,7 @@ package rstmgr_reg_pkg; parameter int RdWidth = 32; parameter int IdxWidth = 4; parameter int NumHwResets = 5; - parameter int NumSwResets = 8; + parameter int NumSwResets = 9; parameter int NumTotalResets = 8; parameter int NumAlerts = 2; @@ -146,12 +146,12 @@ package rstmgr_reg_pkg; // Register -> HW type typedef struct packed { - rstmgr_reg2hw_alert_test_reg_t alert_test; // [34:31] - rstmgr_reg2hw_reset_req_reg_t reset_req; // [30:27] - rstmgr_reg2hw_reset_info_reg_t reset_info; // [26:21] - rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [20:16] - rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [15:11] - rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [7:0] sw_rst_ctrl_n; // [10:3] + rstmgr_reg2hw_alert_test_reg_t alert_test; // [35:32] + rstmgr_reg2hw_reset_req_reg_t reset_req; // [31:28] + rstmgr_reg2hw_reset_info_reg_t reset_info; // [27:22] + rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [21:17] + rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [16:12] + rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [8:0] sw_rst_ctrl_n; // [11:3] rstmgr_reg2hw_err_code_reg_t err_code; // [2:0] } rstmgr_reg2hw_t; @@ -188,15 +188,17 @@ package rstmgr_reg_pkg; parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_5_OFFSET = 7'h 40; parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_6_OFFSET = 7'h 44; parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_7_OFFSET = 7'h 48; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_0_OFFSET = 7'h 4c; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_1_OFFSET = 7'h 50; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_2_OFFSET = 7'h 54; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_3_OFFSET = 7'h 58; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_4_OFFSET = 7'h 5c; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_5_OFFSET = 7'h 60; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_6_OFFSET = 7'h 64; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_7_OFFSET = 7'h 68; - parameter logic [BlockAw-1:0] RSTMGR_ERR_CODE_OFFSET = 7'h 6c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_8_OFFSET = 7'h 4c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_0_OFFSET = 7'h 50; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_1_OFFSET = 7'h 54; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_2_OFFSET = 7'h 58; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_3_OFFSET = 7'h 5c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_4_OFFSET = 7'h 60; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_5_OFFSET = 7'h 64; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_6_OFFSET = 7'h 68; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_7_OFFSET = 7'h 6c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_8_OFFSET = 7'h 70; + parameter logic [BlockAw-1:0] RSTMGR_ERR_CODE_OFFSET = 7'h 74; // Reset values for hwext registers and their fields parameter logic [1:0] RSTMGR_ALERT_TEST_RESVAL = 2'h 0; @@ -232,6 +234,7 @@ package rstmgr_reg_pkg; RSTMGR_SW_RST_REGWEN_5, RSTMGR_SW_RST_REGWEN_6, RSTMGR_SW_RST_REGWEN_7, + RSTMGR_SW_RST_REGWEN_8, RSTMGR_SW_RST_CTRL_N_0, RSTMGR_SW_RST_CTRL_N_1, RSTMGR_SW_RST_CTRL_N_2, @@ -240,11 +243,12 @@ package rstmgr_reg_pkg; RSTMGR_SW_RST_CTRL_N_5, RSTMGR_SW_RST_CTRL_N_6, RSTMGR_SW_RST_CTRL_N_7, + RSTMGR_SW_RST_CTRL_N_8, RSTMGR_ERR_CODE } rstmgr_id_e; // Register width information to check illegal writes - parameter logic [3:0] RSTMGR_PERMIT [28] = '{ + parameter logic [3:0] RSTMGR_PERMIT [30] = '{ 4'b 0001, // index[ 0] RSTMGR_ALERT_TEST 4'b 0001, // index[ 1] RSTMGR_RESET_REQ 4'b 0001, // index[ 2] RSTMGR_RESET_INFO @@ -264,15 +268,17 @@ package rstmgr_reg_pkg; 4'b 0001, // index[16] RSTMGR_SW_RST_REGWEN_5 4'b 0001, // index[17] RSTMGR_SW_RST_REGWEN_6 4'b 0001, // index[18] RSTMGR_SW_RST_REGWEN_7 - 4'b 0001, // index[19] RSTMGR_SW_RST_CTRL_N_0 - 4'b 0001, // index[20] RSTMGR_SW_RST_CTRL_N_1 - 4'b 0001, // index[21] RSTMGR_SW_RST_CTRL_N_2 - 4'b 0001, // index[22] RSTMGR_SW_RST_CTRL_N_3 - 4'b 0001, // index[23] RSTMGR_SW_RST_CTRL_N_4 - 4'b 0001, // index[24] RSTMGR_SW_RST_CTRL_N_5 - 4'b 0001, // index[25] RSTMGR_SW_RST_CTRL_N_6 - 4'b 0001, // index[26] RSTMGR_SW_RST_CTRL_N_7 - 4'b 0001 // index[27] RSTMGR_ERR_CODE + 4'b 0001, // index[19] RSTMGR_SW_RST_REGWEN_8 + 4'b 0001, // index[20] RSTMGR_SW_RST_CTRL_N_0 + 4'b 0001, // index[21] RSTMGR_SW_RST_CTRL_N_1 + 4'b 0001, // index[22] RSTMGR_SW_RST_CTRL_N_2 + 4'b 0001, // index[23] RSTMGR_SW_RST_CTRL_N_3 + 4'b 0001, // index[24] RSTMGR_SW_RST_CTRL_N_4 + 4'b 0001, // index[25] RSTMGR_SW_RST_CTRL_N_5 + 4'b 0001, // index[26] RSTMGR_SW_RST_CTRL_N_6 + 4'b 0001, // index[27] RSTMGR_SW_RST_CTRL_N_7 + 4'b 0001, // index[28] RSTMGR_SW_RST_CTRL_N_8 + 4'b 0001 // index[29] RSTMGR_ERR_CODE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv index a24ad7d2c6fb90..8b93d9262ab169 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv @@ -54,9 +54,9 @@ module rstmgr_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [27:0] reg_we_check; + logic [29:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(28) + .OneHotWidth(30) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -186,6 +186,9 @@ module rstmgr_reg_top ( logic sw_rst_regwen_7_we; logic sw_rst_regwen_7_qs; logic sw_rst_regwen_7_wd; + logic sw_rst_regwen_8_we; + logic sw_rst_regwen_8_qs; + logic sw_rst_regwen_8_wd; logic sw_rst_ctrl_n_0_we; logic sw_rst_ctrl_n_0_qs; logic sw_rst_ctrl_n_0_wd; @@ -210,6 +213,9 @@ module rstmgr_reg_top ( logic sw_rst_ctrl_n_7_we; logic sw_rst_ctrl_n_7_qs; logic sw_rst_ctrl_n_7_wd; + logic sw_rst_ctrl_n_8_we; + logic sw_rst_ctrl_n_8_qs; + logic sw_rst_ctrl_n_8_wd; logic err_code_reg_intg_err_qs; logic err_code_reset_consistency_err_qs; logic err_code_fsm_err_qs; @@ -870,6 +876,35 @@ module rstmgr_reg_top ( ); + // Subregister 8 of Multireg sw_rst_regwen + // R[sw_rst_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_regwen_8_we), + .wd (sw_rst_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_rst_regwen_8_qs) + ); + + // Subregister 0 of Multireg sw_rst_ctrl_n // R[sw_rst_ctrl_n_0]: V(False) // Create REGWEN-gated WE signal @@ -1126,6 +1161,38 @@ module rstmgr_reg_top ( ); + // Subregister 8 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n_8]: V(False) + // Create REGWEN-gated WE signal + logic sw_rst_ctrl_n_8_gated_we; + assign sw_rst_ctrl_n_8_gated_we = sw_rst_ctrl_n_8_we & sw_rst_regwen_8_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_ctrl_n_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_ctrl_n_8_gated_we), + .wd (sw_rst_ctrl_n_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_ctrl_n[8].q), + .ds (), + + // to register interface (read) + .qs (sw_rst_ctrl_n_8_qs) + ); + + // R[err_code]: V(False) // F[reg_intg_err]: 0:0 prim_subreg #( @@ -1210,7 +1277,7 @@ module rstmgr_reg_top ( - logic [27:0] addr_hit; + logic [29:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == RSTMGR_ALERT_TEST_OFFSET); @@ -1232,15 +1299,17 @@ module rstmgr_reg_top ( addr_hit[16] = (reg_addr == RSTMGR_SW_RST_REGWEN_5_OFFSET); addr_hit[17] = (reg_addr == RSTMGR_SW_RST_REGWEN_6_OFFSET); addr_hit[18] = (reg_addr == RSTMGR_SW_RST_REGWEN_7_OFFSET); - addr_hit[19] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET); - addr_hit[20] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET); - addr_hit[21] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET); - addr_hit[22] = (reg_addr == RSTMGR_SW_RST_CTRL_N_3_OFFSET); - addr_hit[23] = (reg_addr == RSTMGR_SW_RST_CTRL_N_4_OFFSET); - addr_hit[24] = (reg_addr == RSTMGR_SW_RST_CTRL_N_5_OFFSET); - addr_hit[25] = (reg_addr == RSTMGR_SW_RST_CTRL_N_6_OFFSET); - addr_hit[26] = (reg_addr == RSTMGR_SW_RST_CTRL_N_7_OFFSET); - addr_hit[27] = (reg_addr == RSTMGR_ERR_CODE_OFFSET); + addr_hit[19] = (reg_addr == RSTMGR_SW_RST_REGWEN_8_OFFSET); + addr_hit[20] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET); + addr_hit[21] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET); + addr_hit[22] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET); + addr_hit[23] = (reg_addr == RSTMGR_SW_RST_CTRL_N_3_OFFSET); + addr_hit[24] = (reg_addr == RSTMGR_SW_RST_CTRL_N_4_OFFSET); + addr_hit[25] = (reg_addr == RSTMGR_SW_RST_CTRL_N_5_OFFSET); + addr_hit[26] = (reg_addr == RSTMGR_SW_RST_CTRL_N_6_OFFSET); + addr_hit[27] = (reg_addr == RSTMGR_SW_RST_CTRL_N_7_OFFSET); + addr_hit[28] = (reg_addr == RSTMGR_SW_RST_CTRL_N_8_OFFSET); + addr_hit[29] = (reg_addr == RSTMGR_ERR_CODE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1275,7 +1344,9 @@ module rstmgr_reg_top ( (addr_hit[24] & (|(RSTMGR_PERMIT[24] & ~reg_be))) | (addr_hit[25] & (|(RSTMGR_PERMIT[25] & ~reg_be))) | (addr_hit[26] & (|(RSTMGR_PERMIT[26] & ~reg_be))) | - (addr_hit[27] & (|(RSTMGR_PERMIT[27] & ~reg_be))))); + (addr_hit[27] & (|(RSTMGR_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(RSTMGR_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(RSTMGR_PERMIT[29] & ~reg_be))))); end // Generate write-enables @@ -1340,30 +1411,36 @@ module rstmgr_reg_top ( assign sw_rst_regwen_7_we = addr_hit[18] & reg_we & !reg_error; assign sw_rst_regwen_7_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_0_we = addr_hit[19] & reg_we & !reg_error; + assign sw_rst_regwen_8_we = addr_hit[19] & reg_we & !reg_error; + + assign sw_rst_regwen_8_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_0_we = addr_hit[20] & reg_we & !reg_error; assign sw_rst_ctrl_n_0_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_1_we = addr_hit[20] & reg_we & !reg_error; + assign sw_rst_ctrl_n_1_we = addr_hit[21] & reg_we & !reg_error; assign sw_rst_ctrl_n_1_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_2_we = addr_hit[21] & reg_we & !reg_error; + assign sw_rst_ctrl_n_2_we = addr_hit[22] & reg_we & !reg_error; assign sw_rst_ctrl_n_2_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_3_we = addr_hit[22] & reg_we & !reg_error; + assign sw_rst_ctrl_n_3_we = addr_hit[23] & reg_we & !reg_error; assign sw_rst_ctrl_n_3_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_4_we = addr_hit[23] & reg_we & !reg_error; + assign sw_rst_ctrl_n_4_we = addr_hit[24] & reg_we & !reg_error; assign sw_rst_ctrl_n_4_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_5_we = addr_hit[24] & reg_we & !reg_error; + assign sw_rst_ctrl_n_5_we = addr_hit[25] & reg_we & !reg_error; assign sw_rst_ctrl_n_5_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_6_we = addr_hit[25] & reg_we & !reg_error; + assign sw_rst_ctrl_n_6_we = addr_hit[26] & reg_we & !reg_error; assign sw_rst_ctrl_n_6_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_7_we = addr_hit[26] & reg_we & !reg_error; + assign sw_rst_ctrl_n_7_we = addr_hit[27] & reg_we & !reg_error; assign sw_rst_ctrl_n_7_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_8_we = addr_hit[28] & reg_we & !reg_error; + + assign sw_rst_ctrl_n_8_wd = reg_wdata[0]; // Assign write-enables to checker logic vector. always_comb begin @@ -1387,15 +1464,17 @@ module rstmgr_reg_top ( reg_we_check[16] = sw_rst_regwen_5_we; reg_we_check[17] = sw_rst_regwen_6_we; reg_we_check[18] = sw_rst_regwen_7_we; - reg_we_check[19] = sw_rst_ctrl_n_0_gated_we; - reg_we_check[20] = sw_rst_ctrl_n_1_gated_we; - reg_we_check[21] = sw_rst_ctrl_n_2_gated_we; - reg_we_check[22] = sw_rst_ctrl_n_3_gated_we; - reg_we_check[23] = sw_rst_ctrl_n_4_gated_we; - reg_we_check[24] = sw_rst_ctrl_n_5_gated_we; - reg_we_check[25] = sw_rst_ctrl_n_6_gated_we; - reg_we_check[26] = sw_rst_ctrl_n_7_gated_we; - reg_we_check[27] = 1'b0; + reg_we_check[19] = sw_rst_regwen_8_we; + reg_we_check[20] = sw_rst_ctrl_n_0_gated_we; + reg_we_check[21] = sw_rst_ctrl_n_1_gated_we; + reg_we_check[22] = sw_rst_ctrl_n_2_gated_we; + reg_we_check[23] = sw_rst_ctrl_n_3_gated_we; + reg_we_check[24] = sw_rst_ctrl_n_4_gated_we; + reg_we_check[25] = sw_rst_ctrl_n_5_gated_we; + reg_we_check[26] = sw_rst_ctrl_n_6_gated_we; + reg_we_check[27] = sw_rst_ctrl_n_7_gated_we; + reg_we_check[28] = sw_rst_ctrl_n_8_gated_we; + reg_we_check[29] = 1'b0; end // Read data return @@ -1485,38 +1564,46 @@ module rstmgr_reg_top ( end addr_hit[19]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_0_qs; + reg_rdata_next[0] = sw_rst_regwen_8_qs; end addr_hit[20]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_1_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_0_qs; end addr_hit[21]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_2_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_1_qs; end addr_hit[22]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_3_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_2_qs; end addr_hit[23]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_4_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_3_qs; end addr_hit[24]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_5_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_4_qs; end addr_hit[25]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_6_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_5_qs; end addr_hit[26]: begin - reg_rdata_next[0] = sw_rst_ctrl_n_7_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_6_qs; end addr_hit[27]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_7_qs; + end + + addr_hit[28]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_8_qs; + end + + addr_hit[29]: begin reg_rdata_next[0] = err_code_reg_intg_err_qs; reg_rdata_next[1] = err_code_reset_consistency_err_qs; reg_rdata_next[2] = err_code_fsm_err_qs; diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson b/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson index 450e68d1be47a8..092d11eb0bd39b 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson @@ -37,7 +37,7 @@ { name: "NumSrc", desc: "Number of interrupt sources", type: "int", - default: "182", + default: "197", local: "true" }, { name: "NumTarget", @@ -1565,6 +1565,126 @@ { bits: "1:0" } ], } + { name: "PRIO182", + desc: "Interrupt Source 182 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO183", + desc: "Interrupt Source 183 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO184", + desc: "Interrupt Source 184 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO185", + desc: "Interrupt Source 185 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO186", + desc: "Interrupt Source 186 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO187", + desc: "Interrupt Source 187 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO188", + desc: "Interrupt Source 188 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO189", + desc: "Interrupt Source 189 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO190", + desc: "Interrupt Source 190 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO191", + desc: "Interrupt Source 191 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO192", + desc: "Interrupt Source 192 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO193", + desc: "Interrupt Source 193 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO194", + desc: "Interrupt Source 194 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO195", + desc: "Interrupt Source 195 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO196", + desc: "Interrupt Source 196 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } { skipto: "0x00001000" } { multireg: { name: "IP", diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson index 489eae178cf980..122ff5eb59fbc5 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson @@ -5,7 +5,7 @@ instance_name: top_earlgrey_rv_plic param_values: { - src: 182 + src: 197 target: 1 prio: 3 topname: earlgrey diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv index 6f6112613e609d..c0bc48d25889b0 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -278,11 +278,26 @@ module rv_plic import rv_plic_reg_pkg::*; #( assign prio[179] = reg2hw.prio179.q; assign prio[180] = reg2hw.prio180.q; assign prio[181] = reg2hw.prio181.q; + assign prio[182] = reg2hw.prio182.q; + assign prio[183] = reg2hw.prio183.q; + assign prio[184] = reg2hw.prio184.q; + assign prio[185] = reg2hw.prio185.q; + assign prio[186] = reg2hw.prio186.q; + assign prio[187] = reg2hw.prio187.q; + assign prio[188] = reg2hw.prio188.q; + assign prio[189] = reg2hw.prio189.q; + assign prio[190] = reg2hw.prio190.q; + assign prio[191] = reg2hw.prio191.q; + assign prio[192] = reg2hw.prio192.q; + assign prio[193] = reg2hw.prio193.q; + assign prio[194] = reg2hw.prio194.q; + assign prio[195] = reg2hw.prio195.q; + assign prio[196] = reg2hw.prio196.q; ////////////////////// // Interrupt Enable // ////////////////////// - for (genvar s = 0; s < 182; s++) begin : gen_ie0 + for (genvar s = 0; s < 197; s++) begin : gen_ie0 assign ie[0][s] = reg2hw.ie0[s].q; end @@ -308,7 +323,7 @@ module rv_plic import rv_plic_reg_pkg::*; #( //////// // IP // //////// - for (genvar s = 0; s < 182; s++) begin : gen_ip + for (genvar s = 0; s < 197; s++) begin : gen_ip assign hw2reg.ip[s].de = 1'b1; // Always write assign hw2reg.ip[s].d = ip[s]; end diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv index 69f2e22c661c07..4982b29c7cfebe 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv @@ -7,7 +7,7 @@ package rv_plic_reg_pkg; // Param list - parameter int NumSrc = 182; + parameter int NumSrc = 197; parameter int NumTarget = 1; parameter int PrioWidth = 2; parameter int NumAlerts = 1; @@ -747,6 +747,66 @@ package rv_plic_reg_pkg; logic [1:0] q; } rv_plic_reg2hw_prio181_reg_t; + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio182_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio183_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio184_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio185_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio186_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio187_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio188_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio189_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio190_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio191_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio192_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio193_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio194_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio195_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio196_reg_t; + typedef struct packed { logic q; } rv_plic_reg2hw_ie0_mreg_t; @@ -781,189 +841,204 @@ package rv_plic_reg_pkg; // Register -> HW type typedef struct packed { - rv_plic_reg2hw_prio0_reg_t prio0; // [560:559] - rv_plic_reg2hw_prio1_reg_t prio1; // [558:557] - rv_plic_reg2hw_prio2_reg_t prio2; // [556:555] - rv_plic_reg2hw_prio3_reg_t prio3; // [554:553] - rv_plic_reg2hw_prio4_reg_t prio4; // [552:551] - rv_plic_reg2hw_prio5_reg_t prio5; // [550:549] - rv_plic_reg2hw_prio6_reg_t prio6; // [548:547] - rv_plic_reg2hw_prio7_reg_t prio7; // [546:545] - rv_plic_reg2hw_prio8_reg_t prio8; // [544:543] - rv_plic_reg2hw_prio9_reg_t prio9; // [542:541] - rv_plic_reg2hw_prio10_reg_t prio10; // [540:539] - rv_plic_reg2hw_prio11_reg_t prio11; // [538:537] - rv_plic_reg2hw_prio12_reg_t prio12; // [536:535] - rv_plic_reg2hw_prio13_reg_t prio13; // [534:533] - rv_plic_reg2hw_prio14_reg_t prio14; // [532:531] - rv_plic_reg2hw_prio15_reg_t prio15; // [530:529] - rv_plic_reg2hw_prio16_reg_t prio16; // [528:527] - rv_plic_reg2hw_prio17_reg_t prio17; // [526:525] - rv_plic_reg2hw_prio18_reg_t prio18; // [524:523] - rv_plic_reg2hw_prio19_reg_t prio19; // [522:521] - rv_plic_reg2hw_prio20_reg_t prio20; // [520:519] - rv_plic_reg2hw_prio21_reg_t prio21; // [518:517] - rv_plic_reg2hw_prio22_reg_t prio22; // [516:515] - rv_plic_reg2hw_prio23_reg_t prio23; // [514:513] - rv_plic_reg2hw_prio24_reg_t prio24; // [512:511] - rv_plic_reg2hw_prio25_reg_t prio25; // [510:509] - rv_plic_reg2hw_prio26_reg_t prio26; // [508:507] - rv_plic_reg2hw_prio27_reg_t prio27; // [506:505] - rv_plic_reg2hw_prio28_reg_t prio28; // [504:503] - rv_plic_reg2hw_prio29_reg_t prio29; // [502:501] - rv_plic_reg2hw_prio30_reg_t prio30; // [500:499] - rv_plic_reg2hw_prio31_reg_t prio31; // [498:497] - rv_plic_reg2hw_prio32_reg_t prio32; // [496:495] - rv_plic_reg2hw_prio33_reg_t prio33; // [494:493] - rv_plic_reg2hw_prio34_reg_t prio34; // [492:491] - rv_plic_reg2hw_prio35_reg_t prio35; // [490:489] - rv_plic_reg2hw_prio36_reg_t prio36; // [488:487] - rv_plic_reg2hw_prio37_reg_t prio37; // [486:485] - rv_plic_reg2hw_prio38_reg_t prio38; // [484:483] - rv_plic_reg2hw_prio39_reg_t prio39; // [482:481] - rv_plic_reg2hw_prio40_reg_t prio40; // [480:479] - rv_plic_reg2hw_prio41_reg_t prio41; // [478:477] - rv_plic_reg2hw_prio42_reg_t prio42; // [476:475] - rv_plic_reg2hw_prio43_reg_t prio43; // [474:473] - rv_plic_reg2hw_prio44_reg_t prio44; // [472:471] - rv_plic_reg2hw_prio45_reg_t prio45; // [470:469] - rv_plic_reg2hw_prio46_reg_t prio46; // [468:467] - rv_plic_reg2hw_prio47_reg_t prio47; // [466:465] - rv_plic_reg2hw_prio48_reg_t prio48; // [464:463] - rv_plic_reg2hw_prio49_reg_t prio49; // [462:461] - rv_plic_reg2hw_prio50_reg_t prio50; // [460:459] - rv_plic_reg2hw_prio51_reg_t prio51; // [458:457] - rv_plic_reg2hw_prio52_reg_t prio52; // [456:455] - rv_plic_reg2hw_prio53_reg_t prio53; // [454:453] - rv_plic_reg2hw_prio54_reg_t prio54; // [452:451] - rv_plic_reg2hw_prio55_reg_t prio55; // [450:449] - rv_plic_reg2hw_prio56_reg_t prio56; // [448:447] - rv_plic_reg2hw_prio57_reg_t prio57; // [446:445] - rv_plic_reg2hw_prio58_reg_t prio58; // [444:443] - rv_plic_reg2hw_prio59_reg_t prio59; // [442:441] - rv_plic_reg2hw_prio60_reg_t prio60; // [440:439] - rv_plic_reg2hw_prio61_reg_t prio61; // [438:437] - rv_plic_reg2hw_prio62_reg_t prio62; // [436:435] - rv_plic_reg2hw_prio63_reg_t prio63; // [434:433] - rv_plic_reg2hw_prio64_reg_t prio64; // [432:431] - rv_plic_reg2hw_prio65_reg_t prio65; // [430:429] - rv_plic_reg2hw_prio66_reg_t prio66; // [428:427] - rv_plic_reg2hw_prio67_reg_t prio67; // [426:425] - rv_plic_reg2hw_prio68_reg_t prio68; // [424:423] - rv_plic_reg2hw_prio69_reg_t prio69; // [422:421] - rv_plic_reg2hw_prio70_reg_t prio70; // [420:419] - rv_plic_reg2hw_prio71_reg_t prio71; // [418:417] - rv_plic_reg2hw_prio72_reg_t prio72; // [416:415] - rv_plic_reg2hw_prio73_reg_t prio73; // [414:413] - rv_plic_reg2hw_prio74_reg_t prio74; // [412:411] - rv_plic_reg2hw_prio75_reg_t prio75; // [410:409] - rv_plic_reg2hw_prio76_reg_t prio76; // [408:407] - rv_plic_reg2hw_prio77_reg_t prio77; // [406:405] - rv_plic_reg2hw_prio78_reg_t prio78; // [404:403] - rv_plic_reg2hw_prio79_reg_t prio79; // [402:401] - rv_plic_reg2hw_prio80_reg_t prio80; // [400:399] - rv_plic_reg2hw_prio81_reg_t prio81; // [398:397] - rv_plic_reg2hw_prio82_reg_t prio82; // [396:395] - rv_plic_reg2hw_prio83_reg_t prio83; // [394:393] - rv_plic_reg2hw_prio84_reg_t prio84; // [392:391] - rv_plic_reg2hw_prio85_reg_t prio85; // [390:389] - rv_plic_reg2hw_prio86_reg_t prio86; // [388:387] - rv_plic_reg2hw_prio87_reg_t prio87; // [386:385] - rv_plic_reg2hw_prio88_reg_t prio88; // [384:383] - rv_plic_reg2hw_prio89_reg_t prio89; // [382:381] - rv_plic_reg2hw_prio90_reg_t prio90; // [380:379] - rv_plic_reg2hw_prio91_reg_t prio91; // [378:377] - rv_plic_reg2hw_prio92_reg_t prio92; // [376:375] - rv_plic_reg2hw_prio93_reg_t prio93; // [374:373] - rv_plic_reg2hw_prio94_reg_t prio94; // [372:371] - rv_plic_reg2hw_prio95_reg_t prio95; // [370:369] - rv_plic_reg2hw_prio96_reg_t prio96; // [368:367] - rv_plic_reg2hw_prio97_reg_t prio97; // [366:365] - rv_plic_reg2hw_prio98_reg_t prio98; // [364:363] - rv_plic_reg2hw_prio99_reg_t prio99; // [362:361] - rv_plic_reg2hw_prio100_reg_t prio100; // [360:359] - rv_plic_reg2hw_prio101_reg_t prio101; // [358:357] - rv_plic_reg2hw_prio102_reg_t prio102; // [356:355] - rv_plic_reg2hw_prio103_reg_t prio103; // [354:353] - rv_plic_reg2hw_prio104_reg_t prio104; // [352:351] - rv_plic_reg2hw_prio105_reg_t prio105; // [350:349] - rv_plic_reg2hw_prio106_reg_t prio106; // [348:347] - rv_plic_reg2hw_prio107_reg_t prio107; // [346:345] - rv_plic_reg2hw_prio108_reg_t prio108; // [344:343] - rv_plic_reg2hw_prio109_reg_t prio109; // [342:341] - rv_plic_reg2hw_prio110_reg_t prio110; // [340:339] - rv_plic_reg2hw_prio111_reg_t prio111; // [338:337] - rv_plic_reg2hw_prio112_reg_t prio112; // [336:335] - rv_plic_reg2hw_prio113_reg_t prio113; // [334:333] - rv_plic_reg2hw_prio114_reg_t prio114; // [332:331] - rv_plic_reg2hw_prio115_reg_t prio115; // [330:329] - rv_plic_reg2hw_prio116_reg_t prio116; // [328:327] - rv_plic_reg2hw_prio117_reg_t prio117; // [326:325] - rv_plic_reg2hw_prio118_reg_t prio118; // [324:323] - rv_plic_reg2hw_prio119_reg_t prio119; // [322:321] - rv_plic_reg2hw_prio120_reg_t prio120; // [320:319] - rv_plic_reg2hw_prio121_reg_t prio121; // [318:317] - rv_plic_reg2hw_prio122_reg_t prio122; // [316:315] - rv_plic_reg2hw_prio123_reg_t prio123; // [314:313] - rv_plic_reg2hw_prio124_reg_t prio124; // [312:311] - rv_plic_reg2hw_prio125_reg_t prio125; // [310:309] - rv_plic_reg2hw_prio126_reg_t prio126; // [308:307] - rv_plic_reg2hw_prio127_reg_t prio127; // [306:305] - rv_plic_reg2hw_prio128_reg_t prio128; // [304:303] - rv_plic_reg2hw_prio129_reg_t prio129; // [302:301] - rv_plic_reg2hw_prio130_reg_t prio130; // [300:299] - rv_plic_reg2hw_prio131_reg_t prio131; // [298:297] - rv_plic_reg2hw_prio132_reg_t prio132; // [296:295] - rv_plic_reg2hw_prio133_reg_t prio133; // [294:293] - rv_plic_reg2hw_prio134_reg_t prio134; // [292:291] - rv_plic_reg2hw_prio135_reg_t prio135; // [290:289] - rv_plic_reg2hw_prio136_reg_t prio136; // [288:287] - rv_plic_reg2hw_prio137_reg_t prio137; // [286:285] - rv_plic_reg2hw_prio138_reg_t prio138; // [284:283] - rv_plic_reg2hw_prio139_reg_t prio139; // [282:281] - rv_plic_reg2hw_prio140_reg_t prio140; // [280:279] - rv_plic_reg2hw_prio141_reg_t prio141; // [278:277] - rv_plic_reg2hw_prio142_reg_t prio142; // [276:275] - rv_plic_reg2hw_prio143_reg_t prio143; // [274:273] - rv_plic_reg2hw_prio144_reg_t prio144; // [272:271] - rv_plic_reg2hw_prio145_reg_t prio145; // [270:269] - rv_plic_reg2hw_prio146_reg_t prio146; // [268:267] - rv_plic_reg2hw_prio147_reg_t prio147; // [266:265] - rv_plic_reg2hw_prio148_reg_t prio148; // [264:263] - rv_plic_reg2hw_prio149_reg_t prio149; // [262:261] - rv_plic_reg2hw_prio150_reg_t prio150; // [260:259] - rv_plic_reg2hw_prio151_reg_t prio151; // [258:257] - rv_plic_reg2hw_prio152_reg_t prio152; // [256:255] - rv_plic_reg2hw_prio153_reg_t prio153; // [254:253] - rv_plic_reg2hw_prio154_reg_t prio154; // [252:251] - rv_plic_reg2hw_prio155_reg_t prio155; // [250:249] - rv_plic_reg2hw_prio156_reg_t prio156; // [248:247] - rv_plic_reg2hw_prio157_reg_t prio157; // [246:245] - rv_plic_reg2hw_prio158_reg_t prio158; // [244:243] - rv_plic_reg2hw_prio159_reg_t prio159; // [242:241] - rv_plic_reg2hw_prio160_reg_t prio160; // [240:239] - rv_plic_reg2hw_prio161_reg_t prio161; // [238:237] - rv_plic_reg2hw_prio162_reg_t prio162; // [236:235] - rv_plic_reg2hw_prio163_reg_t prio163; // [234:233] - rv_plic_reg2hw_prio164_reg_t prio164; // [232:231] - rv_plic_reg2hw_prio165_reg_t prio165; // [230:229] - rv_plic_reg2hw_prio166_reg_t prio166; // [228:227] - rv_plic_reg2hw_prio167_reg_t prio167; // [226:225] - rv_plic_reg2hw_prio168_reg_t prio168; // [224:223] - rv_plic_reg2hw_prio169_reg_t prio169; // [222:221] - rv_plic_reg2hw_prio170_reg_t prio170; // [220:219] - rv_plic_reg2hw_prio171_reg_t prio171; // [218:217] - rv_plic_reg2hw_prio172_reg_t prio172; // [216:215] - rv_plic_reg2hw_prio173_reg_t prio173; // [214:213] - rv_plic_reg2hw_prio174_reg_t prio174; // [212:211] - rv_plic_reg2hw_prio175_reg_t prio175; // [210:209] - rv_plic_reg2hw_prio176_reg_t prio176; // [208:207] - rv_plic_reg2hw_prio177_reg_t prio177; // [206:205] - rv_plic_reg2hw_prio178_reg_t prio178; // [204:203] - rv_plic_reg2hw_prio179_reg_t prio179; // [202:201] - rv_plic_reg2hw_prio180_reg_t prio180; // [200:199] - rv_plic_reg2hw_prio181_reg_t prio181; // [198:197] - rv_plic_reg2hw_ie0_mreg_t [181:0] ie0; // [196:15] + rv_plic_reg2hw_prio0_reg_t prio0; // [605:604] + rv_plic_reg2hw_prio1_reg_t prio1; // [603:602] + rv_plic_reg2hw_prio2_reg_t prio2; // [601:600] + rv_plic_reg2hw_prio3_reg_t prio3; // [599:598] + rv_plic_reg2hw_prio4_reg_t prio4; // [597:596] + rv_plic_reg2hw_prio5_reg_t prio5; // [595:594] + rv_plic_reg2hw_prio6_reg_t prio6; // [593:592] + rv_plic_reg2hw_prio7_reg_t prio7; // [591:590] + rv_plic_reg2hw_prio8_reg_t prio8; // [589:588] + rv_plic_reg2hw_prio9_reg_t prio9; // [587:586] + rv_plic_reg2hw_prio10_reg_t prio10; // [585:584] + rv_plic_reg2hw_prio11_reg_t prio11; // [583:582] + rv_plic_reg2hw_prio12_reg_t prio12; // [581:580] + rv_plic_reg2hw_prio13_reg_t prio13; // [579:578] + rv_plic_reg2hw_prio14_reg_t prio14; // [577:576] + rv_plic_reg2hw_prio15_reg_t prio15; // [575:574] + rv_plic_reg2hw_prio16_reg_t prio16; // [573:572] + rv_plic_reg2hw_prio17_reg_t prio17; // [571:570] + rv_plic_reg2hw_prio18_reg_t prio18; // [569:568] + rv_plic_reg2hw_prio19_reg_t prio19; // [567:566] + rv_plic_reg2hw_prio20_reg_t prio20; // [565:564] + rv_plic_reg2hw_prio21_reg_t prio21; // [563:562] + rv_plic_reg2hw_prio22_reg_t prio22; // [561:560] + rv_plic_reg2hw_prio23_reg_t prio23; // [559:558] + rv_plic_reg2hw_prio24_reg_t prio24; // [557:556] + rv_plic_reg2hw_prio25_reg_t prio25; // [555:554] + rv_plic_reg2hw_prio26_reg_t prio26; // [553:552] + rv_plic_reg2hw_prio27_reg_t prio27; // [551:550] + rv_plic_reg2hw_prio28_reg_t prio28; // [549:548] + rv_plic_reg2hw_prio29_reg_t prio29; // [547:546] + rv_plic_reg2hw_prio30_reg_t prio30; // [545:544] + rv_plic_reg2hw_prio31_reg_t prio31; // [543:542] + rv_plic_reg2hw_prio32_reg_t prio32; // [541:540] + rv_plic_reg2hw_prio33_reg_t prio33; // [539:538] + rv_plic_reg2hw_prio34_reg_t prio34; // [537:536] + rv_plic_reg2hw_prio35_reg_t prio35; // [535:534] + rv_plic_reg2hw_prio36_reg_t prio36; // [533:532] + rv_plic_reg2hw_prio37_reg_t prio37; // [531:530] + rv_plic_reg2hw_prio38_reg_t prio38; // [529:528] + rv_plic_reg2hw_prio39_reg_t prio39; // [527:526] + rv_plic_reg2hw_prio40_reg_t prio40; // [525:524] + rv_plic_reg2hw_prio41_reg_t prio41; // [523:522] + rv_plic_reg2hw_prio42_reg_t prio42; // [521:520] + rv_plic_reg2hw_prio43_reg_t prio43; // [519:518] + rv_plic_reg2hw_prio44_reg_t prio44; // [517:516] + rv_plic_reg2hw_prio45_reg_t prio45; // [515:514] + rv_plic_reg2hw_prio46_reg_t prio46; // [513:512] + rv_plic_reg2hw_prio47_reg_t prio47; // [511:510] + rv_plic_reg2hw_prio48_reg_t prio48; // [509:508] + rv_plic_reg2hw_prio49_reg_t prio49; // [507:506] + rv_plic_reg2hw_prio50_reg_t prio50; // [505:504] + rv_plic_reg2hw_prio51_reg_t prio51; // [503:502] + rv_plic_reg2hw_prio52_reg_t prio52; // [501:500] + rv_plic_reg2hw_prio53_reg_t prio53; // [499:498] + rv_plic_reg2hw_prio54_reg_t prio54; // [497:496] + rv_plic_reg2hw_prio55_reg_t prio55; // [495:494] + rv_plic_reg2hw_prio56_reg_t prio56; // [493:492] + rv_plic_reg2hw_prio57_reg_t prio57; // [491:490] + rv_plic_reg2hw_prio58_reg_t prio58; // [489:488] + rv_plic_reg2hw_prio59_reg_t prio59; // [487:486] + rv_plic_reg2hw_prio60_reg_t prio60; // [485:484] + rv_plic_reg2hw_prio61_reg_t prio61; // [483:482] + rv_plic_reg2hw_prio62_reg_t prio62; // [481:480] + rv_plic_reg2hw_prio63_reg_t prio63; // [479:478] + rv_plic_reg2hw_prio64_reg_t prio64; // [477:476] + rv_plic_reg2hw_prio65_reg_t prio65; // [475:474] + rv_plic_reg2hw_prio66_reg_t prio66; // [473:472] + rv_plic_reg2hw_prio67_reg_t prio67; // [471:470] + rv_plic_reg2hw_prio68_reg_t prio68; // [469:468] + rv_plic_reg2hw_prio69_reg_t prio69; // [467:466] + rv_plic_reg2hw_prio70_reg_t prio70; // [465:464] + rv_plic_reg2hw_prio71_reg_t prio71; // [463:462] + rv_plic_reg2hw_prio72_reg_t prio72; // [461:460] + rv_plic_reg2hw_prio73_reg_t prio73; // [459:458] + rv_plic_reg2hw_prio74_reg_t prio74; // [457:456] + rv_plic_reg2hw_prio75_reg_t prio75; // [455:454] + rv_plic_reg2hw_prio76_reg_t prio76; // [453:452] + rv_plic_reg2hw_prio77_reg_t prio77; // [451:450] + rv_plic_reg2hw_prio78_reg_t prio78; // [449:448] + rv_plic_reg2hw_prio79_reg_t prio79; // [447:446] + rv_plic_reg2hw_prio80_reg_t prio80; // [445:444] + rv_plic_reg2hw_prio81_reg_t prio81; // [443:442] + rv_plic_reg2hw_prio82_reg_t prio82; // [441:440] + rv_plic_reg2hw_prio83_reg_t prio83; // [439:438] + rv_plic_reg2hw_prio84_reg_t prio84; // [437:436] + rv_plic_reg2hw_prio85_reg_t prio85; // [435:434] + rv_plic_reg2hw_prio86_reg_t prio86; // [433:432] + rv_plic_reg2hw_prio87_reg_t prio87; // [431:430] + rv_plic_reg2hw_prio88_reg_t prio88; // [429:428] + rv_plic_reg2hw_prio89_reg_t prio89; // [427:426] + rv_plic_reg2hw_prio90_reg_t prio90; // [425:424] + rv_plic_reg2hw_prio91_reg_t prio91; // [423:422] + rv_plic_reg2hw_prio92_reg_t prio92; // [421:420] + rv_plic_reg2hw_prio93_reg_t prio93; // [419:418] + rv_plic_reg2hw_prio94_reg_t prio94; // [417:416] + rv_plic_reg2hw_prio95_reg_t prio95; // [415:414] + rv_plic_reg2hw_prio96_reg_t prio96; // [413:412] + rv_plic_reg2hw_prio97_reg_t prio97; // [411:410] + rv_plic_reg2hw_prio98_reg_t prio98; // [409:408] + rv_plic_reg2hw_prio99_reg_t prio99; // [407:406] + rv_plic_reg2hw_prio100_reg_t prio100; // [405:404] + rv_plic_reg2hw_prio101_reg_t prio101; // [403:402] + rv_plic_reg2hw_prio102_reg_t prio102; // [401:400] + rv_plic_reg2hw_prio103_reg_t prio103; // [399:398] + rv_plic_reg2hw_prio104_reg_t prio104; // [397:396] + rv_plic_reg2hw_prio105_reg_t prio105; // [395:394] + rv_plic_reg2hw_prio106_reg_t prio106; // [393:392] + rv_plic_reg2hw_prio107_reg_t prio107; // [391:390] + rv_plic_reg2hw_prio108_reg_t prio108; // [389:388] + rv_plic_reg2hw_prio109_reg_t prio109; // [387:386] + rv_plic_reg2hw_prio110_reg_t prio110; // [385:384] + rv_plic_reg2hw_prio111_reg_t prio111; // [383:382] + rv_plic_reg2hw_prio112_reg_t prio112; // [381:380] + rv_plic_reg2hw_prio113_reg_t prio113; // [379:378] + rv_plic_reg2hw_prio114_reg_t prio114; // [377:376] + rv_plic_reg2hw_prio115_reg_t prio115; // [375:374] + rv_plic_reg2hw_prio116_reg_t prio116; // [373:372] + rv_plic_reg2hw_prio117_reg_t prio117; // [371:370] + rv_plic_reg2hw_prio118_reg_t prio118; // [369:368] + rv_plic_reg2hw_prio119_reg_t prio119; // [367:366] + rv_plic_reg2hw_prio120_reg_t prio120; // [365:364] + rv_plic_reg2hw_prio121_reg_t prio121; // [363:362] + rv_plic_reg2hw_prio122_reg_t prio122; // [361:360] + rv_plic_reg2hw_prio123_reg_t prio123; // [359:358] + rv_plic_reg2hw_prio124_reg_t prio124; // [357:356] + rv_plic_reg2hw_prio125_reg_t prio125; // [355:354] + rv_plic_reg2hw_prio126_reg_t prio126; // [353:352] + rv_plic_reg2hw_prio127_reg_t prio127; // [351:350] + rv_plic_reg2hw_prio128_reg_t prio128; // [349:348] + rv_plic_reg2hw_prio129_reg_t prio129; // [347:346] + rv_plic_reg2hw_prio130_reg_t prio130; // [345:344] + rv_plic_reg2hw_prio131_reg_t prio131; // [343:342] + rv_plic_reg2hw_prio132_reg_t prio132; // [341:340] + rv_plic_reg2hw_prio133_reg_t prio133; // [339:338] + rv_plic_reg2hw_prio134_reg_t prio134; // [337:336] + rv_plic_reg2hw_prio135_reg_t prio135; // [335:334] + rv_plic_reg2hw_prio136_reg_t prio136; // [333:332] + rv_plic_reg2hw_prio137_reg_t prio137; // [331:330] + rv_plic_reg2hw_prio138_reg_t prio138; // [329:328] + rv_plic_reg2hw_prio139_reg_t prio139; // [327:326] + rv_plic_reg2hw_prio140_reg_t prio140; // [325:324] + rv_plic_reg2hw_prio141_reg_t prio141; // [323:322] + rv_plic_reg2hw_prio142_reg_t prio142; // [321:320] + rv_plic_reg2hw_prio143_reg_t prio143; // [319:318] + rv_plic_reg2hw_prio144_reg_t prio144; // [317:316] + rv_plic_reg2hw_prio145_reg_t prio145; // [315:314] + rv_plic_reg2hw_prio146_reg_t prio146; // [313:312] + rv_plic_reg2hw_prio147_reg_t prio147; // [311:310] + rv_plic_reg2hw_prio148_reg_t prio148; // [309:308] + rv_plic_reg2hw_prio149_reg_t prio149; // [307:306] + rv_plic_reg2hw_prio150_reg_t prio150; // [305:304] + rv_plic_reg2hw_prio151_reg_t prio151; // [303:302] + rv_plic_reg2hw_prio152_reg_t prio152; // [301:300] + rv_plic_reg2hw_prio153_reg_t prio153; // [299:298] + rv_plic_reg2hw_prio154_reg_t prio154; // [297:296] + rv_plic_reg2hw_prio155_reg_t prio155; // [295:294] + rv_plic_reg2hw_prio156_reg_t prio156; // [293:292] + rv_plic_reg2hw_prio157_reg_t prio157; // [291:290] + rv_plic_reg2hw_prio158_reg_t prio158; // [289:288] + rv_plic_reg2hw_prio159_reg_t prio159; // [287:286] + rv_plic_reg2hw_prio160_reg_t prio160; // [285:284] + rv_plic_reg2hw_prio161_reg_t prio161; // [283:282] + rv_plic_reg2hw_prio162_reg_t prio162; // [281:280] + rv_plic_reg2hw_prio163_reg_t prio163; // [279:278] + rv_plic_reg2hw_prio164_reg_t prio164; // [277:276] + rv_plic_reg2hw_prio165_reg_t prio165; // [275:274] + rv_plic_reg2hw_prio166_reg_t prio166; // [273:272] + rv_plic_reg2hw_prio167_reg_t prio167; // [271:270] + rv_plic_reg2hw_prio168_reg_t prio168; // [269:268] + rv_plic_reg2hw_prio169_reg_t prio169; // [267:266] + rv_plic_reg2hw_prio170_reg_t prio170; // [265:264] + rv_plic_reg2hw_prio171_reg_t prio171; // [263:262] + rv_plic_reg2hw_prio172_reg_t prio172; // [261:260] + rv_plic_reg2hw_prio173_reg_t prio173; // [259:258] + rv_plic_reg2hw_prio174_reg_t prio174; // [257:256] + rv_plic_reg2hw_prio175_reg_t prio175; // [255:254] + rv_plic_reg2hw_prio176_reg_t prio176; // [253:252] + rv_plic_reg2hw_prio177_reg_t prio177; // [251:250] + rv_plic_reg2hw_prio178_reg_t prio178; // [249:248] + rv_plic_reg2hw_prio179_reg_t prio179; // [247:246] + rv_plic_reg2hw_prio180_reg_t prio180; // [245:244] + rv_plic_reg2hw_prio181_reg_t prio181; // [243:242] + rv_plic_reg2hw_prio182_reg_t prio182; // [241:240] + rv_plic_reg2hw_prio183_reg_t prio183; // [239:238] + rv_plic_reg2hw_prio184_reg_t prio184; // [237:236] + rv_plic_reg2hw_prio185_reg_t prio185; // [235:234] + rv_plic_reg2hw_prio186_reg_t prio186; // [233:232] + rv_plic_reg2hw_prio187_reg_t prio187; // [231:230] + rv_plic_reg2hw_prio188_reg_t prio188; // [229:228] + rv_plic_reg2hw_prio189_reg_t prio189; // [227:226] + rv_plic_reg2hw_prio190_reg_t prio190; // [225:224] + rv_plic_reg2hw_prio191_reg_t prio191; // [223:222] + rv_plic_reg2hw_prio192_reg_t prio192; // [221:220] + rv_plic_reg2hw_prio193_reg_t prio193; // [219:218] + rv_plic_reg2hw_prio194_reg_t prio194; // [217:216] + rv_plic_reg2hw_prio195_reg_t prio195; // [215:214] + rv_plic_reg2hw_prio196_reg_t prio196; // [213:212] + rv_plic_reg2hw_ie0_mreg_t [196:0] ie0; // [211:15] rv_plic_reg2hw_threshold0_reg_t threshold0; // [14:13] rv_plic_reg2hw_cc0_reg_t cc0; // [12:3] rv_plic_reg2hw_msip0_reg_t msip0; // [2:2] @@ -972,7 +1047,7 @@ package rv_plic_reg_pkg; // HW -> register type typedef struct packed { - rv_plic_hw2reg_ip_mreg_t [181:0] ip; // [371:8] + rv_plic_hw2reg_ip_mreg_t [196:0] ip; // [401:8] rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] } rv_plic_hw2reg_t; @@ -1159,18 +1234,35 @@ package rv_plic_reg_pkg; parameter logic [BlockAw-1:0] RV_PLIC_PRIO179_OFFSET = 27'h 2cc; parameter logic [BlockAw-1:0] RV_PLIC_PRIO180_OFFSET = 27'h 2d0; parameter logic [BlockAw-1:0] RV_PLIC_PRIO181_OFFSET = 27'h 2d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO182_OFFSET = 27'h 2d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO183_OFFSET = 27'h 2dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO184_OFFSET = 27'h 2e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO185_OFFSET = 27'h 2e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO186_OFFSET = 27'h 2e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO187_OFFSET = 27'h 2ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO188_OFFSET = 27'h 2f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO189_OFFSET = 27'h 2f4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO190_OFFSET = 27'h 2f8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO191_OFFSET = 27'h 2fc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO192_OFFSET = 27'h 300; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO193_OFFSET = 27'h 304; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO194_OFFSET = 27'h 308; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO195_OFFSET = 27'h 30c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO196_OFFSET = 27'h 310; parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 27'h 1000; parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 27'h 1004; parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 27'h 1008; parameter logic [BlockAw-1:0] RV_PLIC_IP_3_OFFSET = 27'h 100c; parameter logic [BlockAw-1:0] RV_PLIC_IP_4_OFFSET = 27'h 1010; parameter logic [BlockAw-1:0] RV_PLIC_IP_5_OFFSET = 27'h 1014; + parameter logic [BlockAw-1:0] RV_PLIC_IP_6_OFFSET = 27'h 1018; parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 27'h 2000; parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 27'h 2004; parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 27'h 2008; parameter logic [BlockAw-1:0] RV_PLIC_IE0_3_OFFSET = 27'h 200c; parameter logic [BlockAw-1:0] RV_PLIC_IE0_4_OFFSET = 27'h 2010; parameter logic [BlockAw-1:0] RV_PLIC_IE0_5_OFFSET = 27'h 2014; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_6_OFFSET = 27'h 2018; parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 27'h 200000; parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 27'h 200004; parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 27'h 4000000; @@ -1364,18 +1456,35 @@ package rv_plic_reg_pkg; RV_PLIC_PRIO179, RV_PLIC_PRIO180, RV_PLIC_PRIO181, + RV_PLIC_PRIO182, + RV_PLIC_PRIO183, + RV_PLIC_PRIO184, + RV_PLIC_PRIO185, + RV_PLIC_PRIO186, + RV_PLIC_PRIO187, + RV_PLIC_PRIO188, + RV_PLIC_PRIO189, + RV_PLIC_PRIO190, + RV_PLIC_PRIO191, + RV_PLIC_PRIO192, + RV_PLIC_PRIO193, + RV_PLIC_PRIO194, + RV_PLIC_PRIO195, + RV_PLIC_PRIO196, RV_PLIC_IP_0, RV_PLIC_IP_1, RV_PLIC_IP_2, RV_PLIC_IP_3, RV_PLIC_IP_4, RV_PLIC_IP_5, + RV_PLIC_IP_6, RV_PLIC_IE0_0, RV_PLIC_IE0_1, RV_PLIC_IE0_2, RV_PLIC_IE0_3, RV_PLIC_IE0_4, RV_PLIC_IE0_5, + RV_PLIC_IE0_6, RV_PLIC_THRESHOLD0, RV_PLIC_CC0, RV_PLIC_MSIP0, @@ -1383,7 +1492,7 @@ package rv_plic_reg_pkg; } rv_plic_id_e; // Register width information to check illegal writes - parameter logic [3:0] RV_PLIC_PERMIT [198] = '{ + parameter logic [3:0] RV_PLIC_PERMIT [215] = '{ 4'b 0001, // index[ 0] RV_PLIC_PRIO0 4'b 0001, // index[ 1] RV_PLIC_PRIO1 4'b 0001, // index[ 2] RV_PLIC_PRIO2 @@ -1566,22 +1675,39 @@ package rv_plic_reg_pkg; 4'b 0001, // index[179] RV_PLIC_PRIO179 4'b 0001, // index[180] RV_PLIC_PRIO180 4'b 0001, // index[181] RV_PLIC_PRIO181 - 4'b 1111, // index[182] RV_PLIC_IP_0 - 4'b 1111, // index[183] RV_PLIC_IP_1 - 4'b 1111, // index[184] RV_PLIC_IP_2 - 4'b 1111, // index[185] RV_PLIC_IP_3 - 4'b 1111, // index[186] RV_PLIC_IP_4 - 4'b 0111, // index[187] RV_PLIC_IP_5 - 4'b 1111, // index[188] RV_PLIC_IE0_0 - 4'b 1111, // index[189] RV_PLIC_IE0_1 - 4'b 1111, // index[190] RV_PLIC_IE0_2 - 4'b 1111, // index[191] RV_PLIC_IE0_3 - 4'b 1111, // index[192] RV_PLIC_IE0_4 - 4'b 0111, // index[193] RV_PLIC_IE0_5 - 4'b 0001, // index[194] RV_PLIC_THRESHOLD0 - 4'b 0001, // index[195] RV_PLIC_CC0 - 4'b 0001, // index[196] RV_PLIC_MSIP0 - 4'b 0001 // index[197] RV_PLIC_ALERT_TEST + 4'b 0001, // index[182] RV_PLIC_PRIO182 + 4'b 0001, // index[183] RV_PLIC_PRIO183 + 4'b 0001, // index[184] RV_PLIC_PRIO184 + 4'b 0001, // index[185] RV_PLIC_PRIO185 + 4'b 0001, // index[186] RV_PLIC_PRIO186 + 4'b 0001, // index[187] RV_PLIC_PRIO187 + 4'b 0001, // index[188] RV_PLIC_PRIO188 + 4'b 0001, // index[189] RV_PLIC_PRIO189 + 4'b 0001, // index[190] RV_PLIC_PRIO190 + 4'b 0001, // index[191] RV_PLIC_PRIO191 + 4'b 0001, // index[192] RV_PLIC_PRIO192 + 4'b 0001, // index[193] RV_PLIC_PRIO193 + 4'b 0001, // index[194] RV_PLIC_PRIO194 + 4'b 0001, // index[195] RV_PLIC_PRIO195 + 4'b 0001, // index[196] RV_PLIC_PRIO196 + 4'b 1111, // index[197] RV_PLIC_IP_0 + 4'b 1111, // index[198] RV_PLIC_IP_1 + 4'b 1111, // index[199] RV_PLIC_IP_2 + 4'b 1111, // index[200] RV_PLIC_IP_3 + 4'b 1111, // index[201] RV_PLIC_IP_4 + 4'b 1111, // index[202] RV_PLIC_IP_5 + 4'b 0001, // index[203] RV_PLIC_IP_6 + 4'b 1111, // index[204] RV_PLIC_IE0_0 + 4'b 1111, // index[205] RV_PLIC_IE0_1 + 4'b 1111, // index[206] RV_PLIC_IE0_2 + 4'b 1111, // index[207] RV_PLIC_IE0_3 + 4'b 1111, // index[208] RV_PLIC_IE0_4 + 4'b 1111, // index[209] RV_PLIC_IE0_5 + 4'b 0001, // index[210] RV_PLIC_IE0_6 + 4'b 0001, // index[211] RV_PLIC_THRESHOLD0 + 4'b 0001, // index[212] RV_PLIC_CC0 + 4'b 0001, // index[213] RV_PLIC_MSIP0 + 4'b 0001 // index[214] RV_PLIC_ALERT_TEST }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv index e1584f8640c6a7..27eb541a9e6a51 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv @@ -52,9 +52,9 @@ module rv_plic_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [197:0] reg_we_check; + logic [214:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(198) + .OneHotWidth(215) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -667,6 +667,51 @@ module rv_plic_reg_top ( logic prio181_we; logic [1:0] prio181_qs; logic [1:0] prio181_wd; + logic prio182_we; + logic [1:0] prio182_qs; + logic [1:0] prio182_wd; + logic prio183_we; + logic [1:0] prio183_qs; + logic [1:0] prio183_wd; + logic prio184_we; + logic [1:0] prio184_qs; + logic [1:0] prio184_wd; + logic prio185_we; + logic [1:0] prio185_qs; + logic [1:0] prio185_wd; + logic prio186_we; + logic [1:0] prio186_qs; + logic [1:0] prio186_wd; + logic prio187_we; + logic [1:0] prio187_qs; + logic [1:0] prio187_wd; + logic prio188_we; + logic [1:0] prio188_qs; + logic [1:0] prio188_wd; + logic prio189_we; + logic [1:0] prio189_qs; + logic [1:0] prio189_wd; + logic prio190_we; + logic [1:0] prio190_qs; + logic [1:0] prio190_wd; + logic prio191_we; + logic [1:0] prio191_qs; + logic [1:0] prio191_wd; + logic prio192_we; + logic [1:0] prio192_qs; + logic [1:0] prio192_wd; + logic prio193_we; + logic [1:0] prio193_qs; + logic [1:0] prio193_wd; + logic prio194_we; + logic [1:0] prio194_qs; + logic [1:0] prio194_wd; + logic prio195_we; + logic [1:0] prio195_qs; + logic [1:0] prio195_wd; + logic prio196_we; + logic [1:0] prio196_qs; + logic [1:0] prio196_wd; logic ip_0_p_0_qs; logic ip_0_p_1_qs; logic ip_0_p_2_qs; @@ -849,6 +894,21 @@ module rv_plic_reg_top ( logic ip_5_p_179_qs; logic ip_5_p_180_qs; logic ip_5_p_181_qs; + logic ip_5_p_182_qs; + logic ip_5_p_183_qs; + logic ip_5_p_184_qs; + logic ip_5_p_185_qs; + logic ip_5_p_186_qs; + logic ip_5_p_187_qs; + logic ip_5_p_188_qs; + logic ip_5_p_189_qs; + logic ip_5_p_190_qs; + logic ip_5_p_191_qs; + logic ip_6_p_192_qs; + logic ip_6_p_193_qs; + logic ip_6_p_194_qs; + logic ip_6_p_195_qs; + logic ip_6_p_196_qs; logic ie0_0_we; logic ie0_0_e_0_qs; logic ie0_0_e_0_wd; @@ -1219,6 +1279,37 @@ module rv_plic_reg_top ( logic ie0_5_e_180_wd; logic ie0_5_e_181_qs; logic ie0_5_e_181_wd; + logic ie0_5_e_182_qs; + logic ie0_5_e_182_wd; + logic ie0_5_e_183_qs; + logic ie0_5_e_183_wd; + logic ie0_5_e_184_qs; + logic ie0_5_e_184_wd; + logic ie0_5_e_185_qs; + logic ie0_5_e_185_wd; + logic ie0_5_e_186_qs; + logic ie0_5_e_186_wd; + logic ie0_5_e_187_qs; + logic ie0_5_e_187_wd; + logic ie0_5_e_188_qs; + logic ie0_5_e_188_wd; + logic ie0_5_e_189_qs; + logic ie0_5_e_189_wd; + logic ie0_5_e_190_qs; + logic ie0_5_e_190_wd; + logic ie0_5_e_191_qs; + logic ie0_5_e_191_wd; + logic ie0_6_we; + logic ie0_6_e_192_qs; + logic ie0_6_e_192_wd; + logic ie0_6_e_193_qs; + logic ie0_6_e_193_wd; + logic ie0_6_e_194_qs; + logic ie0_6_e_194_wd; + logic ie0_6_e_195_qs; + logic ie0_6_e_195_wd; + logic ie0_6_e_196_qs; + logic ie0_6_e_196_wd; logic threshold0_we; logic [1:0] threshold0_qs; logic [1:0] threshold0_wd; @@ -6329,6 +6420,426 @@ module rv_plic_reg_top ( ); + // R[prio182]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio182 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio182_we), + .wd (prio182_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio182.q), + .ds (), + + // to register interface (read) + .qs (prio182_qs) + ); + + + // R[prio183]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio183 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio183_we), + .wd (prio183_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio183.q), + .ds (), + + // to register interface (read) + .qs (prio183_qs) + ); + + + // R[prio184]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio184 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio184_we), + .wd (prio184_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio184.q), + .ds (), + + // to register interface (read) + .qs (prio184_qs) + ); + + + // R[prio185]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio185 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio185_we), + .wd (prio185_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio185.q), + .ds (), + + // to register interface (read) + .qs (prio185_qs) + ); + + + // R[prio186]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio186 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio186_we), + .wd (prio186_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio186.q), + .ds (), + + // to register interface (read) + .qs (prio186_qs) + ); + + + // R[prio187]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio187 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio187_we), + .wd (prio187_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio187.q), + .ds (), + + // to register interface (read) + .qs (prio187_qs) + ); + + + // R[prio188]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio188 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio188_we), + .wd (prio188_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio188.q), + .ds (), + + // to register interface (read) + .qs (prio188_qs) + ); + + + // R[prio189]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio189 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio189_we), + .wd (prio189_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio189.q), + .ds (), + + // to register interface (read) + .qs (prio189_qs) + ); + + + // R[prio190]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio190 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio190_we), + .wd (prio190_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio190.q), + .ds (), + + // to register interface (read) + .qs (prio190_qs) + ); + + + // R[prio191]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio191 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio191_we), + .wd (prio191_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio191.q), + .ds (), + + // to register interface (read) + .qs (prio191_qs) + ); + + + // R[prio192]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio192 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio192_we), + .wd (prio192_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio192.q), + .ds (), + + // to register interface (read) + .qs (prio192_qs) + ); + + + // R[prio193]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio193 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio193_we), + .wd (prio193_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio193.q), + .ds (), + + // to register interface (read) + .qs (prio193_qs) + ); + + + // R[prio194]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio194 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio194_we), + .wd (prio194_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio194.q), + .ds (), + + // to register interface (read) + .qs (prio194_qs) + ); + + + // R[prio195]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio195 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio195_we), + .wd (prio195_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio195.q), + .ds (), + + // to register interface (read) + .qs (prio195_qs) + ); + + + // R[prio196]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio196 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio196_we), + .wd (prio196_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio196.q), + .ds (), + + // to register interface (read) + .qs (prio196_qs) + ); + + // Subregister 0 of Multireg ip // R[ip_0]: V(False) // F[p_0]: 0:0 @@ -6337,7 +6848,655 @@ module rv_plic_reg_top ( .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_0 ( + ) u_ip_0_p_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[0].de), + .d (hw2reg.ip[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_0_qs) + ); + + // F[p_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[1].de), + .d (hw2reg.ip[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_1_qs) + ); + + // F[p_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[2].de), + .d (hw2reg.ip[2].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_2_qs) + ); + + // F[p_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[3].de), + .d (hw2reg.ip[3].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_3_qs) + ); + + // F[p_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[4].de), + .d (hw2reg.ip[4].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_4_qs) + ); + + // F[p_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[5].de), + .d (hw2reg.ip[5].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_5_qs) + ); + + // F[p_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[6].de), + .d (hw2reg.ip[6].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_6_qs) + ); + + // F[p_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[7].de), + .d (hw2reg.ip[7].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_7_qs) + ); + + // F[p_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[8].de), + .d (hw2reg.ip[8].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_8_qs) + ); + + // F[p_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[9].de), + .d (hw2reg.ip[9].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_9_qs) + ); + + // F[p_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[10].de), + .d (hw2reg.ip[10].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_10_qs) + ); + + // F[p_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[11].de), + .d (hw2reg.ip[11].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_11_qs) + ); + + // F[p_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[12].de), + .d (hw2reg.ip[12].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_12_qs) + ); + + // F[p_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[13].de), + .d (hw2reg.ip[13].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_13_qs) + ); + + // F[p_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[14].de), + .d (hw2reg.ip[14].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_14_qs) + ); + + // F[p_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[15].de), + .d (hw2reg.ip[15].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_15_qs) + ); + + // F[p_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[16].de), + .d (hw2reg.ip[16].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_16_qs) + ); + + // F[p_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[17].de), + .d (hw2reg.ip[17].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_17_qs) + ); + + // F[p_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[18].de), + .d (hw2reg.ip[18].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_18_qs) + ); + + // F[p_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[19].de), + .d (hw2reg.ip[19].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_19_qs) + ); + + // F[p_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[20].de), + .d (hw2reg.ip[20].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_20_qs) + ); + + // F[p_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[21].de), + .d (hw2reg.ip[21].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_21_qs) + ); + + // F[p_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[22].de), + .d (hw2reg.ip[22].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_22_qs) + ); + + // F[p_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[23].de), + .d (hw2reg.ip[23].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_23_qs) + ); + + // F[p_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_24 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6346,8 +7505,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[0].de), - .d (hw2reg.ip[0].d), + .de (hw2reg.ip[24].de), + .d (hw2reg.ip[24].d), // to internal hardware .qe (), @@ -6355,16 +7514,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_0_qs) + .qs (ip_0_p_24_qs) ); - // F[p_1]: 1:1 + // F[p_25]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_1 ( + ) u_ip_0_p_25 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6373,8 +7532,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[1].de), - .d (hw2reg.ip[1].d), + .de (hw2reg.ip[25].de), + .d (hw2reg.ip[25].d), // to internal hardware .qe (), @@ -6382,16 +7541,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_1_qs) + .qs (ip_0_p_25_qs) ); - // F[p_2]: 2:2 + // F[p_26]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_2 ( + ) u_ip_0_p_26 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6400,8 +7559,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[2].de), - .d (hw2reg.ip[2].d), + .de (hw2reg.ip[26].de), + .d (hw2reg.ip[26].d), // to internal hardware .qe (), @@ -6409,16 +7568,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_2_qs) + .qs (ip_0_p_26_qs) ); - // F[p_3]: 3:3 + // F[p_27]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_3 ( + ) u_ip_0_p_27 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6427,8 +7586,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[3].de), - .d (hw2reg.ip[3].d), + .de (hw2reg.ip[27].de), + .d (hw2reg.ip[27].d), // to internal hardware .qe (), @@ -6436,16 +7595,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_3_qs) + .qs (ip_0_p_27_qs) ); - // F[p_4]: 4:4 + // F[p_28]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_4 ( + ) u_ip_0_p_28 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6454,8 +7613,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[4].de), - .d (hw2reg.ip[4].d), + .de (hw2reg.ip[28].de), + .d (hw2reg.ip[28].d), // to internal hardware .qe (), @@ -6463,16 +7622,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_4_qs) + .qs (ip_0_p_28_qs) ); - // F[p_5]: 5:5 + // F[p_29]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_5 ( + ) u_ip_0_p_29 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6481,8 +7640,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[5].de), - .d (hw2reg.ip[5].d), + .de (hw2reg.ip[29].de), + .d (hw2reg.ip[29].d), // to internal hardware .qe (), @@ -6490,16 +7649,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_5_qs) + .qs (ip_0_p_29_qs) ); - // F[p_6]: 6:6 + // F[p_30]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_6 ( + ) u_ip_0_p_30 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6508,8 +7667,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[6].de), - .d (hw2reg.ip[6].d), + .de (hw2reg.ip[30].de), + .d (hw2reg.ip[30].d), // to internal hardware .qe (), @@ -6517,16 +7676,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_6_qs) + .qs (ip_0_p_30_qs) ); - // F[p_7]: 7:7 + // F[p_31]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_7 ( + ) u_ip_0_p_31 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6535,8 +7694,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[7].de), - .d (hw2reg.ip[7].d), + .de (hw2reg.ip[31].de), + .d (hw2reg.ip[31].d), // to internal hardware .qe (), @@ -6544,16 +7703,181 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_7_qs) + .qs (ip_0_p_31_qs) ); - // F[p_8]: 8:8 + + // Subregister 1 of Multireg ip + // R[ip_1]: V(False) + // F[p_32]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_8 ( + ) u_ip_1_p_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[32].de), + .d (hw2reg.ip[32].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_32_qs) + ); + + // F[p_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[33].de), + .d (hw2reg.ip[33].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_33_qs) + ); + + // F[p_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[34].de), + .d (hw2reg.ip[34].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_34_qs) + ); + + // F[p_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[35].de), + .d (hw2reg.ip[35].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_35_qs) + ); + + // F[p_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[36].de), + .d (hw2reg.ip[36].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_36_qs) + ); + + // F[p_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[37].de), + .d (hw2reg.ip[37].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_37_qs) + ); + + // F[p_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_38 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6562,8 +7886,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[8].de), - .d (hw2reg.ip[8].d), + .de (hw2reg.ip[38].de), + .d (hw2reg.ip[38].d), // to internal hardware .qe (), @@ -6571,16 +7895,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_8_qs) + .qs (ip_1_p_38_qs) ); - // F[p_9]: 9:9 + // F[p_39]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_9 ( + ) u_ip_1_p_39 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6589,8 +7913,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[9].de), - .d (hw2reg.ip[9].d), + .de (hw2reg.ip[39].de), + .d (hw2reg.ip[39].d), // to internal hardware .qe (), @@ -6598,16 +7922,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_9_qs) + .qs (ip_1_p_39_qs) ); - // F[p_10]: 10:10 + // F[p_40]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_10 ( + ) u_ip_1_p_40 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6616,8 +7940,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[10].de), - .d (hw2reg.ip[10].d), + .de (hw2reg.ip[40].de), + .d (hw2reg.ip[40].d), // to internal hardware .qe (), @@ -6625,16 +7949,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_10_qs) + .qs (ip_1_p_40_qs) ); - // F[p_11]: 11:11 + // F[p_41]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_11 ( + ) u_ip_1_p_41 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6643,8 +7967,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[11].de), - .d (hw2reg.ip[11].d), + .de (hw2reg.ip[41].de), + .d (hw2reg.ip[41].d), // to internal hardware .qe (), @@ -6652,16 +7976,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_11_qs) + .qs (ip_1_p_41_qs) ); - // F[p_12]: 12:12 + // F[p_42]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_12 ( + ) u_ip_1_p_42 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6670,8 +7994,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[12].de), - .d (hw2reg.ip[12].d), + .de (hw2reg.ip[42].de), + .d (hw2reg.ip[42].d), // to internal hardware .qe (), @@ -6679,16 +8003,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_12_qs) + .qs (ip_1_p_42_qs) ); - // F[p_13]: 13:13 + // F[p_43]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_13 ( + ) u_ip_1_p_43 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6697,8 +8021,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[13].de), - .d (hw2reg.ip[13].d), + .de (hw2reg.ip[43].de), + .d (hw2reg.ip[43].d), // to internal hardware .qe (), @@ -6706,16 +8030,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_13_qs) + .qs (ip_1_p_43_qs) ); - // F[p_14]: 14:14 + // F[p_44]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_14 ( + ) u_ip_1_p_44 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6724,8 +8048,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[14].de), - .d (hw2reg.ip[14].d), + .de (hw2reg.ip[44].de), + .d (hw2reg.ip[44].d), // to internal hardware .qe (), @@ -6733,16 +8057,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_14_qs) + .qs (ip_1_p_44_qs) ); - // F[p_15]: 15:15 + // F[p_45]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_15 ( + ) u_ip_1_p_45 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6751,8 +8075,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[15].de), - .d (hw2reg.ip[15].d), + .de (hw2reg.ip[45].de), + .d (hw2reg.ip[45].d), // to internal hardware .qe (), @@ -6760,16 +8084,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_15_qs) + .qs (ip_1_p_45_qs) ); - // F[p_16]: 16:16 + // F[p_46]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_16 ( + ) u_ip_1_p_46 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6778,8 +8102,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[16].de), - .d (hw2reg.ip[16].d), + .de (hw2reg.ip[46].de), + .d (hw2reg.ip[46].d), // to internal hardware .qe (), @@ -6787,16 +8111,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_16_qs) + .qs (ip_1_p_46_qs) ); - // F[p_17]: 17:17 + // F[p_47]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_17 ( + ) u_ip_1_p_47 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6805,8 +8129,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[17].de), - .d (hw2reg.ip[17].d), + .de (hw2reg.ip[47].de), + .d (hw2reg.ip[47].d), // to internal hardware .qe (), @@ -6814,16 +8138,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_17_qs) + .qs (ip_1_p_47_qs) ); - // F[p_18]: 18:18 + // F[p_48]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_18 ( + ) u_ip_1_p_48 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6832,8 +8156,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[18].de), - .d (hw2reg.ip[18].d), + .de (hw2reg.ip[48].de), + .d (hw2reg.ip[48].d), // to internal hardware .qe (), @@ -6841,16 +8165,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_18_qs) + .qs (ip_1_p_48_qs) ); - // F[p_19]: 19:19 + // F[p_49]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_19 ( + ) u_ip_1_p_49 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6859,8 +8183,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[19].de), - .d (hw2reg.ip[19].d), + .de (hw2reg.ip[49].de), + .d (hw2reg.ip[49].d), // to internal hardware .qe (), @@ -6868,16 +8192,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_19_qs) + .qs (ip_1_p_49_qs) ); - // F[p_20]: 20:20 + // F[p_50]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_20 ( + ) u_ip_1_p_50 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6886,8 +8210,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[20].de), - .d (hw2reg.ip[20].d), + .de (hw2reg.ip[50].de), + .d (hw2reg.ip[50].d), // to internal hardware .qe (), @@ -6895,16 +8219,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_20_qs) + .qs (ip_1_p_50_qs) ); - // F[p_21]: 21:21 + // F[p_51]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_21 ( + ) u_ip_1_p_51 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6913,8 +8237,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[21].de), - .d (hw2reg.ip[21].d), + .de (hw2reg.ip[51].de), + .d (hw2reg.ip[51].d), // to internal hardware .qe (), @@ -6922,16 +8246,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_21_qs) + .qs (ip_1_p_51_qs) ); - // F[p_22]: 22:22 + // F[p_52]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_22 ( + ) u_ip_1_p_52 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6940,8 +8264,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[22].de), - .d (hw2reg.ip[22].d), + .de (hw2reg.ip[52].de), + .d (hw2reg.ip[52].d), // to internal hardware .qe (), @@ -6949,16 +8273,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_22_qs) + .qs (ip_1_p_52_qs) ); - // F[p_23]: 23:23 + // F[p_53]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_23 ( + ) u_ip_1_p_53 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6967,8 +8291,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[23].de), - .d (hw2reg.ip[23].d), + .de (hw2reg.ip[53].de), + .d (hw2reg.ip[53].d), // to internal hardware .qe (), @@ -6976,16 +8300,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_23_qs) + .qs (ip_1_p_53_qs) ); - // F[p_24]: 24:24 + // F[p_54]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_24 ( + ) u_ip_1_p_54 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -6994,8 +8318,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[24].de), - .d (hw2reg.ip[24].d), + .de (hw2reg.ip[54].de), + .d (hw2reg.ip[54].d), // to internal hardware .qe (), @@ -7003,16 +8327,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_24_qs) + .qs (ip_1_p_54_qs) ); - // F[p_25]: 25:25 + // F[p_55]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_25 ( + ) u_ip_1_p_55 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7021,8 +8345,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[25].de), - .d (hw2reg.ip[25].d), + .de (hw2reg.ip[55].de), + .d (hw2reg.ip[55].d), // to internal hardware .qe (), @@ -7030,16 +8354,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_25_qs) + .qs (ip_1_p_55_qs) ); - // F[p_26]: 26:26 + // F[p_56]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_26 ( + ) u_ip_1_p_56 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7048,8 +8372,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[26].de), - .d (hw2reg.ip[26].d), + .de (hw2reg.ip[56].de), + .d (hw2reg.ip[56].d), // to internal hardware .qe (), @@ -7057,16 +8381,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_26_qs) + .qs (ip_1_p_56_qs) ); - // F[p_27]: 27:27 + // F[p_57]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_27 ( + ) u_ip_1_p_57 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7075,8 +8399,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[27].de), - .d (hw2reg.ip[27].d), + .de (hw2reg.ip[57].de), + .d (hw2reg.ip[57].d), // to internal hardware .qe (), @@ -7084,16 +8408,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_27_qs) + .qs (ip_1_p_57_qs) ); - // F[p_28]: 28:28 + // F[p_58]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_28 ( + ) u_ip_1_p_58 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7102,8 +8426,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[28].de), - .d (hw2reg.ip[28].d), + .de (hw2reg.ip[58].de), + .d (hw2reg.ip[58].d), // to internal hardware .qe (), @@ -7111,16 +8435,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_28_qs) + .qs (ip_1_p_58_qs) ); - // F[p_29]: 29:29 + // F[p_59]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_29 ( + ) u_ip_1_p_59 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7129,8 +8453,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[29].de), - .d (hw2reg.ip[29].d), + .de (hw2reg.ip[59].de), + .d (hw2reg.ip[59].d), // to internal hardware .qe (), @@ -7138,16 +8462,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_29_qs) + .qs (ip_1_p_59_qs) ); - // F[p_30]: 30:30 + // F[p_60]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_30 ( + ) u_ip_1_p_60 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7156,8 +8480,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[30].de), - .d (hw2reg.ip[30].d), + .de (hw2reg.ip[60].de), + .d (hw2reg.ip[60].d), // to internal hardware .qe (), @@ -7165,16 +8489,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_30_qs) + .qs (ip_1_p_60_qs) ); - // F[p_31]: 31:31 + // F[p_61]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_0_p_31 ( + ) u_ip_1_p_61 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7183,8 +8507,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[31].de), - .d (hw2reg.ip[31].d), + .de (hw2reg.ip[61].de), + .d (hw2reg.ip[61].d), // to internal hardware .qe (), @@ -7192,19 +8516,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_0_p_31_qs) + .qs (ip_1_p_61_qs) ); - - // Subregister 1 of Multireg ip - // R[ip_1]: V(False) - // F[p_32]: 0:0 + // F[p_62]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_32 ( + ) u_ip_1_p_62 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7213,8 +8534,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[32].de), - .d (hw2reg.ip[32].d), + .de (hw2reg.ip[62].de), + .d (hw2reg.ip[62].d), // to internal hardware .qe (), @@ -7222,16 +8543,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_32_qs) + .qs (ip_1_p_62_qs) ); - // F[p_33]: 1:1 + // F[p_63]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_33 ( + ) u_ip_1_p_63 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7240,8 +8561,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[33].de), - .d (hw2reg.ip[33].d), + .de (hw2reg.ip[63].de), + .d (hw2reg.ip[63].d), // to internal hardware .qe (), @@ -7249,16 +8570,19 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_33_qs) + .qs (ip_1_p_63_qs) ); - // F[p_34]: 2:2 + + // Subregister 2 of Multireg ip + // R[ip_2]: V(False) + // F[p_64]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_34 ( + ) u_ip_2_p_64 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7267,8 +8591,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[34].de), - .d (hw2reg.ip[34].d), + .de (hw2reg.ip[64].de), + .d (hw2reg.ip[64].d), // to internal hardware .qe (), @@ -7276,16 +8600,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_34_qs) + .qs (ip_2_p_64_qs) ); - // F[p_35]: 3:3 + // F[p_65]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_35 ( + ) u_ip_2_p_65 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7294,8 +8618,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[35].de), - .d (hw2reg.ip[35].d), + .de (hw2reg.ip[65].de), + .d (hw2reg.ip[65].d), // to internal hardware .qe (), @@ -7303,16 +8627,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_35_qs) + .qs (ip_2_p_65_qs) ); - // F[p_36]: 4:4 + // F[p_66]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_36 ( + ) u_ip_2_p_66 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7321,8 +8645,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[36].de), - .d (hw2reg.ip[36].d), + .de (hw2reg.ip[66].de), + .d (hw2reg.ip[66].d), // to internal hardware .qe (), @@ -7330,16 +8654,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_36_qs) + .qs (ip_2_p_66_qs) ); - // F[p_37]: 5:5 + // F[p_67]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_37 ( + ) u_ip_2_p_67 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7348,8 +8672,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[37].de), - .d (hw2reg.ip[37].d), + .de (hw2reg.ip[67].de), + .d (hw2reg.ip[67].d), // to internal hardware .qe (), @@ -7357,16 +8681,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_37_qs) + .qs (ip_2_p_67_qs) ); - // F[p_38]: 6:6 + // F[p_68]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_38 ( + ) u_ip_2_p_68 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7375,8 +8699,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[38].de), - .d (hw2reg.ip[38].d), + .de (hw2reg.ip[68].de), + .d (hw2reg.ip[68].d), // to internal hardware .qe (), @@ -7384,16 +8708,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_38_qs) + .qs (ip_2_p_68_qs) ); - // F[p_39]: 7:7 + // F[p_69]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_39 ( + ) u_ip_2_p_69 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7402,8 +8726,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[39].de), - .d (hw2reg.ip[39].d), + .de (hw2reg.ip[69].de), + .d (hw2reg.ip[69].d), // to internal hardware .qe (), @@ -7411,16 +8735,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_39_qs) + .qs (ip_2_p_69_qs) ); - // F[p_40]: 8:8 + // F[p_70]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_40 ( + ) u_ip_2_p_70 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7429,8 +8753,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[40].de), - .d (hw2reg.ip[40].d), + .de (hw2reg.ip[70].de), + .d (hw2reg.ip[70].d), // to internal hardware .qe (), @@ -7438,16 +8762,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_40_qs) + .qs (ip_2_p_70_qs) ); - // F[p_41]: 9:9 + // F[p_71]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_41 ( + ) u_ip_2_p_71 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7456,8 +8780,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[41].de), - .d (hw2reg.ip[41].d), + .de (hw2reg.ip[71].de), + .d (hw2reg.ip[71].d), // to internal hardware .qe (), @@ -7465,16 +8789,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_41_qs) + .qs (ip_2_p_71_qs) ); - // F[p_42]: 10:10 + // F[p_72]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_42 ( + ) u_ip_2_p_72 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7483,8 +8807,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[42].de), - .d (hw2reg.ip[42].d), + .de (hw2reg.ip[72].de), + .d (hw2reg.ip[72].d), // to internal hardware .qe (), @@ -7492,16 +8816,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_42_qs) + .qs (ip_2_p_72_qs) ); - // F[p_43]: 11:11 + // F[p_73]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_43 ( + ) u_ip_2_p_73 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7510,8 +8834,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[43].de), - .d (hw2reg.ip[43].d), + .de (hw2reg.ip[73].de), + .d (hw2reg.ip[73].d), // to internal hardware .qe (), @@ -7519,16 +8843,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_43_qs) + .qs (ip_2_p_73_qs) ); - // F[p_44]: 12:12 + // F[p_74]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_44 ( + ) u_ip_2_p_74 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7537,8 +8861,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[44].de), - .d (hw2reg.ip[44].d), + .de (hw2reg.ip[74].de), + .d (hw2reg.ip[74].d), // to internal hardware .qe (), @@ -7546,16 +8870,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_44_qs) + .qs (ip_2_p_74_qs) ); - // F[p_45]: 13:13 + // F[p_75]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_45 ( + ) u_ip_2_p_75 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7564,8 +8888,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[45].de), - .d (hw2reg.ip[45].d), + .de (hw2reg.ip[75].de), + .d (hw2reg.ip[75].d), // to internal hardware .qe (), @@ -7573,16 +8897,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_45_qs) + .qs (ip_2_p_75_qs) ); - // F[p_46]: 14:14 + // F[p_76]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_46 ( + ) u_ip_2_p_76 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7591,8 +8915,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[46].de), - .d (hw2reg.ip[46].d), + .de (hw2reg.ip[76].de), + .d (hw2reg.ip[76].d), // to internal hardware .qe (), @@ -7600,16 +8924,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_46_qs) + .qs (ip_2_p_76_qs) ); - // F[p_47]: 15:15 + // F[p_77]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_47 ( + ) u_ip_2_p_77 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7618,8 +8942,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[47].de), - .d (hw2reg.ip[47].d), + .de (hw2reg.ip[77].de), + .d (hw2reg.ip[77].d), // to internal hardware .qe (), @@ -7627,16 +8951,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_47_qs) + .qs (ip_2_p_77_qs) ); - // F[p_48]: 16:16 + // F[p_78]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_48 ( + ) u_ip_2_p_78 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7645,8 +8969,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[48].de), - .d (hw2reg.ip[48].d), + .de (hw2reg.ip[78].de), + .d (hw2reg.ip[78].d), // to internal hardware .qe (), @@ -7654,16 +8978,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_48_qs) + .qs (ip_2_p_78_qs) ); - // F[p_49]: 17:17 + // F[p_79]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_49 ( + ) u_ip_2_p_79 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7672,8 +8996,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[49].de), - .d (hw2reg.ip[49].d), + .de (hw2reg.ip[79].de), + .d (hw2reg.ip[79].d), // to internal hardware .qe (), @@ -7681,16 +9005,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_49_qs) + .qs (ip_2_p_79_qs) ); - // F[p_50]: 18:18 + // F[p_80]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_50 ( + ) u_ip_2_p_80 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7699,8 +9023,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[50].de), - .d (hw2reg.ip[50].d), + .de (hw2reg.ip[80].de), + .d (hw2reg.ip[80].d), // to internal hardware .qe (), @@ -7708,16 +9032,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_50_qs) + .qs (ip_2_p_80_qs) ); - // F[p_51]: 19:19 + // F[p_81]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_51 ( + ) u_ip_2_p_81 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7726,8 +9050,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[51].de), - .d (hw2reg.ip[51].d), + .de (hw2reg.ip[81].de), + .d (hw2reg.ip[81].d), // to internal hardware .qe (), @@ -7735,16 +9059,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_51_qs) + .qs (ip_2_p_81_qs) ); - // F[p_52]: 20:20 + // F[p_82]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_52 ( + ) u_ip_2_p_82 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7753,8 +9077,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[52].de), - .d (hw2reg.ip[52].d), + .de (hw2reg.ip[82].de), + .d (hw2reg.ip[82].d), // to internal hardware .qe (), @@ -7762,16 +9086,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_52_qs) + .qs (ip_2_p_82_qs) ); - // F[p_53]: 21:21 + // F[p_83]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_53 ( + ) u_ip_2_p_83 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7780,8 +9104,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[53].de), - .d (hw2reg.ip[53].d), + .de (hw2reg.ip[83].de), + .d (hw2reg.ip[83].d), // to internal hardware .qe (), @@ -7789,16 +9113,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_53_qs) + .qs (ip_2_p_83_qs) ); - // F[p_54]: 22:22 + // F[p_84]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_54 ( + ) u_ip_2_p_84 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7807,8 +9131,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[54].de), - .d (hw2reg.ip[54].d), + .de (hw2reg.ip[84].de), + .d (hw2reg.ip[84].d), // to internal hardware .qe (), @@ -7816,16 +9140,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_54_qs) + .qs (ip_2_p_84_qs) ); - // F[p_55]: 23:23 + // F[p_85]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_55 ( + ) u_ip_2_p_85 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7834,8 +9158,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[55].de), - .d (hw2reg.ip[55].d), + .de (hw2reg.ip[85].de), + .d (hw2reg.ip[85].d), // to internal hardware .qe (), @@ -7843,16 +9167,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_55_qs) + .qs (ip_2_p_85_qs) ); - // F[p_56]: 24:24 + // F[p_86]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_56 ( + ) u_ip_2_p_86 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7861,8 +9185,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[56].de), - .d (hw2reg.ip[56].d), + .de (hw2reg.ip[86].de), + .d (hw2reg.ip[86].d), // to internal hardware .qe (), @@ -7870,16 +9194,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_56_qs) + .qs (ip_2_p_86_qs) ); - // F[p_57]: 25:25 + // F[p_87]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_57 ( + ) u_ip_2_p_87 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7888,8 +9212,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[57].de), - .d (hw2reg.ip[57].d), + .de (hw2reg.ip[87].de), + .d (hw2reg.ip[87].d), // to internal hardware .qe (), @@ -7897,16 +9221,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_57_qs) + .qs (ip_2_p_87_qs) ); - // F[p_58]: 26:26 + // F[p_88]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_58 ( + ) u_ip_2_p_88 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7915,8 +9239,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[58].de), - .d (hw2reg.ip[58].d), + .de (hw2reg.ip[88].de), + .d (hw2reg.ip[88].d), // to internal hardware .qe (), @@ -7924,16 +9248,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_58_qs) + .qs (ip_2_p_88_qs) ); - // F[p_59]: 27:27 + // F[p_89]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_59 ( + ) u_ip_2_p_89 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7942,8 +9266,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[59].de), - .d (hw2reg.ip[59].d), + .de (hw2reg.ip[89].de), + .d (hw2reg.ip[89].d), // to internal hardware .qe (), @@ -7951,16 +9275,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_59_qs) + .qs (ip_2_p_89_qs) ); - // F[p_60]: 28:28 + // F[p_90]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_60 ( + ) u_ip_2_p_90 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7969,8 +9293,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[60].de), - .d (hw2reg.ip[60].d), + .de (hw2reg.ip[90].de), + .d (hw2reg.ip[90].d), // to internal hardware .qe (), @@ -7978,16 +9302,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_60_qs) + .qs (ip_2_p_90_qs) ); - // F[p_61]: 29:29 + // F[p_91]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_61 ( + ) u_ip_2_p_91 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -7996,8 +9320,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[61].de), - .d (hw2reg.ip[61].d), + .de (hw2reg.ip[91].de), + .d (hw2reg.ip[91].d), // to internal hardware .qe (), @@ -8005,16 +9329,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_61_qs) + .qs (ip_2_p_91_qs) ); - // F[p_62]: 30:30 + // F[p_92]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_62 ( + ) u_ip_2_p_92 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8023,8 +9347,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[62].de), - .d (hw2reg.ip[62].d), + .de (hw2reg.ip[92].de), + .d (hw2reg.ip[92].d), // to internal hardware .qe (), @@ -8032,16 +9356,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_62_qs) + .qs (ip_2_p_92_qs) ); - // F[p_63]: 31:31 + // F[p_93]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_1_p_63 ( + ) u_ip_2_p_93 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8050,8 +9374,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[63].de), - .d (hw2reg.ip[63].d), + .de (hw2reg.ip[93].de), + .d (hw2reg.ip[93].d), // to internal hardware .qe (), @@ -8059,19 +9383,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_1_p_63_qs) + .qs (ip_2_p_93_qs) ); - - // Subregister 2 of Multireg ip - // R[ip_2]: V(False) - // F[p_64]: 0:0 + // F[p_94]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_64 ( + ) u_ip_2_p_94 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8080,8 +9401,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[64].de), - .d (hw2reg.ip[64].d), + .de (hw2reg.ip[94].de), + .d (hw2reg.ip[94].d), // to internal hardware .qe (), @@ -8089,16 +9410,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_64_qs) + .qs (ip_2_p_94_qs) ); - // F[p_65]: 1:1 + // F[p_95]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_65 ( + ) u_ip_2_p_95 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8107,8 +9428,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[65].de), - .d (hw2reg.ip[65].d), + .de (hw2reg.ip[95].de), + .d (hw2reg.ip[95].d), // to internal hardware .qe (), @@ -8116,16 +9437,19 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_65_qs) + .qs (ip_2_p_95_qs) ); - // F[p_66]: 2:2 + + // Subregister 3 of Multireg ip + // R[ip_3]: V(False) + // F[p_96]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_66 ( + ) u_ip_3_p_96 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8134,8 +9458,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[66].de), - .d (hw2reg.ip[66].d), + .de (hw2reg.ip[96].de), + .d (hw2reg.ip[96].d), // to internal hardware .qe (), @@ -8143,16 +9467,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_66_qs) + .qs (ip_3_p_96_qs) ); - // F[p_67]: 3:3 + // F[p_97]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_67 ( + ) u_ip_3_p_97 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8161,8 +9485,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[67].de), - .d (hw2reg.ip[67].d), + .de (hw2reg.ip[97].de), + .d (hw2reg.ip[97].d), // to internal hardware .qe (), @@ -8170,16 +9494,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_67_qs) + .qs (ip_3_p_97_qs) ); - // F[p_68]: 4:4 + // F[p_98]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_68 ( + ) u_ip_3_p_98 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8188,8 +9512,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[68].de), - .d (hw2reg.ip[68].d), + .de (hw2reg.ip[98].de), + .d (hw2reg.ip[98].d), // to internal hardware .qe (), @@ -8197,16 +9521,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_68_qs) + .qs (ip_3_p_98_qs) ); - // F[p_69]: 5:5 + // F[p_99]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_69 ( + ) u_ip_3_p_99 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8215,8 +9539,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[69].de), - .d (hw2reg.ip[69].d), + .de (hw2reg.ip[99].de), + .d (hw2reg.ip[99].d), // to internal hardware .qe (), @@ -8224,16 +9548,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_69_qs) + .qs (ip_3_p_99_qs) ); - // F[p_70]: 6:6 + // F[p_100]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_70 ( + ) u_ip_3_p_100 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8242,8 +9566,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[70].de), - .d (hw2reg.ip[70].d), + .de (hw2reg.ip[100].de), + .d (hw2reg.ip[100].d), // to internal hardware .qe (), @@ -8251,16 +9575,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_70_qs) + .qs (ip_3_p_100_qs) ); - // F[p_71]: 7:7 + // F[p_101]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_71 ( + ) u_ip_3_p_101 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8269,8 +9593,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[71].de), - .d (hw2reg.ip[71].d), + .de (hw2reg.ip[101].de), + .d (hw2reg.ip[101].d), // to internal hardware .qe (), @@ -8278,16 +9602,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_71_qs) + .qs (ip_3_p_101_qs) ); - // F[p_72]: 8:8 + // F[p_102]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_72 ( + ) u_ip_3_p_102 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8296,8 +9620,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[72].de), - .d (hw2reg.ip[72].d), + .de (hw2reg.ip[102].de), + .d (hw2reg.ip[102].d), // to internal hardware .qe (), @@ -8305,16 +9629,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_72_qs) + .qs (ip_3_p_102_qs) ); - // F[p_73]: 9:9 + // F[p_103]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_73 ( + ) u_ip_3_p_103 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8323,8 +9647,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[73].de), - .d (hw2reg.ip[73].d), + .de (hw2reg.ip[103].de), + .d (hw2reg.ip[103].d), // to internal hardware .qe (), @@ -8332,16 +9656,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_73_qs) + .qs (ip_3_p_103_qs) ); - // F[p_74]: 10:10 + // F[p_104]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_74 ( + ) u_ip_3_p_104 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8350,8 +9674,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[74].de), - .d (hw2reg.ip[74].d), + .de (hw2reg.ip[104].de), + .d (hw2reg.ip[104].d), // to internal hardware .qe (), @@ -8359,16 +9683,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_74_qs) + .qs (ip_3_p_104_qs) ); - // F[p_75]: 11:11 + // F[p_105]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_75 ( + ) u_ip_3_p_105 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8377,8 +9701,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[75].de), - .d (hw2reg.ip[75].d), + .de (hw2reg.ip[105].de), + .d (hw2reg.ip[105].d), // to internal hardware .qe (), @@ -8386,16 +9710,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_75_qs) + .qs (ip_3_p_105_qs) ); - // F[p_76]: 12:12 + // F[p_106]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_76 ( + ) u_ip_3_p_106 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8404,8 +9728,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[76].de), - .d (hw2reg.ip[76].d), + .de (hw2reg.ip[106].de), + .d (hw2reg.ip[106].d), // to internal hardware .qe (), @@ -8413,16 +9737,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_76_qs) + .qs (ip_3_p_106_qs) ); - // F[p_77]: 13:13 + // F[p_107]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_77 ( + ) u_ip_3_p_107 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8431,8 +9755,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[77].de), - .d (hw2reg.ip[77].d), + .de (hw2reg.ip[107].de), + .d (hw2reg.ip[107].d), // to internal hardware .qe (), @@ -8440,16 +9764,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_77_qs) + .qs (ip_3_p_107_qs) ); - // F[p_78]: 14:14 + // F[p_108]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_78 ( + ) u_ip_3_p_108 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8458,8 +9782,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[78].de), - .d (hw2reg.ip[78].d), + .de (hw2reg.ip[108].de), + .d (hw2reg.ip[108].d), // to internal hardware .qe (), @@ -8467,16 +9791,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_78_qs) + .qs (ip_3_p_108_qs) ); - // F[p_79]: 15:15 + // F[p_109]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_79 ( + ) u_ip_3_p_109 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8485,8 +9809,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[79].de), - .d (hw2reg.ip[79].d), + .de (hw2reg.ip[109].de), + .d (hw2reg.ip[109].d), // to internal hardware .qe (), @@ -8494,16 +9818,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_79_qs) + .qs (ip_3_p_109_qs) ); - // F[p_80]: 16:16 + // F[p_110]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_80 ( + ) u_ip_3_p_110 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8512,8 +9836,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[80].de), - .d (hw2reg.ip[80].d), + .de (hw2reg.ip[110].de), + .d (hw2reg.ip[110].d), // to internal hardware .qe (), @@ -8521,16 +9845,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_80_qs) + .qs (ip_3_p_110_qs) ); - // F[p_81]: 17:17 + // F[p_111]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_81 ( + ) u_ip_3_p_111 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8539,8 +9863,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[81].de), - .d (hw2reg.ip[81].d), + .de (hw2reg.ip[111].de), + .d (hw2reg.ip[111].d), // to internal hardware .qe (), @@ -8548,16 +9872,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_81_qs) + .qs (ip_3_p_111_qs) ); - // F[p_82]: 18:18 + // F[p_112]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_82 ( + ) u_ip_3_p_112 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8566,8 +9890,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[82].de), - .d (hw2reg.ip[82].d), + .de (hw2reg.ip[112].de), + .d (hw2reg.ip[112].d), // to internal hardware .qe (), @@ -8575,16 +9899,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_82_qs) + .qs (ip_3_p_112_qs) ); - // F[p_83]: 19:19 + // F[p_113]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_83 ( + ) u_ip_3_p_113 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8593,8 +9917,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[83].de), - .d (hw2reg.ip[83].d), + .de (hw2reg.ip[113].de), + .d (hw2reg.ip[113].d), // to internal hardware .qe (), @@ -8602,16 +9926,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_83_qs) + .qs (ip_3_p_113_qs) ); - // F[p_84]: 20:20 + // F[p_114]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_84 ( + ) u_ip_3_p_114 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8620,8 +9944,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[84].de), - .d (hw2reg.ip[84].d), + .de (hw2reg.ip[114].de), + .d (hw2reg.ip[114].d), // to internal hardware .qe (), @@ -8629,16 +9953,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_84_qs) + .qs (ip_3_p_114_qs) ); - // F[p_85]: 21:21 + // F[p_115]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_85 ( + ) u_ip_3_p_115 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8647,8 +9971,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[85].de), - .d (hw2reg.ip[85].d), + .de (hw2reg.ip[115].de), + .d (hw2reg.ip[115].d), // to internal hardware .qe (), @@ -8656,16 +9980,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_85_qs) + .qs (ip_3_p_115_qs) ); - // F[p_86]: 22:22 + // F[p_116]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_86 ( + ) u_ip_3_p_116 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8674,8 +9998,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[86].de), - .d (hw2reg.ip[86].d), + .de (hw2reg.ip[116].de), + .d (hw2reg.ip[116].d), // to internal hardware .qe (), @@ -8683,16 +10007,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_86_qs) + .qs (ip_3_p_116_qs) ); - // F[p_87]: 23:23 + // F[p_117]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_87 ( + ) u_ip_3_p_117 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8701,8 +10025,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[87].de), - .d (hw2reg.ip[87].d), + .de (hw2reg.ip[117].de), + .d (hw2reg.ip[117].d), // to internal hardware .qe (), @@ -8710,16 +10034,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_87_qs) + .qs (ip_3_p_117_qs) ); - // F[p_88]: 24:24 + // F[p_118]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_88 ( + ) u_ip_3_p_118 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8728,8 +10052,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[88].de), - .d (hw2reg.ip[88].d), + .de (hw2reg.ip[118].de), + .d (hw2reg.ip[118].d), // to internal hardware .qe (), @@ -8737,16 +10061,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_88_qs) + .qs (ip_3_p_118_qs) ); - // F[p_89]: 25:25 + // F[p_119]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_89 ( + ) u_ip_3_p_119 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8755,8 +10079,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[89].de), - .d (hw2reg.ip[89].d), + .de (hw2reg.ip[119].de), + .d (hw2reg.ip[119].d), // to internal hardware .qe (), @@ -8764,16 +10088,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_89_qs) + .qs (ip_3_p_119_qs) ); - // F[p_90]: 26:26 + // F[p_120]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_90 ( + ) u_ip_3_p_120 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8782,8 +10106,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[90].de), - .d (hw2reg.ip[90].d), + .de (hw2reg.ip[120].de), + .d (hw2reg.ip[120].d), // to internal hardware .qe (), @@ -8791,16 +10115,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_90_qs) + .qs (ip_3_p_120_qs) ); - // F[p_91]: 27:27 + // F[p_121]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_91 ( + ) u_ip_3_p_121 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8809,8 +10133,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[91].de), - .d (hw2reg.ip[91].d), + .de (hw2reg.ip[121].de), + .d (hw2reg.ip[121].d), // to internal hardware .qe (), @@ -8818,16 +10142,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_91_qs) + .qs (ip_3_p_121_qs) ); - // F[p_92]: 28:28 + // F[p_122]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_92 ( + ) u_ip_3_p_122 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8836,8 +10160,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[92].de), - .d (hw2reg.ip[92].d), + .de (hw2reg.ip[122].de), + .d (hw2reg.ip[122].d), // to internal hardware .qe (), @@ -8845,16 +10169,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_92_qs) + .qs (ip_3_p_122_qs) ); - // F[p_93]: 29:29 + // F[p_123]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_93 ( + ) u_ip_3_p_123 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8863,8 +10187,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[93].de), - .d (hw2reg.ip[93].d), + .de (hw2reg.ip[123].de), + .d (hw2reg.ip[123].d), // to internal hardware .qe (), @@ -8872,16 +10196,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_93_qs) + .qs (ip_3_p_123_qs) ); - // F[p_94]: 30:30 + // F[p_124]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_94 ( + ) u_ip_3_p_124 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8890,8 +10214,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[94].de), - .d (hw2reg.ip[94].d), + .de (hw2reg.ip[124].de), + .d (hw2reg.ip[124].d), // to internal hardware .qe (), @@ -8899,16 +10223,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_94_qs) + .qs (ip_3_p_124_qs) ); - // F[p_95]: 31:31 + // F[p_125]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_2_p_95 ( + ) u_ip_3_p_125 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8917,8 +10241,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[95].de), - .d (hw2reg.ip[95].d), + .de (hw2reg.ip[125].de), + .d (hw2reg.ip[125].d), // to internal hardware .qe (), @@ -8926,19 +10250,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_2_p_95_qs) + .qs (ip_3_p_125_qs) ); - - // Subregister 3 of Multireg ip - // R[ip_3]: V(False) - // F[p_96]: 0:0 + // F[p_126]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_96 ( + ) u_ip_3_p_126 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8947,8 +10268,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[96].de), - .d (hw2reg.ip[96].d), + .de (hw2reg.ip[126].de), + .d (hw2reg.ip[126].d), // to internal hardware .qe (), @@ -8956,16 +10277,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_96_qs) + .qs (ip_3_p_126_qs) ); - // F[p_97]: 1:1 + // F[p_127]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_97 ( + ) u_ip_3_p_127 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -8974,8 +10295,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[97].de), - .d (hw2reg.ip[97].d), + .de (hw2reg.ip[127].de), + .d (hw2reg.ip[127].d), // to internal hardware .qe (), @@ -8983,16 +10304,19 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_97_qs) + .qs (ip_3_p_127_qs) ); - // F[p_98]: 2:2 + + // Subregister 4 of Multireg ip + // R[ip_4]: V(False) + // F[p_128]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_98 ( + ) u_ip_4_p_128 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9001,8 +10325,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[98].de), - .d (hw2reg.ip[98].d), + .de (hw2reg.ip[128].de), + .d (hw2reg.ip[128].d), // to internal hardware .qe (), @@ -9010,16 +10334,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_98_qs) + .qs (ip_4_p_128_qs) ); - // F[p_99]: 3:3 + // F[p_129]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_99 ( + ) u_ip_4_p_129 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9028,8 +10352,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[99].de), - .d (hw2reg.ip[99].d), + .de (hw2reg.ip[129].de), + .d (hw2reg.ip[129].d), // to internal hardware .qe (), @@ -9037,16 +10361,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_99_qs) + .qs (ip_4_p_129_qs) ); - // F[p_100]: 4:4 + // F[p_130]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_100 ( + ) u_ip_4_p_130 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9055,8 +10379,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[100].de), - .d (hw2reg.ip[100].d), + .de (hw2reg.ip[130].de), + .d (hw2reg.ip[130].d), // to internal hardware .qe (), @@ -9064,16 +10388,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_100_qs) + .qs (ip_4_p_130_qs) ); - // F[p_101]: 5:5 + // F[p_131]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_101 ( + ) u_ip_4_p_131 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9082,8 +10406,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[101].de), - .d (hw2reg.ip[101].d), + .de (hw2reg.ip[131].de), + .d (hw2reg.ip[131].d), // to internal hardware .qe (), @@ -9091,16 +10415,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_101_qs) + .qs (ip_4_p_131_qs) ); - // F[p_102]: 6:6 + // F[p_132]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_102 ( + ) u_ip_4_p_132 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9109,8 +10433,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[102].de), - .d (hw2reg.ip[102].d), + .de (hw2reg.ip[132].de), + .d (hw2reg.ip[132].d), // to internal hardware .qe (), @@ -9118,16 +10442,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_102_qs) + .qs (ip_4_p_132_qs) ); - // F[p_103]: 7:7 + // F[p_133]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_103 ( + ) u_ip_4_p_133 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9136,8 +10460,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[103].de), - .d (hw2reg.ip[103].d), + .de (hw2reg.ip[133].de), + .d (hw2reg.ip[133].d), // to internal hardware .qe (), @@ -9145,16 +10469,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_103_qs) + .qs (ip_4_p_133_qs) ); - // F[p_104]: 8:8 + // F[p_134]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_104 ( + ) u_ip_4_p_134 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9163,8 +10487,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[104].de), - .d (hw2reg.ip[104].d), + .de (hw2reg.ip[134].de), + .d (hw2reg.ip[134].d), // to internal hardware .qe (), @@ -9172,16 +10496,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_104_qs) + .qs (ip_4_p_134_qs) ); - // F[p_105]: 9:9 + // F[p_135]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_105 ( + ) u_ip_4_p_135 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9190,8 +10514,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[105].de), - .d (hw2reg.ip[105].d), + .de (hw2reg.ip[135].de), + .d (hw2reg.ip[135].d), // to internal hardware .qe (), @@ -9199,16 +10523,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_105_qs) + .qs (ip_4_p_135_qs) ); - // F[p_106]: 10:10 + // F[p_136]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_106 ( + ) u_ip_4_p_136 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9217,8 +10541,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[106].de), - .d (hw2reg.ip[106].d), + .de (hw2reg.ip[136].de), + .d (hw2reg.ip[136].d), // to internal hardware .qe (), @@ -9226,16 +10550,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_106_qs) + .qs (ip_4_p_136_qs) ); - // F[p_107]: 11:11 + // F[p_137]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_107 ( + ) u_ip_4_p_137 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9244,8 +10568,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[107].de), - .d (hw2reg.ip[107].d), + .de (hw2reg.ip[137].de), + .d (hw2reg.ip[137].d), // to internal hardware .qe (), @@ -9253,16 +10577,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_107_qs) + .qs (ip_4_p_137_qs) ); - // F[p_108]: 12:12 + // F[p_138]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_108 ( + ) u_ip_4_p_138 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9271,8 +10595,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[108].de), - .d (hw2reg.ip[108].d), + .de (hw2reg.ip[138].de), + .d (hw2reg.ip[138].d), // to internal hardware .qe (), @@ -9280,16 +10604,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_108_qs) + .qs (ip_4_p_138_qs) ); - // F[p_109]: 13:13 + // F[p_139]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_109 ( + ) u_ip_4_p_139 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9298,8 +10622,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[109].de), - .d (hw2reg.ip[109].d), + .de (hw2reg.ip[139].de), + .d (hw2reg.ip[139].d), // to internal hardware .qe (), @@ -9307,16 +10631,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_109_qs) + .qs (ip_4_p_139_qs) ); - // F[p_110]: 14:14 + // F[p_140]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_110 ( + ) u_ip_4_p_140 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9325,8 +10649,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[110].de), - .d (hw2reg.ip[110].d), + .de (hw2reg.ip[140].de), + .d (hw2reg.ip[140].d), // to internal hardware .qe (), @@ -9334,16 +10658,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_110_qs) + .qs (ip_4_p_140_qs) ); - // F[p_111]: 15:15 + // F[p_141]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_111 ( + ) u_ip_4_p_141 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9352,8 +10676,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[111].de), - .d (hw2reg.ip[111].d), + .de (hw2reg.ip[141].de), + .d (hw2reg.ip[141].d), // to internal hardware .qe (), @@ -9361,16 +10685,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_111_qs) + .qs (ip_4_p_141_qs) ); - // F[p_112]: 16:16 + // F[p_142]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_112 ( + ) u_ip_4_p_142 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9379,8 +10703,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[112].de), - .d (hw2reg.ip[112].d), + .de (hw2reg.ip[142].de), + .d (hw2reg.ip[142].d), // to internal hardware .qe (), @@ -9388,16 +10712,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_112_qs) + .qs (ip_4_p_142_qs) ); - // F[p_113]: 17:17 + // F[p_143]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_113 ( + ) u_ip_4_p_143 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9406,8 +10730,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[113].de), - .d (hw2reg.ip[113].d), + .de (hw2reg.ip[143].de), + .d (hw2reg.ip[143].d), // to internal hardware .qe (), @@ -9415,16 +10739,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_113_qs) + .qs (ip_4_p_143_qs) ); - // F[p_114]: 18:18 + // F[p_144]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_114 ( + ) u_ip_4_p_144 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9433,8 +10757,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[114].de), - .d (hw2reg.ip[114].d), + .de (hw2reg.ip[144].de), + .d (hw2reg.ip[144].d), // to internal hardware .qe (), @@ -9442,16 +10766,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_114_qs) + .qs (ip_4_p_144_qs) ); - // F[p_115]: 19:19 + // F[p_145]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_115 ( + ) u_ip_4_p_145 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9460,8 +10784,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[115].de), - .d (hw2reg.ip[115].d), + .de (hw2reg.ip[145].de), + .d (hw2reg.ip[145].d), // to internal hardware .qe (), @@ -9469,16 +10793,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_115_qs) + .qs (ip_4_p_145_qs) ); - // F[p_116]: 20:20 + // F[p_146]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_116 ( + ) u_ip_4_p_146 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9487,8 +10811,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[116].de), - .d (hw2reg.ip[116].d), + .de (hw2reg.ip[146].de), + .d (hw2reg.ip[146].d), // to internal hardware .qe (), @@ -9496,16 +10820,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_116_qs) + .qs (ip_4_p_146_qs) ); - // F[p_117]: 21:21 + // F[p_147]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_117 ( + ) u_ip_4_p_147 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9514,8 +10838,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[117].de), - .d (hw2reg.ip[117].d), + .de (hw2reg.ip[147].de), + .d (hw2reg.ip[147].d), // to internal hardware .qe (), @@ -9523,16 +10847,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_117_qs) + .qs (ip_4_p_147_qs) ); - // F[p_118]: 22:22 + // F[p_148]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_118 ( + ) u_ip_4_p_148 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9541,8 +10865,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[118].de), - .d (hw2reg.ip[118].d), + .de (hw2reg.ip[148].de), + .d (hw2reg.ip[148].d), // to internal hardware .qe (), @@ -9550,16 +10874,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_118_qs) + .qs (ip_4_p_148_qs) ); - // F[p_119]: 23:23 + // F[p_149]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_119 ( + ) u_ip_4_p_149 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9568,8 +10892,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[119].de), - .d (hw2reg.ip[119].d), + .de (hw2reg.ip[149].de), + .d (hw2reg.ip[149].d), // to internal hardware .qe (), @@ -9577,16 +10901,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_119_qs) + .qs (ip_4_p_149_qs) ); - // F[p_120]: 24:24 + // F[p_150]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_120 ( + ) u_ip_4_p_150 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9595,8 +10919,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[120].de), - .d (hw2reg.ip[120].d), + .de (hw2reg.ip[150].de), + .d (hw2reg.ip[150].d), // to internal hardware .qe (), @@ -9604,16 +10928,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_120_qs) + .qs (ip_4_p_150_qs) ); - // F[p_121]: 25:25 + // F[p_151]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_121 ( + ) u_ip_4_p_151 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9622,8 +10946,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[121].de), - .d (hw2reg.ip[121].d), + .de (hw2reg.ip[151].de), + .d (hw2reg.ip[151].d), // to internal hardware .qe (), @@ -9631,16 +10955,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_121_qs) + .qs (ip_4_p_151_qs) ); - // F[p_122]: 26:26 + // F[p_152]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_122 ( + ) u_ip_4_p_152 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9649,8 +10973,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[122].de), - .d (hw2reg.ip[122].d), + .de (hw2reg.ip[152].de), + .d (hw2reg.ip[152].d), // to internal hardware .qe (), @@ -9658,16 +10982,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_122_qs) + .qs (ip_4_p_152_qs) ); - // F[p_123]: 27:27 + // F[p_153]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_123 ( + ) u_ip_4_p_153 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9676,8 +11000,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[123].de), - .d (hw2reg.ip[123].d), + .de (hw2reg.ip[153].de), + .d (hw2reg.ip[153].d), // to internal hardware .qe (), @@ -9685,16 +11009,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_123_qs) + .qs (ip_4_p_153_qs) ); - // F[p_124]: 28:28 + // F[p_154]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_124 ( + ) u_ip_4_p_154 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9703,8 +11027,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[124].de), - .d (hw2reg.ip[124].d), + .de (hw2reg.ip[154].de), + .d (hw2reg.ip[154].d), // to internal hardware .qe (), @@ -9712,16 +11036,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_124_qs) + .qs (ip_4_p_154_qs) ); - // F[p_125]: 29:29 + // F[p_155]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_125 ( + ) u_ip_4_p_155 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9730,8 +11054,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[125].de), - .d (hw2reg.ip[125].d), + .de (hw2reg.ip[155].de), + .d (hw2reg.ip[155].d), // to internal hardware .qe (), @@ -9739,16 +11063,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_125_qs) + .qs (ip_4_p_155_qs) ); - // F[p_126]: 30:30 + // F[p_156]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_126 ( + ) u_ip_4_p_156 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9757,8 +11081,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[126].de), - .d (hw2reg.ip[126].d), + .de (hw2reg.ip[156].de), + .d (hw2reg.ip[156].d), // to internal hardware .qe (), @@ -9766,16 +11090,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_126_qs) + .qs (ip_4_p_156_qs) ); - // F[p_127]: 31:31 + // F[p_157]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_3_p_127 ( + ) u_ip_4_p_157 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9784,8 +11108,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[127].de), - .d (hw2reg.ip[127].d), + .de (hw2reg.ip[157].de), + .d (hw2reg.ip[157].d), // to internal hardware .qe (), @@ -9793,19 +11117,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_3_p_127_qs) + .qs (ip_4_p_157_qs) ); - - // Subregister 4 of Multireg ip - // R[ip_4]: V(False) - // F[p_128]: 0:0 + // F[p_158]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_128 ( + ) u_ip_4_p_158 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9814,8 +11135,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[128].de), - .d (hw2reg.ip[128].d), + .de (hw2reg.ip[158].de), + .d (hw2reg.ip[158].d), // to internal hardware .qe (), @@ -9823,16 +11144,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_128_qs) + .qs (ip_4_p_158_qs) ); - // F[p_129]: 1:1 + // F[p_159]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_129 ( + ) u_ip_4_p_159 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9841,8 +11162,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[129].de), - .d (hw2reg.ip[129].d), + .de (hw2reg.ip[159].de), + .d (hw2reg.ip[159].d), // to internal hardware .qe (), @@ -9850,16 +11171,19 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_129_qs) + .qs (ip_4_p_159_qs) ); - // F[p_130]: 2:2 + + // Subregister 5 of Multireg ip + // R[ip_5]: V(False) + // F[p_160]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_130 ( + ) u_ip_5_p_160 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9868,8 +11192,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[130].de), - .d (hw2reg.ip[130].d), + .de (hw2reg.ip[160].de), + .d (hw2reg.ip[160].d), // to internal hardware .qe (), @@ -9877,16 +11201,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_130_qs) + .qs (ip_5_p_160_qs) ); - // F[p_131]: 3:3 + // F[p_161]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_131 ( + ) u_ip_5_p_161 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9895,8 +11219,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[131].de), - .d (hw2reg.ip[131].d), + .de (hw2reg.ip[161].de), + .d (hw2reg.ip[161].d), // to internal hardware .qe (), @@ -9904,16 +11228,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_131_qs) + .qs (ip_5_p_161_qs) ); - // F[p_132]: 4:4 + // F[p_162]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_132 ( + ) u_ip_5_p_162 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9922,8 +11246,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[132].de), - .d (hw2reg.ip[132].d), + .de (hw2reg.ip[162].de), + .d (hw2reg.ip[162].d), // to internal hardware .qe (), @@ -9931,16 +11255,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_132_qs) + .qs (ip_5_p_162_qs) ); - // F[p_133]: 5:5 + // F[p_163]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_133 ( + ) u_ip_5_p_163 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9949,8 +11273,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[133].de), - .d (hw2reg.ip[133].d), + .de (hw2reg.ip[163].de), + .d (hw2reg.ip[163].d), // to internal hardware .qe (), @@ -9958,16 +11282,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_133_qs) + .qs (ip_5_p_163_qs) ); - // F[p_134]: 6:6 + // F[p_164]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_134 ( + ) u_ip_5_p_164 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -9976,8 +11300,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[134].de), - .d (hw2reg.ip[134].d), + .de (hw2reg.ip[164].de), + .d (hw2reg.ip[164].d), // to internal hardware .qe (), @@ -9985,16 +11309,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_134_qs) + .qs (ip_5_p_164_qs) ); - // F[p_135]: 7:7 + // F[p_165]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_135 ( + ) u_ip_5_p_165 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10003,8 +11327,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[135].de), - .d (hw2reg.ip[135].d), + .de (hw2reg.ip[165].de), + .d (hw2reg.ip[165].d), // to internal hardware .qe (), @@ -10012,16 +11336,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_135_qs) + .qs (ip_5_p_165_qs) ); - // F[p_136]: 8:8 + // F[p_166]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_136 ( + ) u_ip_5_p_166 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10030,8 +11354,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[136].de), - .d (hw2reg.ip[136].d), + .de (hw2reg.ip[166].de), + .d (hw2reg.ip[166].d), // to internal hardware .qe (), @@ -10039,16 +11363,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_136_qs) + .qs (ip_5_p_166_qs) ); - // F[p_137]: 9:9 + // F[p_167]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_137 ( + ) u_ip_5_p_167 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10057,8 +11381,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[137].de), - .d (hw2reg.ip[137].d), + .de (hw2reg.ip[167].de), + .d (hw2reg.ip[167].d), // to internal hardware .qe (), @@ -10066,16 +11390,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_137_qs) + .qs (ip_5_p_167_qs) ); - // F[p_138]: 10:10 + // F[p_168]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_138 ( + ) u_ip_5_p_168 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10084,8 +11408,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[138].de), - .d (hw2reg.ip[138].d), + .de (hw2reg.ip[168].de), + .d (hw2reg.ip[168].d), // to internal hardware .qe (), @@ -10093,16 +11417,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_138_qs) + .qs (ip_5_p_168_qs) ); - // F[p_139]: 11:11 + // F[p_169]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_139 ( + ) u_ip_5_p_169 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10111,8 +11435,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[139].de), - .d (hw2reg.ip[139].d), + .de (hw2reg.ip[169].de), + .d (hw2reg.ip[169].d), // to internal hardware .qe (), @@ -10120,16 +11444,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_139_qs) + .qs (ip_5_p_169_qs) ); - // F[p_140]: 12:12 + // F[p_170]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_140 ( + ) u_ip_5_p_170 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10138,8 +11462,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[140].de), - .d (hw2reg.ip[140].d), + .de (hw2reg.ip[170].de), + .d (hw2reg.ip[170].d), // to internal hardware .qe (), @@ -10147,16 +11471,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_140_qs) + .qs (ip_5_p_170_qs) ); - // F[p_141]: 13:13 + // F[p_171]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_141 ( + ) u_ip_5_p_171 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10165,8 +11489,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[141].de), - .d (hw2reg.ip[141].d), + .de (hw2reg.ip[171].de), + .d (hw2reg.ip[171].d), // to internal hardware .qe (), @@ -10174,16 +11498,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_141_qs) + .qs (ip_5_p_171_qs) ); - // F[p_142]: 14:14 + // F[p_172]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_142 ( + ) u_ip_5_p_172 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10192,8 +11516,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[142].de), - .d (hw2reg.ip[142].d), + .de (hw2reg.ip[172].de), + .d (hw2reg.ip[172].d), // to internal hardware .qe (), @@ -10201,16 +11525,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_142_qs) + .qs (ip_5_p_172_qs) ); - // F[p_143]: 15:15 + // F[p_173]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_143 ( + ) u_ip_5_p_173 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10219,8 +11543,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[143].de), - .d (hw2reg.ip[143].d), + .de (hw2reg.ip[173].de), + .d (hw2reg.ip[173].d), // to internal hardware .qe (), @@ -10228,16 +11552,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_143_qs) + .qs (ip_5_p_173_qs) ); - // F[p_144]: 16:16 + // F[p_174]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_144 ( + ) u_ip_5_p_174 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10246,8 +11570,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[144].de), - .d (hw2reg.ip[144].d), + .de (hw2reg.ip[174].de), + .d (hw2reg.ip[174].d), // to internal hardware .qe (), @@ -10255,16 +11579,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_144_qs) + .qs (ip_5_p_174_qs) ); - // F[p_145]: 17:17 + // F[p_175]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_145 ( + ) u_ip_5_p_175 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10273,8 +11597,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[145].de), - .d (hw2reg.ip[145].d), + .de (hw2reg.ip[175].de), + .d (hw2reg.ip[175].d), // to internal hardware .qe (), @@ -10282,16 +11606,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_145_qs) + .qs (ip_5_p_175_qs) ); - // F[p_146]: 18:18 + // F[p_176]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_146 ( + ) u_ip_5_p_176 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10300,8 +11624,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[146].de), - .d (hw2reg.ip[146].d), + .de (hw2reg.ip[176].de), + .d (hw2reg.ip[176].d), // to internal hardware .qe (), @@ -10309,16 +11633,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_146_qs) + .qs (ip_5_p_176_qs) ); - // F[p_147]: 19:19 + // F[p_177]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_147 ( + ) u_ip_5_p_177 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10327,8 +11651,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[147].de), - .d (hw2reg.ip[147].d), + .de (hw2reg.ip[177].de), + .d (hw2reg.ip[177].d), // to internal hardware .qe (), @@ -10336,16 +11660,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_147_qs) + .qs (ip_5_p_177_qs) ); - // F[p_148]: 20:20 + // F[p_178]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_148 ( + ) u_ip_5_p_178 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10354,8 +11678,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[148].de), - .d (hw2reg.ip[148].d), + .de (hw2reg.ip[178].de), + .d (hw2reg.ip[178].d), // to internal hardware .qe (), @@ -10363,16 +11687,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_148_qs) + .qs (ip_5_p_178_qs) ); - // F[p_149]: 21:21 + // F[p_179]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_149 ( + ) u_ip_5_p_179 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10381,8 +11705,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[149].de), - .d (hw2reg.ip[149].d), + .de (hw2reg.ip[179].de), + .d (hw2reg.ip[179].d), // to internal hardware .qe (), @@ -10390,16 +11714,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_149_qs) + .qs (ip_5_p_179_qs) ); - // F[p_150]: 22:22 + // F[p_180]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_150 ( + ) u_ip_5_p_180 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10408,8 +11732,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[150].de), - .d (hw2reg.ip[150].d), + .de (hw2reg.ip[180].de), + .d (hw2reg.ip[180].d), // to internal hardware .qe (), @@ -10417,16 +11741,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_150_qs) + .qs (ip_5_p_180_qs) ); - // F[p_151]: 23:23 + // F[p_181]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_151 ( + ) u_ip_5_p_181 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10435,8 +11759,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[151].de), - .d (hw2reg.ip[151].d), + .de (hw2reg.ip[181].de), + .d (hw2reg.ip[181].d), // to internal hardware .qe (), @@ -10444,16 +11768,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_151_qs) + .qs (ip_5_p_181_qs) ); - // F[p_152]: 24:24 + // F[p_182]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_152 ( + ) u_ip_5_p_182 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10462,8 +11786,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[152].de), - .d (hw2reg.ip[152].d), + .de (hw2reg.ip[182].de), + .d (hw2reg.ip[182].d), // to internal hardware .qe (), @@ -10471,16 +11795,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_152_qs) + .qs (ip_5_p_182_qs) ); - // F[p_153]: 25:25 + // F[p_183]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_153 ( + ) u_ip_5_p_183 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10489,8 +11813,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[153].de), - .d (hw2reg.ip[153].d), + .de (hw2reg.ip[183].de), + .d (hw2reg.ip[183].d), // to internal hardware .qe (), @@ -10498,16 +11822,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_153_qs) + .qs (ip_5_p_183_qs) ); - // F[p_154]: 26:26 + // F[p_184]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_154 ( + ) u_ip_5_p_184 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10516,8 +11840,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[154].de), - .d (hw2reg.ip[154].d), + .de (hw2reg.ip[184].de), + .d (hw2reg.ip[184].d), // to internal hardware .qe (), @@ -10525,16 +11849,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_154_qs) + .qs (ip_5_p_184_qs) ); - // F[p_155]: 27:27 + // F[p_185]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_155 ( + ) u_ip_5_p_185 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10543,8 +11867,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[155].de), - .d (hw2reg.ip[155].d), + .de (hw2reg.ip[185].de), + .d (hw2reg.ip[185].d), // to internal hardware .qe (), @@ -10552,16 +11876,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_155_qs) + .qs (ip_5_p_185_qs) ); - // F[p_156]: 28:28 + // F[p_186]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_156 ( + ) u_ip_5_p_186 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10570,8 +11894,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[156].de), - .d (hw2reg.ip[156].d), + .de (hw2reg.ip[186].de), + .d (hw2reg.ip[186].d), // to internal hardware .qe (), @@ -10579,16 +11903,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_156_qs) + .qs (ip_5_p_186_qs) ); - // F[p_157]: 29:29 + // F[p_187]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_157 ( + ) u_ip_5_p_187 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10597,8 +11921,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[157].de), - .d (hw2reg.ip[157].d), + .de (hw2reg.ip[187].de), + .d (hw2reg.ip[187].d), // to internal hardware .qe (), @@ -10606,16 +11930,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_157_qs) + .qs (ip_5_p_187_qs) ); - // F[p_158]: 30:30 + // F[p_188]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_158 ( + ) u_ip_5_p_188 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10624,8 +11948,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[158].de), - .d (hw2reg.ip[158].d), + .de (hw2reg.ip[188].de), + .d (hw2reg.ip[188].d), // to internal hardware .qe (), @@ -10633,16 +11957,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_158_qs) + .qs (ip_5_p_188_qs) ); - // F[p_159]: 31:31 + // F[p_189]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_4_p_159 ( + ) u_ip_5_p_189 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10651,8 +11975,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[159].de), - .d (hw2reg.ip[159].d), + .de (hw2reg.ip[189].de), + .d (hw2reg.ip[189].d), // to internal hardware .qe (), @@ -10660,19 +11984,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_4_p_159_qs) + .qs (ip_5_p_189_qs) ); - - // Subregister 5 of Multireg ip - // R[ip_5]: V(False) - // F[p_160]: 0:0 + // F[p_190]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_160 ( + ) u_ip_5_p_190 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10681,8 +12002,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[160].de), - .d (hw2reg.ip[160].d), + .de (hw2reg.ip[190].de), + .d (hw2reg.ip[190].d), // to internal hardware .qe (), @@ -10690,16 +12011,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_5_p_160_qs) + .qs (ip_5_p_190_qs) ); - // F[p_161]: 1:1 + // F[p_191]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_161 ( + ) u_ip_5_p_191 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10708,8 +12029,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[161].de), - .d (hw2reg.ip[161].d), + .de (hw2reg.ip[191].de), + .d (hw2reg.ip[191].d), // to internal hardware .qe (), @@ -10717,16 +12038,19 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_5_p_161_qs) + .qs (ip_5_p_191_qs) ); - // F[p_162]: 2:2 + + // Subregister 6 of Multireg ip + // R[ip_6]: V(False) + // F[p_192]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_162 ( + ) u_ip_6_p_192 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10735,8 +12059,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[162].de), - .d (hw2reg.ip[162].d), + .de (hw2reg.ip[192].de), + .d (hw2reg.ip[192].d), // to internal hardware .qe (), @@ -10744,16 +12068,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_5_p_162_qs) + .qs (ip_6_p_192_qs) ); - // F[p_163]: 3:3 + // F[p_193]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_163 ( + ) u_ip_6_p_193 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10762,8 +12086,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[163].de), - .d (hw2reg.ip[163].d), + .de (hw2reg.ip[193].de), + .d (hw2reg.ip[193].d), // to internal hardware .qe (), @@ -10771,16 +12095,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_5_p_163_qs) + .qs (ip_6_p_193_qs) ); - // F[p_164]: 4:4 + // F[p_194]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_164 ( + ) u_ip_6_p_194 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10789,8 +12113,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[164].de), - .d (hw2reg.ip[164].d), + .de (hw2reg.ip[194].de), + .d (hw2reg.ip[194].d), // to internal hardware .qe (), @@ -10798,16 +12122,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_5_p_164_qs) + .qs (ip_6_p_194_qs) ); - // F[p_165]: 5:5 + // F[p_195]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_165 ( + ) u_ip_6_p_195 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10816,8 +12140,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[165].de), - .d (hw2reg.ip[165].d), + .de (hw2reg.ip[195].de), + .d (hw2reg.ip[195].d), // to internal hardware .qe (), @@ -10825,16 +12149,16 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_5_p_165_qs) + .qs (ip_6_p_195_qs) ); - // F[p_166]: 6:6 + // F[p_196]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_166 ( + ) u_ip_6_p_196 ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -10843,8 +12167,8 @@ module rv_plic_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.ip[166].de), - .d (hw2reg.ip[166].d), + .de (hw2reg.ip[196].de), + .d (hw2reg.ip[196].d), // to internal hardware .qe (), @@ -10852,430 +12176,430 @@ module rv_plic_reg_top ( .ds (), // to register interface (read) - .qs (ip_5_p_166_qs) + .qs (ip_6_p_196_qs) ); - // F[p_167]: 7:7 + + // Subregister 0 of Multireg ie0 + // R[ie0_0]: V(False) + // F[e_0]: 0:0 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_167 ( + ) u_ie0_0_e_0 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_0_wd), // from internal hardware - .de (hw2reg.ip[167].de), - .d (hw2reg.ip[167].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[0].q), .ds (), // to register interface (read) - .qs (ip_5_p_167_qs) + .qs (ie0_0_e_0_qs) ); - // F[p_168]: 8:8 + // F[e_1]: 1:1 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_168 ( + ) u_ie0_0_e_1 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_1_wd), // from internal hardware - .de (hw2reg.ip[168].de), - .d (hw2reg.ip[168].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[1].q), .ds (), // to register interface (read) - .qs (ip_5_p_168_qs) + .qs (ie0_0_e_1_qs) ); - // F[p_169]: 9:9 + // F[e_2]: 2:2 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_169 ( + ) u_ie0_0_e_2 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_2_wd), // from internal hardware - .de (hw2reg.ip[169].de), - .d (hw2reg.ip[169].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[2].q), .ds (), // to register interface (read) - .qs (ip_5_p_169_qs) + .qs (ie0_0_e_2_qs) ); - // F[p_170]: 10:10 + // F[e_3]: 3:3 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_170 ( + ) u_ie0_0_e_3 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_3_wd), // from internal hardware - .de (hw2reg.ip[170].de), - .d (hw2reg.ip[170].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[3].q), .ds (), // to register interface (read) - .qs (ip_5_p_170_qs) + .qs (ie0_0_e_3_qs) ); - // F[p_171]: 11:11 + // F[e_4]: 4:4 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_171 ( + ) u_ie0_0_e_4 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_4_wd), // from internal hardware - .de (hw2reg.ip[171].de), - .d (hw2reg.ip[171].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[4].q), .ds (), // to register interface (read) - .qs (ip_5_p_171_qs) + .qs (ie0_0_e_4_qs) ); - // F[p_172]: 12:12 + // F[e_5]: 5:5 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_172 ( + ) u_ie0_0_e_5 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_5_wd), // from internal hardware - .de (hw2reg.ip[172].de), - .d (hw2reg.ip[172].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[5].q), .ds (), // to register interface (read) - .qs (ip_5_p_172_qs) + .qs (ie0_0_e_5_qs) ); - // F[p_173]: 13:13 + // F[e_6]: 6:6 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_173 ( + ) u_ie0_0_e_6 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_6_wd), // from internal hardware - .de (hw2reg.ip[173].de), - .d (hw2reg.ip[173].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[6].q), .ds (), // to register interface (read) - .qs (ip_5_p_173_qs) + .qs (ie0_0_e_6_qs) ); - // F[p_174]: 14:14 + // F[e_7]: 7:7 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_174 ( + ) u_ie0_0_e_7 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_7_wd), // from internal hardware - .de (hw2reg.ip[174].de), - .d (hw2reg.ip[174].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[7].q), .ds (), // to register interface (read) - .qs (ip_5_p_174_qs) + .qs (ie0_0_e_7_qs) ); - // F[p_175]: 15:15 + // F[e_8]: 8:8 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_175 ( + ) u_ie0_0_e_8 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_8_wd), // from internal hardware - .de (hw2reg.ip[175].de), - .d (hw2reg.ip[175].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[8].q), .ds (), // to register interface (read) - .qs (ip_5_p_175_qs) + .qs (ie0_0_e_8_qs) ); - // F[p_176]: 16:16 + // F[e_9]: 9:9 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_176 ( + ) u_ie0_0_e_9 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_9_wd), // from internal hardware - .de (hw2reg.ip[176].de), - .d (hw2reg.ip[176].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[9].q), .ds (), // to register interface (read) - .qs (ip_5_p_176_qs) + .qs (ie0_0_e_9_qs) ); - // F[p_177]: 17:17 + // F[e_10]: 10:10 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_177 ( + ) u_ie0_0_e_10 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_10_wd), // from internal hardware - .de (hw2reg.ip[177].de), - .d (hw2reg.ip[177].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[10].q), .ds (), // to register interface (read) - .qs (ip_5_p_177_qs) + .qs (ie0_0_e_10_qs) ); - // F[p_178]: 18:18 + // F[e_11]: 11:11 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_178 ( + ) u_ie0_0_e_11 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_11_wd), // from internal hardware - .de (hw2reg.ip[178].de), - .d (hw2reg.ip[178].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[11].q), .ds (), // to register interface (read) - .qs (ip_5_p_178_qs) + .qs (ie0_0_e_11_qs) ); - // F[p_179]: 19:19 + // F[e_12]: 12:12 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_179 ( + ) u_ie0_0_e_12 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_12_wd), // from internal hardware - .de (hw2reg.ip[179].de), - .d (hw2reg.ip[179].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[12].q), .ds (), // to register interface (read) - .qs (ip_5_p_179_qs) + .qs (ie0_0_e_12_qs) ); - // F[p_180]: 20:20 + // F[e_13]: 13:13 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_180 ( + ) u_ie0_0_e_13 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_13_wd), // from internal hardware - .de (hw2reg.ip[180].de), - .d (hw2reg.ip[180].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[13].q), .ds (), // to register interface (read) - .qs (ip_5_p_180_qs) + .qs (ie0_0_e_13_qs) ); - // F[p_181]: 21:21 + // F[e_14]: 14:14 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ip_5_p_181 ( + ) u_ie0_0_e_14 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (1'b0), - .wd ('0), + .we (ie0_0_we), + .wd (ie0_0_e_14_wd), // from internal hardware - .de (hw2reg.ip[181].de), - .d (hw2reg.ip[181].d), + .de (1'b0), + .d ('0), // to internal hardware .qe (), - .q (), + .q (reg2hw.ie0[14].q), .ds (), // to register interface (read) - .qs (ip_5_p_181_qs) + .qs (ie0_0_e_14_qs) ); - - // Subregister 0 of Multireg ie0 - // R[ie0_0]: V(False) - // F[e_0]: 0:0 + // F[e_15]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_0 ( + ) u_ie0_0_e_15 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_0_wd), + .wd (ie0_0_e_15_wd), // from internal hardware .de (1'b0), @@ -11283,26 +12607,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[0].q), + .q (reg2hw.ie0[15].q), .ds (), // to register interface (read) - .qs (ie0_0_e_0_qs) + .qs (ie0_0_e_15_qs) ); - // F[e_1]: 1:1 + // F[e_16]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_1 ( + ) u_ie0_0_e_16 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_1_wd), + .wd (ie0_0_e_16_wd), // from internal hardware .de (1'b0), @@ -11310,26 +12634,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[1].q), + .q (reg2hw.ie0[16].q), .ds (), // to register interface (read) - .qs (ie0_0_e_1_qs) + .qs (ie0_0_e_16_qs) ); - // F[e_2]: 2:2 + // F[e_17]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_2 ( + ) u_ie0_0_e_17 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_2_wd), + .wd (ie0_0_e_17_wd), // from internal hardware .de (1'b0), @@ -11337,26 +12661,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[2].q), + .q (reg2hw.ie0[17].q), .ds (), // to register interface (read) - .qs (ie0_0_e_2_qs) + .qs (ie0_0_e_17_qs) ); - // F[e_3]: 3:3 + // F[e_18]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_3 ( + ) u_ie0_0_e_18 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_3_wd), + .wd (ie0_0_e_18_wd), // from internal hardware .de (1'b0), @@ -11364,26 +12688,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[3].q), + .q (reg2hw.ie0[18].q), .ds (), // to register interface (read) - .qs (ie0_0_e_3_qs) + .qs (ie0_0_e_18_qs) ); - // F[e_4]: 4:4 + // F[e_19]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_4 ( + ) u_ie0_0_e_19 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_4_wd), + .wd (ie0_0_e_19_wd), // from internal hardware .de (1'b0), @@ -11391,26 +12715,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[4].q), + .q (reg2hw.ie0[19].q), .ds (), // to register interface (read) - .qs (ie0_0_e_4_qs) + .qs (ie0_0_e_19_qs) ); - // F[e_5]: 5:5 + // F[e_20]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_5 ( + ) u_ie0_0_e_20 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_5_wd), + .wd (ie0_0_e_20_wd), // from internal hardware .de (1'b0), @@ -11418,26 +12742,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[5].q), + .q (reg2hw.ie0[20].q), .ds (), // to register interface (read) - .qs (ie0_0_e_5_qs) + .qs (ie0_0_e_20_qs) ); - // F[e_6]: 6:6 + // F[e_21]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_6 ( + ) u_ie0_0_e_21 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_6_wd), + .wd (ie0_0_e_21_wd), // from internal hardware .de (1'b0), @@ -11445,26 +12769,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[6].q), + .q (reg2hw.ie0[21].q), .ds (), // to register interface (read) - .qs (ie0_0_e_6_qs) + .qs (ie0_0_e_21_qs) ); - // F[e_7]: 7:7 + // F[e_22]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_7 ( + ) u_ie0_0_e_22 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_7_wd), + .wd (ie0_0_e_22_wd), // from internal hardware .de (1'b0), @@ -11472,26 +12796,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[7].q), + .q (reg2hw.ie0[22].q), .ds (), // to register interface (read) - .qs (ie0_0_e_7_qs) + .qs (ie0_0_e_22_qs) ); - // F[e_8]: 8:8 + // F[e_23]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_8 ( + ) u_ie0_0_e_23 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_8_wd), + .wd (ie0_0_e_23_wd), // from internal hardware .de (1'b0), @@ -11499,26 +12823,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[8].q), + .q (reg2hw.ie0[23].q), .ds (), // to register interface (read) - .qs (ie0_0_e_8_qs) + .qs (ie0_0_e_23_qs) ); - // F[e_9]: 9:9 + // F[e_24]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_9 ( + ) u_ie0_0_e_24 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_9_wd), + .wd (ie0_0_e_24_wd), // from internal hardware .de (1'b0), @@ -11526,26 +12850,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[9].q), + .q (reg2hw.ie0[24].q), .ds (), // to register interface (read) - .qs (ie0_0_e_9_qs) + .qs (ie0_0_e_24_qs) ); - // F[e_10]: 10:10 + // F[e_25]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_10 ( + ) u_ie0_0_e_25 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_10_wd), + .wd (ie0_0_e_25_wd), // from internal hardware .de (1'b0), @@ -11553,26 +12877,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[10].q), + .q (reg2hw.ie0[25].q), .ds (), // to register interface (read) - .qs (ie0_0_e_10_qs) + .qs (ie0_0_e_25_qs) ); - // F[e_11]: 11:11 + // F[e_26]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_11 ( + ) u_ie0_0_e_26 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_11_wd), + .wd (ie0_0_e_26_wd), // from internal hardware .de (1'b0), @@ -11580,26 +12904,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[11].q), + .q (reg2hw.ie0[26].q), .ds (), // to register interface (read) - .qs (ie0_0_e_11_qs) + .qs (ie0_0_e_26_qs) ); - // F[e_12]: 12:12 + // F[e_27]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_12 ( + ) u_ie0_0_e_27 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_12_wd), + .wd (ie0_0_e_27_wd), // from internal hardware .de (1'b0), @@ -11607,26 +12931,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[12].q), + .q (reg2hw.ie0[27].q), .ds (), // to register interface (read) - .qs (ie0_0_e_12_qs) + .qs (ie0_0_e_27_qs) ); - // F[e_13]: 13:13 + // F[e_28]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_13 ( + ) u_ie0_0_e_28 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_13_wd), + .wd (ie0_0_e_28_wd), // from internal hardware .de (1'b0), @@ -11634,26 +12958,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[13].q), + .q (reg2hw.ie0[28].q), .ds (), // to register interface (read) - .qs (ie0_0_e_13_qs) + .qs (ie0_0_e_28_qs) ); - // F[e_14]: 14:14 + // F[e_29]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_14 ( + ) u_ie0_0_e_29 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_14_wd), + .wd (ie0_0_e_29_wd), // from internal hardware .de (1'b0), @@ -11661,26 +12985,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[14].q), + .q (reg2hw.ie0[29].q), .ds (), // to register interface (read) - .qs (ie0_0_e_14_qs) + .qs (ie0_0_e_29_qs) ); - // F[e_15]: 15:15 + // F[e_30]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_15 ( + ) u_ie0_0_e_30 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_15_wd), + .wd (ie0_0_e_30_wd), // from internal hardware .de (1'b0), @@ -11688,26 +13012,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[15].q), + .q (reg2hw.ie0[30].q), .ds (), // to register interface (read) - .qs (ie0_0_e_15_qs) + .qs (ie0_0_e_30_qs) ); - // F[e_16]: 16:16 + // F[e_31]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_16 ( + ) u_ie0_0_e_31 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_0_we), - .wd (ie0_0_e_16_wd), + .wd (ie0_0_e_31_wd), // from internal hardware .de (1'b0), @@ -11715,26 +13039,29 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[16].q), + .q (reg2hw.ie0[31].q), .ds (), // to register interface (read) - .qs (ie0_0_e_16_qs) + .qs (ie0_0_e_31_qs) ); - // F[e_17]: 17:17 + + // Subregister 1 of Multireg ie0 + // R[ie0_1]: V(False) + // F[e_32]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_17 ( + ) u_ie0_1_e_32 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_17_wd), + .we (ie0_1_we), + .wd (ie0_1_e_32_wd), // from internal hardware .de (1'b0), @@ -11742,26 +13069,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[17].q), + .q (reg2hw.ie0[32].q), .ds (), // to register interface (read) - .qs (ie0_0_e_17_qs) + .qs (ie0_1_e_32_qs) ); - // F[e_18]: 18:18 + // F[e_33]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_18 ( + ) u_ie0_1_e_33 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_18_wd), + .we (ie0_1_we), + .wd (ie0_1_e_33_wd), // from internal hardware .de (1'b0), @@ -11769,26 +13096,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[18].q), + .q (reg2hw.ie0[33].q), .ds (), // to register interface (read) - .qs (ie0_0_e_18_qs) + .qs (ie0_1_e_33_qs) ); - // F[e_19]: 19:19 + // F[e_34]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_19 ( + ) u_ie0_1_e_34 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_19_wd), + .we (ie0_1_we), + .wd (ie0_1_e_34_wd), // from internal hardware .de (1'b0), @@ -11796,26 +13123,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[19].q), + .q (reg2hw.ie0[34].q), .ds (), // to register interface (read) - .qs (ie0_0_e_19_qs) + .qs (ie0_1_e_34_qs) ); - // F[e_20]: 20:20 + // F[e_35]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_20 ( + ) u_ie0_1_e_35 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_20_wd), + .we (ie0_1_we), + .wd (ie0_1_e_35_wd), // from internal hardware .de (1'b0), @@ -11823,26 +13150,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[20].q), + .q (reg2hw.ie0[35].q), .ds (), // to register interface (read) - .qs (ie0_0_e_20_qs) + .qs (ie0_1_e_35_qs) ); - // F[e_21]: 21:21 + // F[e_36]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_21 ( + ) u_ie0_1_e_36 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_21_wd), + .we (ie0_1_we), + .wd (ie0_1_e_36_wd), // from internal hardware .de (1'b0), @@ -11850,26 +13177,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[21].q), + .q (reg2hw.ie0[36].q), .ds (), // to register interface (read) - .qs (ie0_0_e_21_qs) + .qs (ie0_1_e_36_qs) ); - // F[e_22]: 22:22 + // F[e_37]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_22 ( + ) u_ie0_1_e_37 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_22_wd), + .we (ie0_1_we), + .wd (ie0_1_e_37_wd), // from internal hardware .de (1'b0), @@ -11877,26 +13204,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[22].q), + .q (reg2hw.ie0[37].q), .ds (), // to register interface (read) - .qs (ie0_0_e_22_qs) + .qs (ie0_1_e_37_qs) ); - // F[e_23]: 23:23 + // F[e_38]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_23 ( + ) u_ie0_1_e_38 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_23_wd), + .we (ie0_1_we), + .wd (ie0_1_e_38_wd), // from internal hardware .de (1'b0), @@ -11904,26 +13231,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[23].q), + .q (reg2hw.ie0[38].q), .ds (), // to register interface (read) - .qs (ie0_0_e_23_qs) + .qs (ie0_1_e_38_qs) ); - // F[e_24]: 24:24 + // F[e_39]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_24 ( + ) u_ie0_1_e_39 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_24_wd), + .we (ie0_1_we), + .wd (ie0_1_e_39_wd), // from internal hardware .de (1'b0), @@ -11931,26 +13258,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[24].q), + .q (reg2hw.ie0[39].q), .ds (), // to register interface (read) - .qs (ie0_0_e_24_qs) + .qs (ie0_1_e_39_qs) ); - // F[e_25]: 25:25 + // F[e_40]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_25 ( + ) u_ie0_1_e_40 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_25_wd), + .we (ie0_1_we), + .wd (ie0_1_e_40_wd), // from internal hardware .de (1'b0), @@ -11958,26 +13285,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[25].q), + .q (reg2hw.ie0[40].q), .ds (), // to register interface (read) - .qs (ie0_0_e_25_qs) + .qs (ie0_1_e_40_qs) ); - // F[e_26]: 26:26 + // F[e_41]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_26 ( + ) u_ie0_1_e_41 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_26_wd), + .we (ie0_1_we), + .wd (ie0_1_e_41_wd), // from internal hardware .de (1'b0), @@ -11985,26 +13312,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[26].q), + .q (reg2hw.ie0[41].q), .ds (), // to register interface (read) - .qs (ie0_0_e_26_qs) + .qs (ie0_1_e_41_qs) ); - // F[e_27]: 27:27 + // F[e_42]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_27 ( + ) u_ie0_1_e_42 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_27_wd), + .we (ie0_1_we), + .wd (ie0_1_e_42_wd), // from internal hardware .de (1'b0), @@ -12012,26 +13339,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[27].q), + .q (reg2hw.ie0[42].q), .ds (), // to register interface (read) - .qs (ie0_0_e_27_qs) + .qs (ie0_1_e_42_qs) ); - // F[e_28]: 28:28 + // F[e_43]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_28 ( + ) u_ie0_1_e_43 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_28_wd), + .we (ie0_1_we), + .wd (ie0_1_e_43_wd), // from internal hardware .de (1'b0), @@ -12039,26 +13366,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[28].q), + .q (reg2hw.ie0[43].q), .ds (), // to register interface (read) - .qs (ie0_0_e_28_qs) + .qs (ie0_1_e_43_qs) ); - // F[e_29]: 29:29 + // F[e_44]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_29 ( + ) u_ie0_1_e_44 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_29_wd), + .we (ie0_1_we), + .wd (ie0_1_e_44_wd), // from internal hardware .de (1'b0), @@ -12066,26 +13393,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[29].q), + .q (reg2hw.ie0[44].q), .ds (), // to register interface (read) - .qs (ie0_0_e_29_qs) + .qs (ie0_1_e_44_qs) ); - // F[e_30]: 30:30 + // F[e_45]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_30 ( + ) u_ie0_1_e_45 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_30_wd), + .we (ie0_1_we), + .wd (ie0_1_e_45_wd), // from internal hardware .de (1'b0), @@ -12093,26 +13420,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[30].q), + .q (reg2hw.ie0[45].q), .ds (), // to register interface (read) - .qs (ie0_0_e_30_qs) + .qs (ie0_1_e_45_qs) ); - // F[e_31]: 31:31 + // F[e_46]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_0_e_31 ( + ) u_ie0_1_e_46 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_0_we), - .wd (ie0_0_e_31_wd), + .we (ie0_1_we), + .wd (ie0_1_e_46_wd), // from internal hardware .de (1'b0), @@ -12120,29 +13447,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[31].q), + .q (reg2hw.ie0[46].q), .ds (), // to register interface (read) - .qs (ie0_0_e_31_qs) + .qs (ie0_1_e_46_qs) ); - - // Subregister 1 of Multireg ie0 - // R[ie0_1]: V(False) - // F[e_32]: 0:0 + // F[e_47]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_32 ( + ) u_ie0_1_e_47 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_32_wd), + .wd (ie0_1_e_47_wd), // from internal hardware .de (1'b0), @@ -12150,26 +13474,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[32].q), + .q (reg2hw.ie0[47].q), .ds (), // to register interface (read) - .qs (ie0_1_e_32_qs) + .qs (ie0_1_e_47_qs) ); - // F[e_33]: 1:1 + // F[e_48]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_33 ( + ) u_ie0_1_e_48 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_33_wd), + .wd (ie0_1_e_48_wd), // from internal hardware .de (1'b0), @@ -12177,26 +13501,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[33].q), + .q (reg2hw.ie0[48].q), .ds (), // to register interface (read) - .qs (ie0_1_e_33_qs) + .qs (ie0_1_e_48_qs) ); - // F[e_34]: 2:2 + // F[e_49]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_34 ( + ) u_ie0_1_e_49 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_34_wd), + .wd (ie0_1_e_49_wd), // from internal hardware .de (1'b0), @@ -12204,26 +13528,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[34].q), + .q (reg2hw.ie0[49].q), .ds (), // to register interface (read) - .qs (ie0_1_e_34_qs) + .qs (ie0_1_e_49_qs) ); - // F[e_35]: 3:3 + // F[e_50]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_35 ( + ) u_ie0_1_e_50 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_35_wd), + .wd (ie0_1_e_50_wd), // from internal hardware .de (1'b0), @@ -12231,26 +13555,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[35].q), + .q (reg2hw.ie0[50].q), .ds (), // to register interface (read) - .qs (ie0_1_e_35_qs) + .qs (ie0_1_e_50_qs) ); - // F[e_36]: 4:4 + // F[e_51]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_36 ( + ) u_ie0_1_e_51 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_36_wd), + .wd (ie0_1_e_51_wd), // from internal hardware .de (1'b0), @@ -12258,26 +13582,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[36].q), + .q (reg2hw.ie0[51].q), .ds (), // to register interface (read) - .qs (ie0_1_e_36_qs) + .qs (ie0_1_e_51_qs) ); - // F[e_37]: 5:5 + // F[e_52]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_37 ( + ) u_ie0_1_e_52 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_37_wd), + .wd (ie0_1_e_52_wd), // from internal hardware .de (1'b0), @@ -12285,26 +13609,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[37].q), + .q (reg2hw.ie0[52].q), .ds (), // to register interface (read) - .qs (ie0_1_e_37_qs) + .qs (ie0_1_e_52_qs) ); - // F[e_38]: 6:6 + // F[e_53]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_38 ( + ) u_ie0_1_e_53 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_38_wd), + .wd (ie0_1_e_53_wd), // from internal hardware .de (1'b0), @@ -12312,26 +13636,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[38].q), + .q (reg2hw.ie0[53].q), .ds (), // to register interface (read) - .qs (ie0_1_e_38_qs) + .qs (ie0_1_e_53_qs) ); - // F[e_39]: 7:7 + // F[e_54]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_39 ( + ) u_ie0_1_e_54 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_39_wd), + .wd (ie0_1_e_54_wd), // from internal hardware .de (1'b0), @@ -12339,26 +13663,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[39].q), + .q (reg2hw.ie0[54].q), .ds (), // to register interface (read) - .qs (ie0_1_e_39_qs) + .qs (ie0_1_e_54_qs) ); - // F[e_40]: 8:8 + // F[e_55]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_40 ( + ) u_ie0_1_e_55 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_40_wd), + .wd (ie0_1_e_55_wd), // from internal hardware .de (1'b0), @@ -12366,26 +13690,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[40].q), + .q (reg2hw.ie0[55].q), .ds (), // to register interface (read) - .qs (ie0_1_e_40_qs) + .qs (ie0_1_e_55_qs) ); - // F[e_41]: 9:9 + // F[e_56]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_41 ( + ) u_ie0_1_e_56 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_41_wd), + .wd (ie0_1_e_56_wd), // from internal hardware .de (1'b0), @@ -12393,26 +13717,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[41].q), + .q (reg2hw.ie0[56].q), .ds (), // to register interface (read) - .qs (ie0_1_e_41_qs) + .qs (ie0_1_e_56_qs) ); - // F[e_42]: 10:10 + // F[e_57]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_42 ( + ) u_ie0_1_e_57 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_42_wd), + .wd (ie0_1_e_57_wd), // from internal hardware .de (1'b0), @@ -12420,26 +13744,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[42].q), + .q (reg2hw.ie0[57].q), .ds (), // to register interface (read) - .qs (ie0_1_e_42_qs) + .qs (ie0_1_e_57_qs) ); - // F[e_43]: 11:11 + // F[e_58]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_43 ( + ) u_ie0_1_e_58 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_43_wd), + .wd (ie0_1_e_58_wd), // from internal hardware .de (1'b0), @@ -12447,26 +13771,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[43].q), + .q (reg2hw.ie0[58].q), .ds (), // to register interface (read) - .qs (ie0_1_e_43_qs) + .qs (ie0_1_e_58_qs) ); - // F[e_44]: 12:12 + // F[e_59]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_44 ( + ) u_ie0_1_e_59 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_44_wd), + .wd (ie0_1_e_59_wd), // from internal hardware .de (1'b0), @@ -12474,26 +13798,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[44].q), + .q (reg2hw.ie0[59].q), .ds (), // to register interface (read) - .qs (ie0_1_e_44_qs) + .qs (ie0_1_e_59_qs) ); - // F[e_45]: 13:13 + // F[e_60]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_45 ( + ) u_ie0_1_e_60 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_45_wd), + .wd (ie0_1_e_60_wd), // from internal hardware .de (1'b0), @@ -12501,26 +13825,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[45].q), + .q (reg2hw.ie0[60].q), .ds (), // to register interface (read) - .qs (ie0_1_e_45_qs) + .qs (ie0_1_e_60_qs) ); - // F[e_46]: 14:14 + // F[e_61]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_46 ( + ) u_ie0_1_e_61 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_46_wd), + .wd (ie0_1_e_61_wd), // from internal hardware .de (1'b0), @@ -12528,26 +13852,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[46].q), + .q (reg2hw.ie0[61].q), .ds (), // to register interface (read) - .qs (ie0_1_e_46_qs) + .qs (ie0_1_e_61_qs) ); - // F[e_47]: 15:15 + // F[e_62]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_47 ( + ) u_ie0_1_e_62 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_47_wd), + .wd (ie0_1_e_62_wd), // from internal hardware .de (1'b0), @@ -12555,26 +13879,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[47].q), + .q (reg2hw.ie0[62].q), .ds (), // to register interface (read) - .qs (ie0_1_e_47_qs) + .qs (ie0_1_e_62_qs) ); - // F[e_48]: 16:16 + // F[e_63]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_48 ( + ) u_ie0_1_e_63 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_1_we), - .wd (ie0_1_e_48_wd), + .wd (ie0_1_e_63_wd), // from internal hardware .de (1'b0), @@ -12582,26 +13906,29 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[48].q), + .q (reg2hw.ie0[63].q), .ds (), // to register interface (read) - .qs (ie0_1_e_48_qs) + .qs (ie0_1_e_63_qs) ); - // F[e_49]: 17:17 + + // Subregister 2 of Multireg ie0 + // R[ie0_2]: V(False) + // F[e_64]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_49 ( + ) u_ie0_2_e_64 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_49_wd), + .we (ie0_2_we), + .wd (ie0_2_e_64_wd), // from internal hardware .de (1'b0), @@ -12609,26 +13936,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[49].q), + .q (reg2hw.ie0[64].q), .ds (), // to register interface (read) - .qs (ie0_1_e_49_qs) + .qs (ie0_2_e_64_qs) ); - // F[e_50]: 18:18 + // F[e_65]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_50 ( + ) u_ie0_2_e_65 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_50_wd), + .we (ie0_2_we), + .wd (ie0_2_e_65_wd), // from internal hardware .de (1'b0), @@ -12636,26 +13963,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[50].q), + .q (reg2hw.ie0[65].q), .ds (), // to register interface (read) - .qs (ie0_1_e_50_qs) + .qs (ie0_2_e_65_qs) ); - // F[e_51]: 19:19 + // F[e_66]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_51 ( + ) u_ie0_2_e_66 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_51_wd), + .we (ie0_2_we), + .wd (ie0_2_e_66_wd), // from internal hardware .de (1'b0), @@ -12663,26 +13990,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[51].q), + .q (reg2hw.ie0[66].q), .ds (), // to register interface (read) - .qs (ie0_1_e_51_qs) + .qs (ie0_2_e_66_qs) ); - // F[e_52]: 20:20 + // F[e_67]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_52 ( + ) u_ie0_2_e_67 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_52_wd), + .we (ie0_2_we), + .wd (ie0_2_e_67_wd), // from internal hardware .de (1'b0), @@ -12690,26 +14017,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[52].q), + .q (reg2hw.ie0[67].q), .ds (), // to register interface (read) - .qs (ie0_1_e_52_qs) + .qs (ie0_2_e_67_qs) ); - // F[e_53]: 21:21 + // F[e_68]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_53 ( + ) u_ie0_2_e_68 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_53_wd), + .we (ie0_2_we), + .wd (ie0_2_e_68_wd), // from internal hardware .de (1'b0), @@ -12717,26 +14044,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[53].q), + .q (reg2hw.ie0[68].q), .ds (), // to register interface (read) - .qs (ie0_1_e_53_qs) + .qs (ie0_2_e_68_qs) ); - // F[e_54]: 22:22 + // F[e_69]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_54 ( + ) u_ie0_2_e_69 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_54_wd), + .we (ie0_2_we), + .wd (ie0_2_e_69_wd), // from internal hardware .de (1'b0), @@ -12744,26 +14071,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[54].q), + .q (reg2hw.ie0[69].q), .ds (), // to register interface (read) - .qs (ie0_1_e_54_qs) + .qs (ie0_2_e_69_qs) ); - // F[e_55]: 23:23 + // F[e_70]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_55 ( + ) u_ie0_2_e_70 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_55_wd), + .we (ie0_2_we), + .wd (ie0_2_e_70_wd), // from internal hardware .de (1'b0), @@ -12771,26 +14098,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[55].q), + .q (reg2hw.ie0[70].q), .ds (), // to register interface (read) - .qs (ie0_1_e_55_qs) + .qs (ie0_2_e_70_qs) ); - // F[e_56]: 24:24 + // F[e_71]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_56 ( + ) u_ie0_2_e_71 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_56_wd), + .we (ie0_2_we), + .wd (ie0_2_e_71_wd), // from internal hardware .de (1'b0), @@ -12798,26 +14125,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[56].q), + .q (reg2hw.ie0[71].q), .ds (), // to register interface (read) - .qs (ie0_1_e_56_qs) + .qs (ie0_2_e_71_qs) ); - // F[e_57]: 25:25 + // F[e_72]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_57 ( + ) u_ie0_2_e_72 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_57_wd), + .we (ie0_2_we), + .wd (ie0_2_e_72_wd), // from internal hardware .de (1'b0), @@ -12825,26 +14152,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[57].q), + .q (reg2hw.ie0[72].q), .ds (), // to register interface (read) - .qs (ie0_1_e_57_qs) + .qs (ie0_2_e_72_qs) ); - // F[e_58]: 26:26 + // F[e_73]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_58 ( + ) u_ie0_2_e_73 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_58_wd), + .we (ie0_2_we), + .wd (ie0_2_e_73_wd), // from internal hardware .de (1'b0), @@ -12852,26 +14179,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[58].q), + .q (reg2hw.ie0[73].q), .ds (), // to register interface (read) - .qs (ie0_1_e_58_qs) + .qs (ie0_2_e_73_qs) ); - // F[e_59]: 27:27 + // F[e_74]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_59 ( + ) u_ie0_2_e_74 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_59_wd), + .we (ie0_2_we), + .wd (ie0_2_e_74_wd), // from internal hardware .de (1'b0), @@ -12879,26 +14206,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[59].q), + .q (reg2hw.ie0[74].q), .ds (), // to register interface (read) - .qs (ie0_1_e_59_qs) + .qs (ie0_2_e_74_qs) ); - // F[e_60]: 28:28 + // F[e_75]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_60 ( + ) u_ie0_2_e_75 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_60_wd), + .we (ie0_2_we), + .wd (ie0_2_e_75_wd), // from internal hardware .de (1'b0), @@ -12906,26 +14233,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[60].q), + .q (reg2hw.ie0[75].q), .ds (), // to register interface (read) - .qs (ie0_1_e_60_qs) + .qs (ie0_2_e_75_qs) ); - // F[e_61]: 29:29 + // F[e_76]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_61 ( + ) u_ie0_2_e_76 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_61_wd), + .we (ie0_2_we), + .wd (ie0_2_e_76_wd), // from internal hardware .de (1'b0), @@ -12933,26 +14260,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[61].q), + .q (reg2hw.ie0[76].q), .ds (), // to register interface (read) - .qs (ie0_1_e_61_qs) + .qs (ie0_2_e_76_qs) ); - // F[e_62]: 30:30 + // F[e_77]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_62 ( + ) u_ie0_2_e_77 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_62_wd), + .we (ie0_2_we), + .wd (ie0_2_e_77_wd), // from internal hardware .de (1'b0), @@ -12960,26 +14287,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[62].q), + .q (reg2hw.ie0[77].q), .ds (), // to register interface (read) - .qs (ie0_1_e_62_qs) + .qs (ie0_2_e_77_qs) ); - // F[e_63]: 31:31 + // F[e_78]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_1_e_63 ( + ) u_ie0_2_e_78 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_1_we), - .wd (ie0_1_e_63_wd), + .we (ie0_2_we), + .wd (ie0_2_e_78_wd), // from internal hardware .de (1'b0), @@ -12987,29 +14314,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[63].q), + .q (reg2hw.ie0[78].q), .ds (), // to register interface (read) - .qs (ie0_1_e_63_qs) + .qs (ie0_2_e_78_qs) ); - - // Subregister 2 of Multireg ie0 - // R[ie0_2]: V(False) - // F[e_64]: 0:0 + // F[e_79]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_64 ( + ) u_ie0_2_e_79 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_64_wd), + .wd (ie0_2_e_79_wd), // from internal hardware .de (1'b0), @@ -13017,26 +14341,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[64].q), + .q (reg2hw.ie0[79].q), .ds (), // to register interface (read) - .qs (ie0_2_e_64_qs) + .qs (ie0_2_e_79_qs) ); - // F[e_65]: 1:1 + // F[e_80]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_65 ( + ) u_ie0_2_e_80 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_65_wd), + .wd (ie0_2_e_80_wd), // from internal hardware .de (1'b0), @@ -13044,26 +14368,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[65].q), + .q (reg2hw.ie0[80].q), .ds (), // to register interface (read) - .qs (ie0_2_e_65_qs) + .qs (ie0_2_e_80_qs) ); - // F[e_66]: 2:2 + // F[e_81]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_66 ( + ) u_ie0_2_e_81 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_66_wd), + .wd (ie0_2_e_81_wd), // from internal hardware .de (1'b0), @@ -13071,26 +14395,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[66].q), + .q (reg2hw.ie0[81].q), .ds (), // to register interface (read) - .qs (ie0_2_e_66_qs) + .qs (ie0_2_e_81_qs) ); - // F[e_67]: 3:3 + // F[e_82]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_67 ( + ) u_ie0_2_e_82 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_67_wd), + .wd (ie0_2_e_82_wd), // from internal hardware .de (1'b0), @@ -13098,26 +14422,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[67].q), + .q (reg2hw.ie0[82].q), .ds (), // to register interface (read) - .qs (ie0_2_e_67_qs) + .qs (ie0_2_e_82_qs) ); - // F[e_68]: 4:4 + // F[e_83]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_68 ( + ) u_ie0_2_e_83 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_68_wd), + .wd (ie0_2_e_83_wd), // from internal hardware .de (1'b0), @@ -13125,26 +14449,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[68].q), + .q (reg2hw.ie0[83].q), .ds (), // to register interface (read) - .qs (ie0_2_e_68_qs) + .qs (ie0_2_e_83_qs) ); - // F[e_69]: 5:5 + // F[e_84]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_69 ( + ) u_ie0_2_e_84 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_69_wd), + .wd (ie0_2_e_84_wd), // from internal hardware .de (1'b0), @@ -13152,26 +14476,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[69].q), + .q (reg2hw.ie0[84].q), .ds (), // to register interface (read) - .qs (ie0_2_e_69_qs) + .qs (ie0_2_e_84_qs) ); - // F[e_70]: 6:6 + // F[e_85]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_70 ( + ) u_ie0_2_e_85 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_70_wd), + .wd (ie0_2_e_85_wd), // from internal hardware .de (1'b0), @@ -13179,26 +14503,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[70].q), + .q (reg2hw.ie0[85].q), .ds (), // to register interface (read) - .qs (ie0_2_e_70_qs) + .qs (ie0_2_e_85_qs) ); - // F[e_71]: 7:7 + // F[e_86]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_71 ( + ) u_ie0_2_e_86 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_71_wd), + .wd (ie0_2_e_86_wd), // from internal hardware .de (1'b0), @@ -13206,26 +14530,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[71].q), + .q (reg2hw.ie0[86].q), .ds (), // to register interface (read) - .qs (ie0_2_e_71_qs) + .qs (ie0_2_e_86_qs) ); - // F[e_72]: 8:8 + // F[e_87]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_72 ( + ) u_ie0_2_e_87 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_72_wd), + .wd (ie0_2_e_87_wd), // from internal hardware .de (1'b0), @@ -13233,26 +14557,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[72].q), + .q (reg2hw.ie0[87].q), .ds (), // to register interface (read) - .qs (ie0_2_e_72_qs) + .qs (ie0_2_e_87_qs) ); - // F[e_73]: 9:9 + // F[e_88]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_73 ( + ) u_ie0_2_e_88 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_73_wd), + .wd (ie0_2_e_88_wd), // from internal hardware .de (1'b0), @@ -13260,26 +14584,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[73].q), + .q (reg2hw.ie0[88].q), .ds (), // to register interface (read) - .qs (ie0_2_e_73_qs) + .qs (ie0_2_e_88_qs) ); - // F[e_74]: 10:10 + // F[e_89]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_74 ( + ) u_ie0_2_e_89 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_74_wd), + .wd (ie0_2_e_89_wd), // from internal hardware .de (1'b0), @@ -13287,26 +14611,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[74].q), + .q (reg2hw.ie0[89].q), .ds (), // to register interface (read) - .qs (ie0_2_e_74_qs) + .qs (ie0_2_e_89_qs) ); - // F[e_75]: 11:11 + // F[e_90]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_75 ( + ) u_ie0_2_e_90 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_75_wd), + .wd (ie0_2_e_90_wd), // from internal hardware .de (1'b0), @@ -13314,26 +14638,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[75].q), + .q (reg2hw.ie0[90].q), .ds (), // to register interface (read) - .qs (ie0_2_e_75_qs) + .qs (ie0_2_e_90_qs) ); - // F[e_76]: 12:12 + // F[e_91]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_76 ( + ) u_ie0_2_e_91 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_76_wd), + .wd (ie0_2_e_91_wd), // from internal hardware .de (1'b0), @@ -13341,26 +14665,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[76].q), + .q (reg2hw.ie0[91].q), .ds (), // to register interface (read) - .qs (ie0_2_e_76_qs) + .qs (ie0_2_e_91_qs) ); - // F[e_77]: 13:13 + // F[e_92]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_77 ( + ) u_ie0_2_e_92 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_77_wd), + .wd (ie0_2_e_92_wd), // from internal hardware .de (1'b0), @@ -13368,26 +14692,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[77].q), + .q (reg2hw.ie0[92].q), .ds (), // to register interface (read) - .qs (ie0_2_e_77_qs) + .qs (ie0_2_e_92_qs) ); - // F[e_78]: 14:14 + // F[e_93]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_78 ( + ) u_ie0_2_e_93 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_78_wd), + .wd (ie0_2_e_93_wd), // from internal hardware .de (1'b0), @@ -13395,26 +14719,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[78].q), + .q (reg2hw.ie0[93].q), .ds (), // to register interface (read) - .qs (ie0_2_e_78_qs) + .qs (ie0_2_e_93_qs) ); - // F[e_79]: 15:15 + // F[e_94]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_79 ( + ) u_ie0_2_e_94 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_79_wd), + .wd (ie0_2_e_94_wd), // from internal hardware .de (1'b0), @@ -13422,26 +14746,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[79].q), + .q (reg2hw.ie0[94].q), .ds (), // to register interface (read) - .qs (ie0_2_e_79_qs) + .qs (ie0_2_e_94_qs) ); - // F[e_80]: 16:16 + // F[e_95]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_80 ( + ) u_ie0_2_e_95 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_2_we), - .wd (ie0_2_e_80_wd), + .wd (ie0_2_e_95_wd), // from internal hardware .de (1'b0), @@ -13449,26 +14773,29 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[80].q), + .q (reg2hw.ie0[95].q), .ds (), // to register interface (read) - .qs (ie0_2_e_80_qs) + .qs (ie0_2_e_95_qs) ); - // F[e_81]: 17:17 + + // Subregister 3 of Multireg ie0 + // R[ie0_3]: V(False) + // F[e_96]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_81 ( + ) u_ie0_3_e_96 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_81_wd), + .we (ie0_3_we), + .wd (ie0_3_e_96_wd), // from internal hardware .de (1'b0), @@ -13476,26 +14803,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[81].q), + .q (reg2hw.ie0[96].q), .ds (), // to register interface (read) - .qs (ie0_2_e_81_qs) + .qs (ie0_3_e_96_qs) ); - // F[e_82]: 18:18 + // F[e_97]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_82 ( + ) u_ie0_3_e_97 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_82_wd), + .we (ie0_3_we), + .wd (ie0_3_e_97_wd), // from internal hardware .de (1'b0), @@ -13503,26 +14830,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[82].q), + .q (reg2hw.ie0[97].q), .ds (), // to register interface (read) - .qs (ie0_2_e_82_qs) + .qs (ie0_3_e_97_qs) ); - // F[e_83]: 19:19 + // F[e_98]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_83 ( + ) u_ie0_3_e_98 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_83_wd), + .we (ie0_3_we), + .wd (ie0_3_e_98_wd), // from internal hardware .de (1'b0), @@ -13530,26 +14857,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[83].q), + .q (reg2hw.ie0[98].q), .ds (), // to register interface (read) - .qs (ie0_2_e_83_qs) + .qs (ie0_3_e_98_qs) ); - // F[e_84]: 20:20 + // F[e_99]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_84 ( + ) u_ie0_3_e_99 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_84_wd), + .we (ie0_3_we), + .wd (ie0_3_e_99_wd), // from internal hardware .de (1'b0), @@ -13557,26 +14884,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[84].q), + .q (reg2hw.ie0[99].q), .ds (), // to register interface (read) - .qs (ie0_2_e_84_qs) + .qs (ie0_3_e_99_qs) ); - // F[e_85]: 21:21 + // F[e_100]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_85 ( + ) u_ie0_3_e_100 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_85_wd), + .we (ie0_3_we), + .wd (ie0_3_e_100_wd), // from internal hardware .de (1'b0), @@ -13584,26 +14911,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[85].q), + .q (reg2hw.ie0[100].q), .ds (), // to register interface (read) - .qs (ie0_2_e_85_qs) + .qs (ie0_3_e_100_qs) ); - // F[e_86]: 22:22 + // F[e_101]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_86 ( + ) u_ie0_3_e_101 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_86_wd), + .we (ie0_3_we), + .wd (ie0_3_e_101_wd), // from internal hardware .de (1'b0), @@ -13611,26 +14938,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[86].q), + .q (reg2hw.ie0[101].q), .ds (), // to register interface (read) - .qs (ie0_2_e_86_qs) + .qs (ie0_3_e_101_qs) ); - // F[e_87]: 23:23 + // F[e_102]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_87 ( + ) u_ie0_3_e_102 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_87_wd), + .we (ie0_3_we), + .wd (ie0_3_e_102_wd), // from internal hardware .de (1'b0), @@ -13638,26 +14965,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[87].q), + .q (reg2hw.ie0[102].q), .ds (), // to register interface (read) - .qs (ie0_2_e_87_qs) + .qs (ie0_3_e_102_qs) ); - // F[e_88]: 24:24 + // F[e_103]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_88 ( + ) u_ie0_3_e_103 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_88_wd), + .we (ie0_3_we), + .wd (ie0_3_e_103_wd), // from internal hardware .de (1'b0), @@ -13665,26 +14992,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[88].q), + .q (reg2hw.ie0[103].q), .ds (), // to register interface (read) - .qs (ie0_2_e_88_qs) + .qs (ie0_3_e_103_qs) ); - // F[e_89]: 25:25 + // F[e_104]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_89 ( + ) u_ie0_3_e_104 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_89_wd), + .we (ie0_3_we), + .wd (ie0_3_e_104_wd), // from internal hardware .de (1'b0), @@ -13692,26 +15019,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[89].q), + .q (reg2hw.ie0[104].q), .ds (), // to register interface (read) - .qs (ie0_2_e_89_qs) + .qs (ie0_3_e_104_qs) ); - // F[e_90]: 26:26 + // F[e_105]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_90 ( + ) u_ie0_3_e_105 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_90_wd), + .we (ie0_3_we), + .wd (ie0_3_e_105_wd), // from internal hardware .de (1'b0), @@ -13719,26 +15046,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[90].q), + .q (reg2hw.ie0[105].q), .ds (), // to register interface (read) - .qs (ie0_2_e_90_qs) + .qs (ie0_3_e_105_qs) ); - // F[e_91]: 27:27 + // F[e_106]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_91 ( + ) u_ie0_3_e_106 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_91_wd), + .we (ie0_3_we), + .wd (ie0_3_e_106_wd), // from internal hardware .de (1'b0), @@ -13746,26 +15073,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[91].q), + .q (reg2hw.ie0[106].q), .ds (), // to register interface (read) - .qs (ie0_2_e_91_qs) + .qs (ie0_3_e_106_qs) ); - // F[e_92]: 28:28 + // F[e_107]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_92 ( + ) u_ie0_3_e_107 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_92_wd), + .we (ie0_3_we), + .wd (ie0_3_e_107_wd), // from internal hardware .de (1'b0), @@ -13773,26 +15100,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[92].q), + .q (reg2hw.ie0[107].q), .ds (), // to register interface (read) - .qs (ie0_2_e_92_qs) + .qs (ie0_3_e_107_qs) ); - // F[e_93]: 29:29 + // F[e_108]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_93 ( + ) u_ie0_3_e_108 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_93_wd), + .we (ie0_3_we), + .wd (ie0_3_e_108_wd), // from internal hardware .de (1'b0), @@ -13800,26 +15127,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[93].q), + .q (reg2hw.ie0[108].q), .ds (), // to register interface (read) - .qs (ie0_2_e_93_qs) + .qs (ie0_3_e_108_qs) ); - // F[e_94]: 30:30 + // F[e_109]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_94 ( + ) u_ie0_3_e_109 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_94_wd), + .we (ie0_3_we), + .wd (ie0_3_e_109_wd), // from internal hardware .de (1'b0), @@ -13827,26 +15154,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[94].q), + .q (reg2hw.ie0[109].q), .ds (), // to register interface (read) - .qs (ie0_2_e_94_qs) + .qs (ie0_3_e_109_qs) ); - // F[e_95]: 31:31 + // F[e_110]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_2_e_95 ( + ) u_ie0_3_e_110 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_2_we), - .wd (ie0_2_e_95_wd), + .we (ie0_3_we), + .wd (ie0_3_e_110_wd), // from internal hardware .de (1'b0), @@ -13854,29 +15181,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[95].q), + .q (reg2hw.ie0[110].q), .ds (), // to register interface (read) - .qs (ie0_2_e_95_qs) + .qs (ie0_3_e_110_qs) ); - - // Subregister 3 of Multireg ie0 - // R[ie0_3]: V(False) - // F[e_96]: 0:0 + // F[e_111]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_96 ( + ) u_ie0_3_e_111 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_96_wd), + .wd (ie0_3_e_111_wd), // from internal hardware .de (1'b0), @@ -13884,26 +15208,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[96].q), + .q (reg2hw.ie0[111].q), .ds (), // to register interface (read) - .qs (ie0_3_e_96_qs) + .qs (ie0_3_e_111_qs) ); - // F[e_97]: 1:1 + // F[e_112]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_97 ( + ) u_ie0_3_e_112 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_97_wd), + .wd (ie0_3_e_112_wd), // from internal hardware .de (1'b0), @@ -13911,26 +15235,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[97].q), + .q (reg2hw.ie0[112].q), .ds (), // to register interface (read) - .qs (ie0_3_e_97_qs) + .qs (ie0_3_e_112_qs) ); - // F[e_98]: 2:2 + // F[e_113]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_98 ( + ) u_ie0_3_e_113 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_98_wd), + .wd (ie0_3_e_113_wd), // from internal hardware .de (1'b0), @@ -13938,26 +15262,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[98].q), + .q (reg2hw.ie0[113].q), .ds (), // to register interface (read) - .qs (ie0_3_e_98_qs) + .qs (ie0_3_e_113_qs) ); - // F[e_99]: 3:3 + // F[e_114]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_99 ( + ) u_ie0_3_e_114 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_99_wd), + .wd (ie0_3_e_114_wd), // from internal hardware .de (1'b0), @@ -13965,26 +15289,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[99].q), + .q (reg2hw.ie0[114].q), .ds (), // to register interface (read) - .qs (ie0_3_e_99_qs) + .qs (ie0_3_e_114_qs) ); - // F[e_100]: 4:4 + // F[e_115]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_100 ( + ) u_ie0_3_e_115 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_100_wd), + .wd (ie0_3_e_115_wd), // from internal hardware .de (1'b0), @@ -13992,26 +15316,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[100].q), + .q (reg2hw.ie0[115].q), .ds (), // to register interface (read) - .qs (ie0_3_e_100_qs) + .qs (ie0_3_e_115_qs) ); - // F[e_101]: 5:5 + // F[e_116]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_101 ( + ) u_ie0_3_e_116 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_101_wd), + .wd (ie0_3_e_116_wd), // from internal hardware .de (1'b0), @@ -14019,26 +15343,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[101].q), + .q (reg2hw.ie0[116].q), .ds (), // to register interface (read) - .qs (ie0_3_e_101_qs) + .qs (ie0_3_e_116_qs) ); - // F[e_102]: 6:6 + // F[e_117]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_102 ( + ) u_ie0_3_e_117 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_102_wd), + .wd (ie0_3_e_117_wd), // from internal hardware .de (1'b0), @@ -14046,26 +15370,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[102].q), + .q (reg2hw.ie0[117].q), .ds (), // to register interface (read) - .qs (ie0_3_e_102_qs) + .qs (ie0_3_e_117_qs) ); - // F[e_103]: 7:7 + // F[e_118]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_103 ( + ) u_ie0_3_e_118 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_103_wd), + .wd (ie0_3_e_118_wd), // from internal hardware .de (1'b0), @@ -14073,26 +15397,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[103].q), + .q (reg2hw.ie0[118].q), .ds (), // to register interface (read) - .qs (ie0_3_e_103_qs) + .qs (ie0_3_e_118_qs) ); - // F[e_104]: 8:8 + // F[e_119]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_104 ( + ) u_ie0_3_e_119 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_104_wd), + .wd (ie0_3_e_119_wd), // from internal hardware .de (1'b0), @@ -14100,26 +15424,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[104].q), + .q (reg2hw.ie0[119].q), .ds (), // to register interface (read) - .qs (ie0_3_e_104_qs) + .qs (ie0_3_e_119_qs) ); - // F[e_105]: 9:9 + // F[e_120]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_105 ( + ) u_ie0_3_e_120 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_105_wd), + .wd (ie0_3_e_120_wd), // from internal hardware .de (1'b0), @@ -14127,26 +15451,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[105].q), + .q (reg2hw.ie0[120].q), .ds (), // to register interface (read) - .qs (ie0_3_e_105_qs) + .qs (ie0_3_e_120_qs) ); - // F[e_106]: 10:10 + // F[e_121]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_106 ( + ) u_ie0_3_e_121 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_106_wd), + .wd (ie0_3_e_121_wd), // from internal hardware .de (1'b0), @@ -14154,26 +15478,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[106].q), + .q (reg2hw.ie0[121].q), .ds (), // to register interface (read) - .qs (ie0_3_e_106_qs) + .qs (ie0_3_e_121_qs) ); - // F[e_107]: 11:11 + // F[e_122]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_107 ( + ) u_ie0_3_e_122 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_107_wd), + .wd (ie0_3_e_122_wd), // from internal hardware .de (1'b0), @@ -14181,26 +15505,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[107].q), + .q (reg2hw.ie0[122].q), .ds (), // to register interface (read) - .qs (ie0_3_e_107_qs) + .qs (ie0_3_e_122_qs) ); - // F[e_108]: 12:12 + // F[e_123]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_108 ( + ) u_ie0_3_e_123 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_108_wd), + .wd (ie0_3_e_123_wd), // from internal hardware .de (1'b0), @@ -14208,26 +15532,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[108].q), + .q (reg2hw.ie0[123].q), .ds (), // to register interface (read) - .qs (ie0_3_e_108_qs) + .qs (ie0_3_e_123_qs) ); - // F[e_109]: 13:13 + // F[e_124]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_109 ( + ) u_ie0_3_e_124 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_109_wd), + .wd (ie0_3_e_124_wd), // from internal hardware .de (1'b0), @@ -14235,26 +15559,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[109].q), + .q (reg2hw.ie0[124].q), .ds (), // to register interface (read) - .qs (ie0_3_e_109_qs) + .qs (ie0_3_e_124_qs) ); - // F[e_110]: 14:14 + // F[e_125]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_110 ( + ) u_ie0_3_e_125 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_110_wd), + .wd (ie0_3_e_125_wd), // from internal hardware .de (1'b0), @@ -14262,26 +15586,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[110].q), + .q (reg2hw.ie0[125].q), .ds (), // to register interface (read) - .qs (ie0_3_e_110_qs) + .qs (ie0_3_e_125_qs) ); - // F[e_111]: 15:15 + // F[e_126]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_111 ( + ) u_ie0_3_e_126 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_111_wd), + .wd (ie0_3_e_126_wd), // from internal hardware .de (1'b0), @@ -14289,26 +15613,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[111].q), + .q (reg2hw.ie0[126].q), .ds (), // to register interface (read) - .qs (ie0_3_e_111_qs) + .qs (ie0_3_e_126_qs) ); - // F[e_112]: 16:16 + // F[e_127]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_112 ( + ) u_ie0_3_e_127 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_3_we), - .wd (ie0_3_e_112_wd), + .wd (ie0_3_e_127_wd), // from internal hardware .de (1'b0), @@ -14316,26 +15640,29 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[112].q), + .q (reg2hw.ie0[127].q), .ds (), // to register interface (read) - .qs (ie0_3_e_112_qs) + .qs (ie0_3_e_127_qs) ); - // F[e_113]: 17:17 + + // Subregister 4 of Multireg ie0 + // R[ie0_4]: V(False) + // F[e_128]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_113 ( + ) u_ie0_4_e_128 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_113_wd), + .we (ie0_4_we), + .wd (ie0_4_e_128_wd), // from internal hardware .de (1'b0), @@ -14343,26 +15670,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[113].q), + .q (reg2hw.ie0[128].q), .ds (), // to register interface (read) - .qs (ie0_3_e_113_qs) + .qs (ie0_4_e_128_qs) ); - // F[e_114]: 18:18 + // F[e_129]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_114 ( + ) u_ie0_4_e_129 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_114_wd), + .we (ie0_4_we), + .wd (ie0_4_e_129_wd), // from internal hardware .de (1'b0), @@ -14370,26 +15697,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[114].q), + .q (reg2hw.ie0[129].q), .ds (), // to register interface (read) - .qs (ie0_3_e_114_qs) + .qs (ie0_4_e_129_qs) ); - // F[e_115]: 19:19 + // F[e_130]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_115 ( + ) u_ie0_4_e_130 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_115_wd), + .we (ie0_4_we), + .wd (ie0_4_e_130_wd), // from internal hardware .de (1'b0), @@ -14397,26 +15724,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[115].q), + .q (reg2hw.ie0[130].q), .ds (), // to register interface (read) - .qs (ie0_3_e_115_qs) + .qs (ie0_4_e_130_qs) ); - // F[e_116]: 20:20 + // F[e_131]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_116 ( + ) u_ie0_4_e_131 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_116_wd), + .we (ie0_4_we), + .wd (ie0_4_e_131_wd), // from internal hardware .de (1'b0), @@ -14424,26 +15751,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[116].q), + .q (reg2hw.ie0[131].q), .ds (), // to register interface (read) - .qs (ie0_3_e_116_qs) + .qs (ie0_4_e_131_qs) ); - // F[e_117]: 21:21 + // F[e_132]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_117 ( + ) u_ie0_4_e_132 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_117_wd), + .we (ie0_4_we), + .wd (ie0_4_e_132_wd), // from internal hardware .de (1'b0), @@ -14451,26 +15778,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[117].q), + .q (reg2hw.ie0[132].q), .ds (), // to register interface (read) - .qs (ie0_3_e_117_qs) + .qs (ie0_4_e_132_qs) ); - // F[e_118]: 22:22 + // F[e_133]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_118 ( + ) u_ie0_4_e_133 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_118_wd), + .we (ie0_4_we), + .wd (ie0_4_e_133_wd), // from internal hardware .de (1'b0), @@ -14478,26 +15805,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[118].q), + .q (reg2hw.ie0[133].q), .ds (), // to register interface (read) - .qs (ie0_3_e_118_qs) + .qs (ie0_4_e_133_qs) ); - // F[e_119]: 23:23 + // F[e_134]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_119 ( + ) u_ie0_4_e_134 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_119_wd), + .we (ie0_4_we), + .wd (ie0_4_e_134_wd), // from internal hardware .de (1'b0), @@ -14505,26 +15832,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[119].q), + .q (reg2hw.ie0[134].q), .ds (), // to register interface (read) - .qs (ie0_3_e_119_qs) + .qs (ie0_4_e_134_qs) ); - // F[e_120]: 24:24 + // F[e_135]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_120 ( + ) u_ie0_4_e_135 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_120_wd), + .we (ie0_4_we), + .wd (ie0_4_e_135_wd), // from internal hardware .de (1'b0), @@ -14532,26 +15859,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[120].q), + .q (reg2hw.ie0[135].q), .ds (), // to register interface (read) - .qs (ie0_3_e_120_qs) + .qs (ie0_4_e_135_qs) ); - // F[e_121]: 25:25 + // F[e_136]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_121 ( + ) u_ie0_4_e_136 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_121_wd), + .we (ie0_4_we), + .wd (ie0_4_e_136_wd), // from internal hardware .de (1'b0), @@ -14559,26 +15886,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[121].q), + .q (reg2hw.ie0[136].q), .ds (), // to register interface (read) - .qs (ie0_3_e_121_qs) + .qs (ie0_4_e_136_qs) ); - // F[e_122]: 26:26 + // F[e_137]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_122 ( + ) u_ie0_4_e_137 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_122_wd), + .we (ie0_4_we), + .wd (ie0_4_e_137_wd), // from internal hardware .de (1'b0), @@ -14586,26 +15913,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[122].q), + .q (reg2hw.ie0[137].q), .ds (), // to register interface (read) - .qs (ie0_3_e_122_qs) + .qs (ie0_4_e_137_qs) ); - // F[e_123]: 27:27 + // F[e_138]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_123 ( + ) u_ie0_4_e_138 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_123_wd), + .we (ie0_4_we), + .wd (ie0_4_e_138_wd), // from internal hardware .de (1'b0), @@ -14613,26 +15940,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[123].q), + .q (reg2hw.ie0[138].q), .ds (), // to register interface (read) - .qs (ie0_3_e_123_qs) + .qs (ie0_4_e_138_qs) ); - // F[e_124]: 28:28 + // F[e_139]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_124 ( + ) u_ie0_4_e_139 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_124_wd), + .we (ie0_4_we), + .wd (ie0_4_e_139_wd), // from internal hardware .de (1'b0), @@ -14640,26 +15967,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[124].q), + .q (reg2hw.ie0[139].q), .ds (), // to register interface (read) - .qs (ie0_3_e_124_qs) + .qs (ie0_4_e_139_qs) ); - // F[e_125]: 29:29 + // F[e_140]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_125 ( + ) u_ie0_4_e_140 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_125_wd), + .we (ie0_4_we), + .wd (ie0_4_e_140_wd), // from internal hardware .de (1'b0), @@ -14667,26 +15994,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[125].q), + .q (reg2hw.ie0[140].q), .ds (), // to register interface (read) - .qs (ie0_3_e_125_qs) + .qs (ie0_4_e_140_qs) ); - // F[e_126]: 30:30 + // F[e_141]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_126 ( + ) u_ie0_4_e_141 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_126_wd), + .we (ie0_4_we), + .wd (ie0_4_e_141_wd), // from internal hardware .de (1'b0), @@ -14694,26 +16021,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[126].q), + .q (reg2hw.ie0[141].q), .ds (), // to register interface (read) - .qs (ie0_3_e_126_qs) + .qs (ie0_4_e_141_qs) ); - // F[e_127]: 31:31 + // F[e_142]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_3_e_127 ( + ) u_ie0_4_e_142 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_3_we), - .wd (ie0_3_e_127_wd), + .we (ie0_4_we), + .wd (ie0_4_e_142_wd), // from internal hardware .de (1'b0), @@ -14721,29 +16048,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[127].q), + .q (reg2hw.ie0[142].q), .ds (), // to register interface (read) - .qs (ie0_3_e_127_qs) + .qs (ie0_4_e_142_qs) ); - - // Subregister 4 of Multireg ie0 - // R[ie0_4]: V(False) - // F[e_128]: 0:0 + // F[e_143]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_128 ( + ) u_ie0_4_e_143 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_128_wd), + .wd (ie0_4_e_143_wd), // from internal hardware .de (1'b0), @@ -14751,26 +16075,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[128].q), + .q (reg2hw.ie0[143].q), .ds (), // to register interface (read) - .qs (ie0_4_e_128_qs) + .qs (ie0_4_e_143_qs) ); - // F[e_129]: 1:1 + // F[e_144]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_129 ( + ) u_ie0_4_e_144 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_129_wd), + .wd (ie0_4_e_144_wd), // from internal hardware .de (1'b0), @@ -14778,26 +16102,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[129].q), + .q (reg2hw.ie0[144].q), .ds (), // to register interface (read) - .qs (ie0_4_e_129_qs) + .qs (ie0_4_e_144_qs) ); - // F[e_130]: 2:2 + // F[e_145]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_130 ( + ) u_ie0_4_e_145 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_130_wd), + .wd (ie0_4_e_145_wd), // from internal hardware .de (1'b0), @@ -14805,26 +16129,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[130].q), + .q (reg2hw.ie0[145].q), .ds (), // to register interface (read) - .qs (ie0_4_e_130_qs) + .qs (ie0_4_e_145_qs) ); - // F[e_131]: 3:3 + // F[e_146]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_131 ( + ) u_ie0_4_e_146 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_131_wd), + .wd (ie0_4_e_146_wd), // from internal hardware .de (1'b0), @@ -14832,26 +16156,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[131].q), + .q (reg2hw.ie0[146].q), .ds (), // to register interface (read) - .qs (ie0_4_e_131_qs) + .qs (ie0_4_e_146_qs) ); - // F[e_132]: 4:4 + // F[e_147]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_132 ( + ) u_ie0_4_e_147 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_132_wd), + .wd (ie0_4_e_147_wd), // from internal hardware .de (1'b0), @@ -14859,26 +16183,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[132].q), + .q (reg2hw.ie0[147].q), .ds (), // to register interface (read) - .qs (ie0_4_e_132_qs) + .qs (ie0_4_e_147_qs) ); - // F[e_133]: 5:5 + // F[e_148]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_133 ( + ) u_ie0_4_e_148 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_133_wd), + .wd (ie0_4_e_148_wd), // from internal hardware .de (1'b0), @@ -14886,26 +16210,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[133].q), + .q (reg2hw.ie0[148].q), .ds (), // to register interface (read) - .qs (ie0_4_e_133_qs) + .qs (ie0_4_e_148_qs) ); - // F[e_134]: 6:6 + // F[e_149]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_134 ( + ) u_ie0_4_e_149 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_134_wd), + .wd (ie0_4_e_149_wd), // from internal hardware .de (1'b0), @@ -14913,26 +16237,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[134].q), + .q (reg2hw.ie0[149].q), .ds (), // to register interface (read) - .qs (ie0_4_e_134_qs) + .qs (ie0_4_e_149_qs) ); - // F[e_135]: 7:7 + // F[e_150]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_135 ( + ) u_ie0_4_e_150 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_135_wd), + .wd (ie0_4_e_150_wd), // from internal hardware .de (1'b0), @@ -14940,26 +16264,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[135].q), + .q (reg2hw.ie0[150].q), .ds (), // to register interface (read) - .qs (ie0_4_e_135_qs) + .qs (ie0_4_e_150_qs) ); - // F[e_136]: 8:8 + // F[e_151]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_136 ( + ) u_ie0_4_e_151 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_136_wd), + .wd (ie0_4_e_151_wd), // from internal hardware .de (1'b0), @@ -14967,26 +16291,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[136].q), + .q (reg2hw.ie0[151].q), .ds (), // to register interface (read) - .qs (ie0_4_e_136_qs) + .qs (ie0_4_e_151_qs) ); - // F[e_137]: 9:9 + // F[e_152]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_137 ( + ) u_ie0_4_e_152 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_137_wd), + .wd (ie0_4_e_152_wd), // from internal hardware .de (1'b0), @@ -14994,26 +16318,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[137].q), + .q (reg2hw.ie0[152].q), .ds (), // to register interface (read) - .qs (ie0_4_e_137_qs) + .qs (ie0_4_e_152_qs) ); - // F[e_138]: 10:10 + // F[e_153]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_138 ( + ) u_ie0_4_e_153 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_138_wd), + .wd (ie0_4_e_153_wd), // from internal hardware .de (1'b0), @@ -15021,26 +16345,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[138].q), + .q (reg2hw.ie0[153].q), .ds (), // to register interface (read) - .qs (ie0_4_e_138_qs) + .qs (ie0_4_e_153_qs) ); - // F[e_139]: 11:11 + // F[e_154]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_139 ( + ) u_ie0_4_e_154 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_139_wd), + .wd (ie0_4_e_154_wd), // from internal hardware .de (1'b0), @@ -15048,26 +16372,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[139].q), + .q (reg2hw.ie0[154].q), .ds (), // to register interface (read) - .qs (ie0_4_e_139_qs) + .qs (ie0_4_e_154_qs) ); - // F[e_140]: 12:12 + // F[e_155]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_140 ( + ) u_ie0_4_e_155 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_140_wd), + .wd (ie0_4_e_155_wd), // from internal hardware .de (1'b0), @@ -15075,26 +16399,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[140].q), + .q (reg2hw.ie0[155].q), .ds (), // to register interface (read) - .qs (ie0_4_e_140_qs) + .qs (ie0_4_e_155_qs) ); - // F[e_141]: 13:13 + // F[e_156]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_141 ( + ) u_ie0_4_e_156 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_141_wd), + .wd (ie0_4_e_156_wd), // from internal hardware .de (1'b0), @@ -15102,26 +16426,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[141].q), + .q (reg2hw.ie0[156].q), .ds (), // to register interface (read) - .qs (ie0_4_e_141_qs) + .qs (ie0_4_e_156_qs) ); - // F[e_142]: 14:14 + // F[e_157]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_142 ( + ) u_ie0_4_e_157 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_142_wd), + .wd (ie0_4_e_157_wd), // from internal hardware .de (1'b0), @@ -15129,26 +16453,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[142].q), + .q (reg2hw.ie0[157].q), .ds (), // to register interface (read) - .qs (ie0_4_e_142_qs) + .qs (ie0_4_e_157_qs) ); - // F[e_143]: 15:15 + // F[e_158]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_143 ( + ) u_ie0_4_e_158 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_143_wd), + .wd (ie0_4_e_158_wd), // from internal hardware .de (1'b0), @@ -15156,26 +16480,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[143].q), + .q (reg2hw.ie0[158].q), .ds (), // to register interface (read) - .qs (ie0_4_e_143_qs) + .qs (ie0_4_e_158_qs) ); - // F[e_144]: 16:16 + // F[e_159]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_144 ( + ) u_ie0_4_e_159 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_4_we), - .wd (ie0_4_e_144_wd), + .wd (ie0_4_e_159_wd), // from internal hardware .de (1'b0), @@ -15183,26 +16507,29 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[144].q), + .q (reg2hw.ie0[159].q), .ds (), // to register interface (read) - .qs (ie0_4_e_144_qs) + .qs (ie0_4_e_159_qs) ); - // F[e_145]: 17:17 + + // Subregister 5 of Multireg ie0 + // R[ie0_5]: V(False) + // F[e_160]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_145 ( + ) u_ie0_5_e_160 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_145_wd), + .we (ie0_5_we), + .wd (ie0_5_e_160_wd), // from internal hardware .de (1'b0), @@ -15210,26 +16537,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[145].q), + .q (reg2hw.ie0[160].q), .ds (), // to register interface (read) - .qs (ie0_4_e_145_qs) + .qs (ie0_5_e_160_qs) ); - // F[e_146]: 18:18 + // F[e_161]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_146 ( + ) u_ie0_5_e_161 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_146_wd), + .we (ie0_5_we), + .wd (ie0_5_e_161_wd), // from internal hardware .de (1'b0), @@ -15237,26 +16564,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[146].q), + .q (reg2hw.ie0[161].q), .ds (), // to register interface (read) - .qs (ie0_4_e_146_qs) + .qs (ie0_5_e_161_qs) ); - // F[e_147]: 19:19 + // F[e_162]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_147 ( + ) u_ie0_5_e_162 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_147_wd), + .we (ie0_5_we), + .wd (ie0_5_e_162_wd), // from internal hardware .de (1'b0), @@ -15264,26 +16591,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[147].q), + .q (reg2hw.ie0[162].q), .ds (), // to register interface (read) - .qs (ie0_4_e_147_qs) + .qs (ie0_5_e_162_qs) ); - // F[e_148]: 20:20 + // F[e_163]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_148 ( + ) u_ie0_5_e_163 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_148_wd), + .we (ie0_5_we), + .wd (ie0_5_e_163_wd), // from internal hardware .de (1'b0), @@ -15291,26 +16618,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[148].q), + .q (reg2hw.ie0[163].q), .ds (), // to register interface (read) - .qs (ie0_4_e_148_qs) + .qs (ie0_5_e_163_qs) ); - // F[e_149]: 21:21 + // F[e_164]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_149 ( + ) u_ie0_5_e_164 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_149_wd), + .we (ie0_5_we), + .wd (ie0_5_e_164_wd), // from internal hardware .de (1'b0), @@ -15318,26 +16645,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[149].q), + .q (reg2hw.ie0[164].q), .ds (), // to register interface (read) - .qs (ie0_4_e_149_qs) + .qs (ie0_5_e_164_qs) ); - // F[e_150]: 22:22 + // F[e_165]: 5:5 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_150 ( + ) u_ie0_5_e_165 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_150_wd), + .we (ie0_5_we), + .wd (ie0_5_e_165_wd), // from internal hardware .de (1'b0), @@ -15345,26 +16672,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[150].q), + .q (reg2hw.ie0[165].q), .ds (), // to register interface (read) - .qs (ie0_4_e_150_qs) + .qs (ie0_5_e_165_qs) ); - // F[e_151]: 23:23 + // F[e_166]: 6:6 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_151 ( + ) u_ie0_5_e_166 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_151_wd), + .we (ie0_5_we), + .wd (ie0_5_e_166_wd), // from internal hardware .de (1'b0), @@ -15372,26 +16699,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[151].q), + .q (reg2hw.ie0[166].q), .ds (), // to register interface (read) - .qs (ie0_4_e_151_qs) + .qs (ie0_5_e_166_qs) ); - // F[e_152]: 24:24 + // F[e_167]: 7:7 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_152 ( + ) u_ie0_5_e_167 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_152_wd), + .we (ie0_5_we), + .wd (ie0_5_e_167_wd), // from internal hardware .de (1'b0), @@ -15399,26 +16726,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[152].q), + .q (reg2hw.ie0[167].q), .ds (), // to register interface (read) - .qs (ie0_4_e_152_qs) + .qs (ie0_5_e_167_qs) ); - // F[e_153]: 25:25 + // F[e_168]: 8:8 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_153 ( + ) u_ie0_5_e_168 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_153_wd), + .we (ie0_5_we), + .wd (ie0_5_e_168_wd), // from internal hardware .de (1'b0), @@ -15426,26 +16753,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[153].q), + .q (reg2hw.ie0[168].q), .ds (), // to register interface (read) - .qs (ie0_4_e_153_qs) + .qs (ie0_5_e_168_qs) ); - // F[e_154]: 26:26 + // F[e_169]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_154 ( + ) u_ie0_5_e_169 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_154_wd), + .we (ie0_5_we), + .wd (ie0_5_e_169_wd), // from internal hardware .de (1'b0), @@ -15453,26 +16780,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[154].q), + .q (reg2hw.ie0[169].q), .ds (), // to register interface (read) - .qs (ie0_4_e_154_qs) + .qs (ie0_5_e_169_qs) ); - // F[e_155]: 27:27 + // F[e_170]: 10:10 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_155 ( + ) u_ie0_5_e_170 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_155_wd), + .we (ie0_5_we), + .wd (ie0_5_e_170_wd), // from internal hardware .de (1'b0), @@ -15480,26 +16807,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[155].q), + .q (reg2hw.ie0[170].q), .ds (), // to register interface (read) - .qs (ie0_4_e_155_qs) + .qs (ie0_5_e_170_qs) ); - // F[e_156]: 28:28 + // F[e_171]: 11:11 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_156 ( + ) u_ie0_5_e_171 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_156_wd), + .we (ie0_5_we), + .wd (ie0_5_e_171_wd), // from internal hardware .de (1'b0), @@ -15507,26 +16834,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[156].q), + .q (reg2hw.ie0[171].q), .ds (), // to register interface (read) - .qs (ie0_4_e_156_qs) + .qs (ie0_5_e_171_qs) ); - // F[e_157]: 29:29 + // F[e_172]: 12:12 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_157 ( + ) u_ie0_5_e_172 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_157_wd), + .we (ie0_5_we), + .wd (ie0_5_e_172_wd), // from internal hardware .de (1'b0), @@ -15534,26 +16861,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[157].q), + .q (reg2hw.ie0[172].q), .ds (), // to register interface (read) - .qs (ie0_4_e_157_qs) + .qs (ie0_5_e_172_qs) ); - // F[e_158]: 30:30 + // F[e_173]: 13:13 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_158 ( + ) u_ie0_5_e_173 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_158_wd), + .we (ie0_5_we), + .wd (ie0_5_e_173_wd), // from internal hardware .de (1'b0), @@ -15561,26 +16888,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[158].q), + .q (reg2hw.ie0[173].q), .ds (), // to register interface (read) - .qs (ie0_4_e_158_qs) + .qs (ie0_5_e_173_qs) ); - // F[e_159]: 31:31 + // F[e_174]: 14:14 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_4_e_159 ( + ) u_ie0_5_e_174 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_4_we), - .wd (ie0_4_e_159_wd), + .we (ie0_5_we), + .wd (ie0_5_e_174_wd), // from internal hardware .de (1'b0), @@ -15588,29 +16915,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[159].q), + .q (reg2hw.ie0[174].q), .ds (), // to register interface (read) - .qs (ie0_4_e_159_qs) + .qs (ie0_5_e_174_qs) ); - - // Subregister 5 of Multireg ie0 - // R[ie0_5]: V(False) - // F[e_160]: 0:0 + // F[e_175]: 15:15 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_160 ( + ) u_ie0_5_e_175 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_160_wd), + .wd (ie0_5_e_175_wd), // from internal hardware .de (1'b0), @@ -15618,26 +16942,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[160].q), + .q (reg2hw.ie0[175].q), .ds (), // to register interface (read) - .qs (ie0_5_e_160_qs) + .qs (ie0_5_e_175_qs) ); - // F[e_161]: 1:1 + // F[e_176]: 16:16 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_161 ( + ) u_ie0_5_e_176 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_161_wd), + .wd (ie0_5_e_176_wd), // from internal hardware .de (1'b0), @@ -15645,26 +16969,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[161].q), + .q (reg2hw.ie0[176].q), .ds (), // to register interface (read) - .qs (ie0_5_e_161_qs) + .qs (ie0_5_e_176_qs) ); - // F[e_162]: 2:2 + // F[e_177]: 17:17 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_162 ( + ) u_ie0_5_e_177 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_162_wd), + .wd (ie0_5_e_177_wd), // from internal hardware .de (1'b0), @@ -15672,26 +16996,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[162].q), + .q (reg2hw.ie0[177].q), .ds (), // to register interface (read) - .qs (ie0_5_e_162_qs) + .qs (ie0_5_e_177_qs) ); - // F[e_163]: 3:3 + // F[e_178]: 18:18 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_163 ( + ) u_ie0_5_e_178 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_163_wd), + .wd (ie0_5_e_178_wd), // from internal hardware .de (1'b0), @@ -15699,26 +17023,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[163].q), + .q (reg2hw.ie0[178].q), .ds (), // to register interface (read) - .qs (ie0_5_e_163_qs) + .qs (ie0_5_e_178_qs) ); - // F[e_164]: 4:4 + // F[e_179]: 19:19 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_164 ( + ) u_ie0_5_e_179 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_164_wd), + .wd (ie0_5_e_179_wd), // from internal hardware .de (1'b0), @@ -15726,26 +17050,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[164].q), + .q (reg2hw.ie0[179].q), .ds (), // to register interface (read) - .qs (ie0_5_e_164_qs) + .qs (ie0_5_e_179_qs) ); - // F[e_165]: 5:5 + // F[e_180]: 20:20 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_165 ( + ) u_ie0_5_e_180 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_165_wd), + .wd (ie0_5_e_180_wd), // from internal hardware .de (1'b0), @@ -15753,26 +17077,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[165].q), + .q (reg2hw.ie0[180].q), .ds (), // to register interface (read) - .qs (ie0_5_e_165_qs) + .qs (ie0_5_e_180_qs) ); - // F[e_166]: 6:6 + // F[e_181]: 21:21 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_166 ( + ) u_ie0_5_e_181 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_166_wd), + .wd (ie0_5_e_181_wd), // from internal hardware .de (1'b0), @@ -15780,26 +17104,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[166].q), + .q (reg2hw.ie0[181].q), .ds (), // to register interface (read) - .qs (ie0_5_e_166_qs) + .qs (ie0_5_e_181_qs) ); - // F[e_167]: 7:7 + // F[e_182]: 22:22 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_167 ( + ) u_ie0_5_e_182 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_167_wd), + .wd (ie0_5_e_182_wd), // from internal hardware .de (1'b0), @@ -15807,26 +17131,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[167].q), + .q (reg2hw.ie0[182].q), .ds (), // to register interface (read) - .qs (ie0_5_e_167_qs) + .qs (ie0_5_e_182_qs) ); - // F[e_168]: 8:8 + // F[e_183]: 23:23 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_168 ( + ) u_ie0_5_e_183 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_168_wd), + .wd (ie0_5_e_183_wd), // from internal hardware .de (1'b0), @@ -15834,26 +17158,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[168].q), + .q (reg2hw.ie0[183].q), .ds (), // to register interface (read) - .qs (ie0_5_e_168_qs) + .qs (ie0_5_e_183_qs) ); - // F[e_169]: 9:9 + // F[e_184]: 24:24 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_169 ( + ) u_ie0_5_e_184 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_169_wd), + .wd (ie0_5_e_184_wd), // from internal hardware .de (1'b0), @@ -15861,26 +17185,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[169].q), + .q (reg2hw.ie0[184].q), .ds (), // to register interface (read) - .qs (ie0_5_e_169_qs) + .qs (ie0_5_e_184_qs) ); - // F[e_170]: 10:10 + // F[e_185]: 25:25 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_170 ( + ) u_ie0_5_e_185 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_170_wd), + .wd (ie0_5_e_185_wd), // from internal hardware .de (1'b0), @@ -15888,26 +17212,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[170].q), + .q (reg2hw.ie0[185].q), .ds (), // to register interface (read) - .qs (ie0_5_e_170_qs) + .qs (ie0_5_e_185_qs) ); - // F[e_171]: 11:11 + // F[e_186]: 26:26 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_171 ( + ) u_ie0_5_e_186 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_171_wd), + .wd (ie0_5_e_186_wd), // from internal hardware .de (1'b0), @@ -15915,26 +17239,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[171].q), + .q (reg2hw.ie0[186].q), .ds (), // to register interface (read) - .qs (ie0_5_e_171_qs) + .qs (ie0_5_e_186_qs) ); - // F[e_172]: 12:12 + // F[e_187]: 27:27 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_172 ( + ) u_ie0_5_e_187 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_172_wd), + .wd (ie0_5_e_187_wd), // from internal hardware .de (1'b0), @@ -15942,26 +17266,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[172].q), + .q (reg2hw.ie0[187].q), .ds (), // to register interface (read) - .qs (ie0_5_e_172_qs) + .qs (ie0_5_e_187_qs) ); - // F[e_173]: 13:13 + // F[e_188]: 28:28 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_173 ( + ) u_ie0_5_e_188 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_173_wd), + .wd (ie0_5_e_188_wd), // from internal hardware .de (1'b0), @@ -15969,26 +17293,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[173].q), + .q (reg2hw.ie0[188].q), .ds (), // to register interface (read) - .qs (ie0_5_e_173_qs) + .qs (ie0_5_e_188_qs) ); - // F[e_174]: 14:14 + // F[e_189]: 29:29 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_174 ( + ) u_ie0_5_e_189 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_174_wd), + .wd (ie0_5_e_189_wd), // from internal hardware .de (1'b0), @@ -15996,26 +17320,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[174].q), + .q (reg2hw.ie0[189].q), .ds (), // to register interface (read) - .qs (ie0_5_e_174_qs) + .qs (ie0_5_e_189_qs) ); - // F[e_175]: 15:15 + // F[e_190]: 30:30 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_175 ( + ) u_ie0_5_e_190 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_175_wd), + .wd (ie0_5_e_190_wd), // from internal hardware .de (1'b0), @@ -16023,26 +17347,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[175].q), + .q (reg2hw.ie0[190].q), .ds (), // to register interface (read) - .qs (ie0_5_e_175_qs) + .qs (ie0_5_e_190_qs) ); - // F[e_176]: 16:16 + // F[e_191]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_176 ( + ) u_ie0_5_e_191 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (ie0_5_we), - .wd (ie0_5_e_176_wd), + .wd (ie0_5_e_191_wd), // from internal hardware .de (1'b0), @@ -16050,26 +17374,29 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[176].q), + .q (reg2hw.ie0[191].q), .ds (), // to register interface (read) - .qs (ie0_5_e_176_qs) + .qs (ie0_5_e_191_qs) ); - // F[e_177]: 17:17 + + // Subregister 6 of Multireg ie0 + // R[ie0_6]: V(False) + // F[e_192]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_177 ( + ) u_ie0_6_e_192 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_177_wd), + .we (ie0_6_we), + .wd (ie0_6_e_192_wd), // from internal hardware .de (1'b0), @@ -16077,26 +17404,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[177].q), + .q (reg2hw.ie0[192].q), .ds (), // to register interface (read) - .qs (ie0_5_e_177_qs) + .qs (ie0_6_e_192_qs) ); - // F[e_178]: 18:18 + // F[e_193]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_178 ( + ) u_ie0_6_e_193 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_178_wd), + .we (ie0_6_we), + .wd (ie0_6_e_193_wd), // from internal hardware .de (1'b0), @@ -16104,26 +17431,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[178].q), + .q (reg2hw.ie0[193].q), .ds (), // to register interface (read) - .qs (ie0_5_e_178_qs) + .qs (ie0_6_e_193_qs) ); - // F[e_179]: 19:19 + // F[e_194]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_179 ( + ) u_ie0_6_e_194 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_179_wd), + .we (ie0_6_we), + .wd (ie0_6_e_194_wd), // from internal hardware .de (1'b0), @@ -16131,26 +17458,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[179].q), + .q (reg2hw.ie0[194].q), .ds (), // to register interface (read) - .qs (ie0_5_e_179_qs) + .qs (ie0_6_e_194_qs) ); - // F[e_180]: 20:20 + // F[e_195]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_180 ( + ) u_ie0_6_e_195 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_180_wd), + .we (ie0_6_we), + .wd (ie0_6_e_195_wd), // from internal hardware .de (1'b0), @@ -16158,26 +17485,26 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[180].q), + .q (reg2hw.ie0[195].q), .ds (), // to register interface (read) - .qs (ie0_5_e_180_qs) + .qs (ie0_6_e_195_qs) ); - // F[e_181]: 21:21 + // F[e_196]: 4:4 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_ie0_5_e_181 ( + ) u_ie0_6_e_196 ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_181_wd), + .we (ie0_6_we), + .wd (ie0_6_e_196_wd), // from internal hardware .de (1'b0), @@ -16185,11 +17512,11 @@ module rv_plic_reg_top ( // to internal hardware .qe (), - .q (reg2hw.ie0[181].q), + .q (reg2hw.ie0[196].q), .ds (), // to register interface (read) - .qs (ie0_5_e_181_qs) + .qs (ie0_6_e_196_qs) ); @@ -16290,7 +17617,7 @@ module rv_plic_reg_top ( - logic [197:0] addr_hit; + logic [214:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO0_OFFSET); @@ -16475,22 +17802,39 @@ module rv_plic_reg_top ( addr_hit[179] = (reg_addr == RV_PLIC_PRIO179_OFFSET); addr_hit[180] = (reg_addr == RV_PLIC_PRIO180_OFFSET); addr_hit[181] = (reg_addr == RV_PLIC_PRIO181_OFFSET); - addr_hit[182] = (reg_addr == RV_PLIC_IP_0_OFFSET); - addr_hit[183] = (reg_addr == RV_PLIC_IP_1_OFFSET); - addr_hit[184] = (reg_addr == RV_PLIC_IP_2_OFFSET); - addr_hit[185] = (reg_addr == RV_PLIC_IP_3_OFFSET); - addr_hit[186] = (reg_addr == RV_PLIC_IP_4_OFFSET); - addr_hit[187] = (reg_addr == RV_PLIC_IP_5_OFFSET); - addr_hit[188] = (reg_addr == RV_PLIC_IE0_0_OFFSET); - addr_hit[189] = (reg_addr == RV_PLIC_IE0_1_OFFSET); - addr_hit[190] = (reg_addr == RV_PLIC_IE0_2_OFFSET); - addr_hit[191] = (reg_addr == RV_PLIC_IE0_3_OFFSET); - addr_hit[192] = (reg_addr == RV_PLIC_IE0_4_OFFSET); - addr_hit[193] = (reg_addr == RV_PLIC_IE0_5_OFFSET); - addr_hit[194] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); - addr_hit[195] = (reg_addr == RV_PLIC_CC0_OFFSET); - addr_hit[196] = (reg_addr == RV_PLIC_MSIP0_OFFSET); - addr_hit[197] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); + addr_hit[182] = (reg_addr == RV_PLIC_PRIO182_OFFSET); + addr_hit[183] = (reg_addr == RV_PLIC_PRIO183_OFFSET); + addr_hit[184] = (reg_addr == RV_PLIC_PRIO184_OFFSET); + addr_hit[185] = (reg_addr == RV_PLIC_PRIO185_OFFSET); + addr_hit[186] = (reg_addr == RV_PLIC_PRIO186_OFFSET); + addr_hit[187] = (reg_addr == RV_PLIC_PRIO187_OFFSET); + addr_hit[188] = (reg_addr == RV_PLIC_PRIO188_OFFSET); + addr_hit[189] = (reg_addr == RV_PLIC_PRIO189_OFFSET); + addr_hit[190] = (reg_addr == RV_PLIC_PRIO190_OFFSET); + addr_hit[191] = (reg_addr == RV_PLIC_PRIO191_OFFSET); + addr_hit[192] = (reg_addr == RV_PLIC_PRIO192_OFFSET); + addr_hit[193] = (reg_addr == RV_PLIC_PRIO193_OFFSET); + addr_hit[194] = (reg_addr == RV_PLIC_PRIO194_OFFSET); + addr_hit[195] = (reg_addr == RV_PLIC_PRIO195_OFFSET); + addr_hit[196] = (reg_addr == RV_PLIC_PRIO196_OFFSET); + addr_hit[197] = (reg_addr == RV_PLIC_IP_0_OFFSET); + addr_hit[198] = (reg_addr == RV_PLIC_IP_1_OFFSET); + addr_hit[199] = (reg_addr == RV_PLIC_IP_2_OFFSET); + addr_hit[200] = (reg_addr == RV_PLIC_IP_3_OFFSET); + addr_hit[201] = (reg_addr == RV_PLIC_IP_4_OFFSET); + addr_hit[202] = (reg_addr == RV_PLIC_IP_5_OFFSET); + addr_hit[203] = (reg_addr == RV_PLIC_IP_6_OFFSET); + addr_hit[204] = (reg_addr == RV_PLIC_IE0_0_OFFSET); + addr_hit[205] = (reg_addr == RV_PLIC_IE0_1_OFFSET); + addr_hit[206] = (reg_addr == RV_PLIC_IE0_2_OFFSET); + addr_hit[207] = (reg_addr == RV_PLIC_IE0_3_OFFSET); + addr_hit[208] = (reg_addr == RV_PLIC_IE0_4_OFFSET); + addr_hit[209] = (reg_addr == RV_PLIC_IE0_5_OFFSET); + addr_hit[210] = (reg_addr == RV_PLIC_IE0_6_OFFSET); + addr_hit[211] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); + addr_hit[212] = (reg_addr == RV_PLIC_CC0_OFFSET); + addr_hit[213] = (reg_addr == RV_PLIC_MSIP0_OFFSET); + addr_hit[214] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -16695,7 +18039,24 @@ module rv_plic_reg_top ( (addr_hit[194] & (|(RV_PLIC_PERMIT[194] & ~reg_be))) | (addr_hit[195] & (|(RV_PLIC_PERMIT[195] & ~reg_be))) | (addr_hit[196] & (|(RV_PLIC_PERMIT[196] & ~reg_be))) | - (addr_hit[197] & (|(RV_PLIC_PERMIT[197] & ~reg_be))))); + (addr_hit[197] & (|(RV_PLIC_PERMIT[197] & ~reg_be))) | + (addr_hit[198] & (|(RV_PLIC_PERMIT[198] & ~reg_be))) | + (addr_hit[199] & (|(RV_PLIC_PERMIT[199] & ~reg_be))) | + (addr_hit[200] & (|(RV_PLIC_PERMIT[200] & ~reg_be))) | + (addr_hit[201] & (|(RV_PLIC_PERMIT[201] & ~reg_be))) | + (addr_hit[202] & (|(RV_PLIC_PERMIT[202] & ~reg_be))) | + (addr_hit[203] & (|(RV_PLIC_PERMIT[203] & ~reg_be))) | + (addr_hit[204] & (|(RV_PLIC_PERMIT[204] & ~reg_be))) | + (addr_hit[205] & (|(RV_PLIC_PERMIT[205] & ~reg_be))) | + (addr_hit[206] & (|(RV_PLIC_PERMIT[206] & ~reg_be))) | + (addr_hit[207] & (|(RV_PLIC_PERMIT[207] & ~reg_be))) | + (addr_hit[208] & (|(RV_PLIC_PERMIT[208] & ~reg_be))) | + (addr_hit[209] & (|(RV_PLIC_PERMIT[209] & ~reg_be))) | + (addr_hit[210] & (|(RV_PLIC_PERMIT[210] & ~reg_be))) | + (addr_hit[211] & (|(RV_PLIC_PERMIT[211] & ~reg_be))) | + (addr_hit[212] & (|(RV_PLIC_PERMIT[212] & ~reg_be))) | + (addr_hit[213] & (|(RV_PLIC_PERMIT[213] & ~reg_be))) | + (addr_hit[214] & (|(RV_PLIC_PERMIT[214] & ~reg_be))))); end // Generate write-enables @@ -17245,7 +18606,52 @@ module rv_plic_reg_top ( assign prio181_we = addr_hit[181] & reg_we & !reg_error; assign prio181_wd = reg_wdata[1:0]; - assign ie0_0_we = addr_hit[188] & reg_we & !reg_error; + assign prio182_we = addr_hit[182] & reg_we & !reg_error; + + assign prio182_wd = reg_wdata[1:0]; + assign prio183_we = addr_hit[183] & reg_we & !reg_error; + + assign prio183_wd = reg_wdata[1:0]; + assign prio184_we = addr_hit[184] & reg_we & !reg_error; + + assign prio184_wd = reg_wdata[1:0]; + assign prio185_we = addr_hit[185] & reg_we & !reg_error; + + assign prio185_wd = reg_wdata[1:0]; + assign prio186_we = addr_hit[186] & reg_we & !reg_error; + + assign prio186_wd = reg_wdata[1:0]; + assign prio187_we = addr_hit[187] & reg_we & !reg_error; + + assign prio187_wd = reg_wdata[1:0]; + assign prio188_we = addr_hit[188] & reg_we & !reg_error; + + assign prio188_wd = reg_wdata[1:0]; + assign prio189_we = addr_hit[189] & reg_we & !reg_error; + + assign prio189_wd = reg_wdata[1:0]; + assign prio190_we = addr_hit[190] & reg_we & !reg_error; + + assign prio190_wd = reg_wdata[1:0]; + assign prio191_we = addr_hit[191] & reg_we & !reg_error; + + assign prio191_wd = reg_wdata[1:0]; + assign prio192_we = addr_hit[192] & reg_we & !reg_error; + + assign prio192_wd = reg_wdata[1:0]; + assign prio193_we = addr_hit[193] & reg_we & !reg_error; + + assign prio193_wd = reg_wdata[1:0]; + assign prio194_we = addr_hit[194] & reg_we & !reg_error; + + assign prio194_wd = reg_wdata[1:0]; + assign prio195_we = addr_hit[195] & reg_we & !reg_error; + + assign prio195_wd = reg_wdata[1:0]; + assign prio196_we = addr_hit[196] & reg_we & !reg_error; + + assign prio196_wd = reg_wdata[1:0]; + assign ie0_0_we = addr_hit[204] & reg_we & !reg_error; assign ie0_0_e_0_wd = reg_wdata[0]; @@ -17310,7 +18716,7 @@ module rv_plic_reg_top ( assign ie0_0_e_30_wd = reg_wdata[30]; assign ie0_0_e_31_wd = reg_wdata[31]; - assign ie0_1_we = addr_hit[189] & reg_we & !reg_error; + assign ie0_1_we = addr_hit[205] & reg_we & !reg_error; assign ie0_1_e_32_wd = reg_wdata[0]; @@ -17375,7 +18781,7 @@ module rv_plic_reg_top ( assign ie0_1_e_62_wd = reg_wdata[30]; assign ie0_1_e_63_wd = reg_wdata[31]; - assign ie0_2_we = addr_hit[190] & reg_we & !reg_error; + assign ie0_2_we = addr_hit[206] & reg_we & !reg_error; assign ie0_2_e_64_wd = reg_wdata[0]; @@ -17440,7 +18846,7 @@ module rv_plic_reg_top ( assign ie0_2_e_94_wd = reg_wdata[30]; assign ie0_2_e_95_wd = reg_wdata[31]; - assign ie0_3_we = addr_hit[191] & reg_we & !reg_error; + assign ie0_3_we = addr_hit[207] & reg_we & !reg_error; assign ie0_3_e_96_wd = reg_wdata[0]; @@ -17505,7 +18911,7 @@ module rv_plic_reg_top ( assign ie0_3_e_126_wd = reg_wdata[30]; assign ie0_3_e_127_wd = reg_wdata[31]; - assign ie0_4_we = addr_hit[192] & reg_we & !reg_error; + assign ie0_4_we = addr_hit[208] & reg_we & !reg_error; assign ie0_4_e_128_wd = reg_wdata[0]; @@ -17570,7 +18976,7 @@ module rv_plic_reg_top ( assign ie0_4_e_158_wd = reg_wdata[30]; assign ie0_4_e_159_wd = reg_wdata[31]; - assign ie0_5_we = addr_hit[193] & reg_we & !reg_error; + assign ie0_5_we = addr_hit[209] & reg_we & !reg_error; assign ie0_5_e_160_wd = reg_wdata[0]; @@ -17615,17 +19021,48 @@ module rv_plic_reg_top ( assign ie0_5_e_180_wd = reg_wdata[20]; assign ie0_5_e_181_wd = reg_wdata[21]; - assign threshold0_we = addr_hit[194] & reg_we & !reg_error; + + assign ie0_5_e_182_wd = reg_wdata[22]; + + assign ie0_5_e_183_wd = reg_wdata[23]; + + assign ie0_5_e_184_wd = reg_wdata[24]; + + assign ie0_5_e_185_wd = reg_wdata[25]; + + assign ie0_5_e_186_wd = reg_wdata[26]; + + assign ie0_5_e_187_wd = reg_wdata[27]; + + assign ie0_5_e_188_wd = reg_wdata[28]; + + assign ie0_5_e_189_wd = reg_wdata[29]; + + assign ie0_5_e_190_wd = reg_wdata[30]; + + assign ie0_5_e_191_wd = reg_wdata[31]; + assign ie0_6_we = addr_hit[210] & reg_we & !reg_error; + + assign ie0_6_e_192_wd = reg_wdata[0]; + + assign ie0_6_e_193_wd = reg_wdata[1]; + + assign ie0_6_e_194_wd = reg_wdata[2]; + + assign ie0_6_e_195_wd = reg_wdata[3]; + + assign ie0_6_e_196_wd = reg_wdata[4]; + assign threshold0_we = addr_hit[211] & reg_we & !reg_error; assign threshold0_wd = reg_wdata[1:0]; - assign cc0_re = addr_hit[195] & reg_re & !reg_error; - assign cc0_we = addr_hit[195] & reg_we & !reg_error; + assign cc0_re = addr_hit[212] & reg_re & !reg_error; + assign cc0_we = addr_hit[212] & reg_we & !reg_error; assign cc0_wd = reg_wdata[7:0]; - assign msip0_we = addr_hit[196] & reg_we & !reg_error; + assign msip0_we = addr_hit[213] & reg_we & !reg_error; assign msip0_wd = reg_wdata[0]; - assign alert_test_we = addr_hit[197] & reg_we & !reg_error; + assign alert_test_we = addr_hit[214] & reg_we & !reg_error; assign alert_test_wd = reg_wdata[0]; @@ -17814,22 +19251,39 @@ module rv_plic_reg_top ( reg_we_check[179] = prio179_we; reg_we_check[180] = prio180_we; reg_we_check[181] = prio181_we; - reg_we_check[182] = 1'b0; - reg_we_check[183] = 1'b0; - reg_we_check[184] = 1'b0; - reg_we_check[185] = 1'b0; - reg_we_check[186] = 1'b0; - reg_we_check[187] = 1'b0; - reg_we_check[188] = ie0_0_we; - reg_we_check[189] = ie0_1_we; - reg_we_check[190] = ie0_2_we; - reg_we_check[191] = ie0_3_we; - reg_we_check[192] = ie0_4_we; - reg_we_check[193] = ie0_5_we; - reg_we_check[194] = threshold0_we; - reg_we_check[195] = cc0_we; - reg_we_check[196] = msip0_we; - reg_we_check[197] = alert_test_we; + reg_we_check[182] = prio182_we; + reg_we_check[183] = prio183_we; + reg_we_check[184] = prio184_we; + reg_we_check[185] = prio185_we; + reg_we_check[186] = prio186_we; + reg_we_check[187] = prio187_we; + reg_we_check[188] = prio188_we; + reg_we_check[189] = prio189_we; + reg_we_check[190] = prio190_we; + reg_we_check[191] = prio191_we; + reg_we_check[192] = prio192_we; + reg_we_check[193] = prio193_we; + reg_we_check[194] = prio194_we; + reg_we_check[195] = prio195_we; + reg_we_check[196] = prio196_we; + reg_we_check[197] = 1'b0; + reg_we_check[198] = 1'b0; + reg_we_check[199] = 1'b0; + reg_we_check[200] = 1'b0; + reg_we_check[201] = 1'b0; + reg_we_check[202] = 1'b0; + reg_we_check[203] = 1'b0; + reg_we_check[204] = ie0_0_we; + reg_we_check[205] = ie0_1_we; + reg_we_check[206] = ie0_2_we; + reg_we_check[207] = ie0_3_we; + reg_we_check[208] = ie0_4_we; + reg_we_check[209] = ie0_5_we; + reg_we_check[210] = ie0_6_we; + reg_we_check[211] = threshold0_we; + reg_we_check[212] = cc0_we; + reg_we_check[213] = msip0_we; + reg_we_check[214] = alert_test_we; end // Read data return @@ -18565,6 +20019,66 @@ module rv_plic_reg_top ( end addr_hit[182]: begin + reg_rdata_next[1:0] = prio182_qs; + end + + addr_hit[183]: begin + reg_rdata_next[1:0] = prio183_qs; + end + + addr_hit[184]: begin + reg_rdata_next[1:0] = prio184_qs; + end + + addr_hit[185]: begin + reg_rdata_next[1:0] = prio185_qs; + end + + addr_hit[186]: begin + reg_rdata_next[1:0] = prio186_qs; + end + + addr_hit[187]: begin + reg_rdata_next[1:0] = prio187_qs; + end + + addr_hit[188]: begin + reg_rdata_next[1:0] = prio188_qs; + end + + addr_hit[189]: begin + reg_rdata_next[1:0] = prio189_qs; + end + + addr_hit[190]: begin + reg_rdata_next[1:0] = prio190_qs; + end + + addr_hit[191]: begin + reg_rdata_next[1:0] = prio191_qs; + end + + addr_hit[192]: begin + reg_rdata_next[1:0] = prio192_qs; + end + + addr_hit[193]: begin + reg_rdata_next[1:0] = prio193_qs; + end + + addr_hit[194]: begin + reg_rdata_next[1:0] = prio194_qs; + end + + addr_hit[195]: begin + reg_rdata_next[1:0] = prio195_qs; + end + + addr_hit[196]: begin + reg_rdata_next[1:0] = prio196_qs; + end + + addr_hit[197]: begin reg_rdata_next[0] = ip_0_p_0_qs; reg_rdata_next[1] = ip_0_p_1_qs; reg_rdata_next[2] = ip_0_p_2_qs; @@ -18599,7 +20113,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_0_p_31_qs; end - addr_hit[183]: begin + addr_hit[198]: begin reg_rdata_next[0] = ip_1_p_32_qs; reg_rdata_next[1] = ip_1_p_33_qs; reg_rdata_next[2] = ip_1_p_34_qs; @@ -18634,7 +20148,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_1_p_63_qs; end - addr_hit[184]: begin + addr_hit[199]: begin reg_rdata_next[0] = ip_2_p_64_qs; reg_rdata_next[1] = ip_2_p_65_qs; reg_rdata_next[2] = ip_2_p_66_qs; @@ -18669,7 +20183,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_2_p_95_qs; end - addr_hit[185]: begin + addr_hit[200]: begin reg_rdata_next[0] = ip_3_p_96_qs; reg_rdata_next[1] = ip_3_p_97_qs; reg_rdata_next[2] = ip_3_p_98_qs; @@ -18704,7 +20218,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_3_p_127_qs; end - addr_hit[186]: begin + addr_hit[201]: begin reg_rdata_next[0] = ip_4_p_128_qs; reg_rdata_next[1] = ip_4_p_129_qs; reg_rdata_next[2] = ip_4_p_130_qs; @@ -18739,7 +20253,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_4_p_159_qs; end - addr_hit[187]: begin + addr_hit[202]: begin reg_rdata_next[0] = ip_5_p_160_qs; reg_rdata_next[1] = ip_5_p_161_qs; reg_rdata_next[2] = ip_5_p_162_qs; @@ -18762,9 +20276,27 @@ module rv_plic_reg_top ( reg_rdata_next[19] = ip_5_p_179_qs; reg_rdata_next[20] = ip_5_p_180_qs; reg_rdata_next[21] = ip_5_p_181_qs; + reg_rdata_next[22] = ip_5_p_182_qs; + reg_rdata_next[23] = ip_5_p_183_qs; + reg_rdata_next[24] = ip_5_p_184_qs; + reg_rdata_next[25] = ip_5_p_185_qs; + reg_rdata_next[26] = ip_5_p_186_qs; + reg_rdata_next[27] = ip_5_p_187_qs; + reg_rdata_next[28] = ip_5_p_188_qs; + reg_rdata_next[29] = ip_5_p_189_qs; + reg_rdata_next[30] = ip_5_p_190_qs; + reg_rdata_next[31] = ip_5_p_191_qs; end - addr_hit[188]: begin + addr_hit[203]: begin + reg_rdata_next[0] = ip_6_p_192_qs; + reg_rdata_next[1] = ip_6_p_193_qs; + reg_rdata_next[2] = ip_6_p_194_qs; + reg_rdata_next[3] = ip_6_p_195_qs; + reg_rdata_next[4] = ip_6_p_196_qs; + end + + addr_hit[204]: begin reg_rdata_next[0] = ie0_0_e_0_qs; reg_rdata_next[1] = ie0_0_e_1_qs; reg_rdata_next[2] = ie0_0_e_2_qs; @@ -18799,7 +20331,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_0_e_31_qs; end - addr_hit[189]: begin + addr_hit[205]: begin reg_rdata_next[0] = ie0_1_e_32_qs; reg_rdata_next[1] = ie0_1_e_33_qs; reg_rdata_next[2] = ie0_1_e_34_qs; @@ -18834,7 +20366,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_1_e_63_qs; end - addr_hit[190]: begin + addr_hit[206]: begin reg_rdata_next[0] = ie0_2_e_64_qs; reg_rdata_next[1] = ie0_2_e_65_qs; reg_rdata_next[2] = ie0_2_e_66_qs; @@ -18869,7 +20401,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_2_e_95_qs; end - addr_hit[191]: begin + addr_hit[207]: begin reg_rdata_next[0] = ie0_3_e_96_qs; reg_rdata_next[1] = ie0_3_e_97_qs; reg_rdata_next[2] = ie0_3_e_98_qs; @@ -18904,7 +20436,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_3_e_127_qs; end - addr_hit[192]: begin + addr_hit[208]: begin reg_rdata_next[0] = ie0_4_e_128_qs; reg_rdata_next[1] = ie0_4_e_129_qs; reg_rdata_next[2] = ie0_4_e_130_qs; @@ -18939,7 +20471,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_4_e_159_qs; end - addr_hit[193]: begin + addr_hit[209]: begin reg_rdata_next[0] = ie0_5_e_160_qs; reg_rdata_next[1] = ie0_5_e_161_qs; reg_rdata_next[2] = ie0_5_e_162_qs; @@ -18962,21 +20494,39 @@ module rv_plic_reg_top ( reg_rdata_next[19] = ie0_5_e_179_qs; reg_rdata_next[20] = ie0_5_e_180_qs; reg_rdata_next[21] = ie0_5_e_181_qs; + reg_rdata_next[22] = ie0_5_e_182_qs; + reg_rdata_next[23] = ie0_5_e_183_qs; + reg_rdata_next[24] = ie0_5_e_184_qs; + reg_rdata_next[25] = ie0_5_e_185_qs; + reg_rdata_next[26] = ie0_5_e_186_qs; + reg_rdata_next[27] = ie0_5_e_187_qs; + reg_rdata_next[28] = ie0_5_e_188_qs; + reg_rdata_next[29] = ie0_5_e_189_qs; + reg_rdata_next[30] = ie0_5_e_190_qs; + reg_rdata_next[31] = ie0_5_e_191_qs; end - addr_hit[194]: begin + addr_hit[210]: begin + reg_rdata_next[0] = ie0_6_e_192_qs; + reg_rdata_next[1] = ie0_6_e_193_qs; + reg_rdata_next[2] = ie0_6_e_194_qs; + reg_rdata_next[3] = ie0_6_e_195_qs; + reg_rdata_next[4] = ie0_6_e_196_qs; + end + + addr_hit[211]: begin reg_rdata_next[1:0] = threshold0_qs; end - addr_hit[195]: begin + addr_hit[212]: begin reg_rdata_next[7:0] = cc0_qs; end - addr_hit[196]: begin + addr_hit[213]: begin reg_rdata_next[0] = msip0_qs; end - addr_hit[197]: begin + addr_hit[214]: begin reg_rdata_next[0] = '0; end diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 4fecb176b33e9b..6c82064eff715d 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -25,6 +25,7 @@ module top_earlgrey #( // parameters for i2c0 // parameters for i2c1 // parameters for i2c2 + // parameters for i2c3 // parameters for pattgen // parameters for rv_timer // parameters for otp_ctrl @@ -214,9 +215,9 @@ module top_earlgrey #( import top_earlgrey_rnd_cnst_pkg::*; // Signals - logic [56:0] mio_p2d; - logic [74:0] mio_d2p; - logic [74:0] mio_en_d2p; + logic [58:0] mio_p2d; + logic [76:0] mio_d2p; + logic [76:0] mio_en_d2p; logic [15:0] dio_p2d; logic [15:0] dio_d2p; logic [15:0] dio_en_d2p; @@ -268,6 +269,13 @@ module top_earlgrey #( logic cio_i2c2_sda_en_d2p; logic cio_i2c2_scl_d2p; logic cio_i2c2_scl_en_d2p; + // i2c3 + logic cio_i2c3_sda_p2d; + logic cio_i2c3_scl_p2d; + logic cio_i2c3_sda_d2p; + logic cio_i2c3_sda_en_d2p; + logic cio_i2c3_scl_d2p; + logic cio_i2c3_scl_en_d2p; // pattgen logic cio_pattgen_pda0_tx_d2p; logic cio_pattgen_pda0_tx_en_d2p; @@ -367,7 +375,7 @@ module top_earlgrey #( // rv_core_ibex - logic [181:0] intr_vector; + logic [196:0] intr_vector; // Interrupt source list logic intr_uart0_tx_watermark; logic intr_uart0_rx_watermark; @@ -455,6 +463,21 @@ module top_earlgrey #( logic intr_i2c2_acq_full; logic intr_i2c2_unexp_stop; logic intr_i2c2_host_timeout; + logic intr_i2c3_fmt_threshold; + logic intr_i2c3_rx_threshold; + logic intr_i2c3_fmt_overflow; + logic intr_i2c3_rx_overflow; + logic intr_i2c3_nak; + logic intr_i2c3_scl_interference; + logic intr_i2c3_sda_interference; + logic intr_i2c3_stretch_timeout; + logic intr_i2c3_sda_unstable; + logic intr_i2c3_cmd_complete; + logic intr_i2c3_tx_stretch; + logic intr_i2c3_tx_overflow; + logic intr_i2c3_acq_full; + logic intr_i2c3_unexp_stop; + logic intr_i2c3_host_timeout; logic intr_pattgen_done_ch0; logic intr_pattgen_done_ch1; logic intr_rv_timer_timer_expired_hart0_timer0; @@ -689,6 +712,8 @@ module top_earlgrey #( tlul_pkg::tl_d2h_t i2c1_tl_rsp; tlul_pkg::tl_h2d_t i2c2_tl_req; tlul_pkg::tl_d2h_t i2c2_tl_rsp; + tlul_pkg::tl_h2d_t i2c3_tl_req; + tlul_pkg::tl_d2h_t i2c3_tl_rsp; tlul_pkg::tl_h2d_t pattgen_tl_req; tlul_pkg::tl_d2h_t pattgen_tl_rsp; tlul_pkg::tl_h2d_t pwm_aon_tl_req; @@ -850,63 +875,66 @@ module top_earlgrey #( // peri_i2c2_0 assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri; assign lpg_rst_en[4] = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::Domain0Sel]; + // peri_i2c3_0 + assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[5] = rstmgr_aon_rst_en.i2c3[rstmgr_pkg::Domain0Sel]; // timers_lc_io_div4_0 - assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_timers; - assign lpg_rst_en[5] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; - // secure_lc_io_div4_0 - assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_secure; + assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_timers; assign lpg_rst_en[6] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // secure_lc_io_div4_0 + assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_div4_secure; + assign lpg_rst_en[7] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; // peri_spi_host0_0 - assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_peri; - assign lpg_rst_en[7] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel]; + assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_peri; + assign lpg_rst_en[8] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel]; // peri_spi_host1_0 - assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_div2_peri; - assign lpg_rst_en[8] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel]; + assign lpg_cg_en[9] = clkmgr_aon_cg_en.io_div2_peri; + assign lpg_rst_en[9] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel]; // peri_usb_0 - assign lpg_cg_en[9] = clkmgr_aon_cg_en.usb_peri; - assign lpg_rst_en[9] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel]; + assign lpg_cg_en[10] = clkmgr_aon_cg_en.usb_peri; + assign lpg_rst_en[10] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel]; // powerup_por_io_div4_Aon - assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_powerup; - assign lpg_rst_en[10] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel]; - // powerup_lc_io_div4_Aon assign lpg_cg_en[11] = clkmgr_aon_cg_en.io_div4_powerup; - assign lpg_rst_en[11] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; - // secure_lc_io_div4_Aon - assign lpg_cg_en[12] = clkmgr_aon_cg_en.io_div4_secure; + assign lpg_rst_en[11] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel]; + // powerup_lc_io_div4_Aon + assign lpg_cg_en[12] = clkmgr_aon_cg_en.io_div4_powerup; assign lpg_rst_en[12] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; - // peri_lc_io_div4_Aon - assign lpg_cg_en[13] = clkmgr_aon_cg_en.io_div4_peri; + // secure_lc_io_div4_Aon + assign lpg_cg_en[13] = clkmgr_aon_cg_en.io_div4_secure; assign lpg_rst_en[13] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; - // timers_lc_io_div4_Aon - assign lpg_cg_en[14] = clkmgr_aon_cg_en.io_div4_timers; + // peri_lc_io_div4_Aon + assign lpg_cg_en[14] = clkmgr_aon_cg_en.io_div4_peri; assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // timers_lc_io_div4_Aon + assign lpg_cg_en[15] = clkmgr_aon_cg_en.io_div4_timers; + assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; // infra_lc_io_div4_0 - assign lpg_cg_en[15] = clkmgr_aon_cg_en.io_div4_infra; - assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; - // infra_lc_io_div4_Aon assign lpg_cg_en[16] = clkmgr_aon_cg_en.io_div4_infra; - assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // infra_lc_io_div4_Aon + assign lpg_cg_en[17] = clkmgr_aon_cg_en.io_div4_infra; + assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; // infra_lc_0 - assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_infra; - assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // infra_sys_0 assign lpg_cg_en[18] = clkmgr_aon_cg_en.main_infra; - assign lpg_rst_en[18] = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel]; + assign lpg_rst_en[18] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // infra_sys_0 + assign lpg_cg_en[19] = clkmgr_aon_cg_en.main_infra; + assign lpg_rst_en[19] = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel]; // secure_lc_0 - assign lpg_cg_en[19] = clkmgr_aon_cg_en.main_secure; - assign lpg_rst_en[19] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // aes_trans_lc_0 - assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_aes; + assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_secure; assign lpg_rst_en[20] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // hmac_trans_lc_0 - assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_hmac; + // aes_trans_lc_0 + assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_aes; assign lpg_rst_en[21] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // kmac_trans_lc_0 - assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_kmac; + // hmac_trans_lc_0 + assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_hmac; assign lpg_rst_en[22] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // otbn_trans_lc_0 - assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_otbn; + // kmac_trans_lc_0 + assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_kmac; assign lpg_rst_en[23] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // otbn_trans_lc_0 + assign lpg_cg_en[24] = clkmgr_aon_cg_en.main_otbn; + assign lpg_rst_en[24] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; // tie-off unused connections //VCS coverage off @@ -1005,6 +1033,8 @@ module top_earlgrey #( assign unused_rst_en_34 = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::DomainAonSel]; prim_mubi_pkg::mubi4_t unused_rst_en_35; assign unused_rst_en_35 = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_36; + assign unused_rst_en_36 = rstmgr_aon_rst_en.i2c3[rstmgr_pkg::DomainAonSel]; //VCS coverage on // pragma coverage on @@ -1335,8 +1365,50 @@ module top_earlgrey #( .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), .rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel]) ); - pattgen #( + i2c #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9]) + ) u_i2c3 ( + + // Input + .cio_sda_i (cio_i2c3_sda_p2d), + .cio_scl_i (cio_i2c3_scl_p2d), + + // Output + .cio_sda_o (cio_i2c3_sda_d2p), + .cio_sda_en_o (cio_i2c3_sda_en_d2p), + .cio_scl_o (cio_i2c3_scl_d2p), + .cio_scl_en_o (cio_i2c3_scl_en_d2p), + + // Interrupt + .intr_fmt_threshold_o (intr_i2c3_fmt_threshold), + .intr_rx_threshold_o (intr_i2c3_rx_threshold), + .intr_fmt_overflow_o (intr_i2c3_fmt_overflow), + .intr_rx_overflow_o (intr_i2c3_rx_overflow), + .intr_nak_o (intr_i2c3_nak), + .intr_scl_interference_o (intr_i2c3_scl_interference), + .intr_sda_interference_o (intr_i2c3_sda_interference), + .intr_stretch_timeout_o (intr_i2c3_stretch_timeout), + .intr_sda_unstable_o (intr_i2c3_sda_unstable), + .intr_cmd_complete_o (intr_i2c3_cmd_complete), + .intr_tx_stretch_o (intr_i2c3_tx_stretch), + .intr_tx_overflow_o (intr_i2c3_tx_overflow), + .intr_acq_full_o (intr_i2c3_acq_full), + .intr_unexp_stop_o (intr_i2c3_unexp_stop), + .intr_host_timeout_o (intr_i2c3_host_timeout), + // [9]: fatal_fault + .alert_tx_o ( alert_tx[9:9] ), + .alert_rx_i ( alert_rx[9:9] ), + + // Inter-module signals + .tl_i(i2c3_tl_req), + .tl_o(i2c3_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_i2c3_n[rstmgr_pkg::Domain0Sel]) + ); + pattgen #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10]) ) u_pattgen ( // Output @@ -1352,9 +1424,9 @@ module top_earlgrey #( // Interrupt .intr_done_ch0_o (intr_pattgen_done_ch0), .intr_done_ch1_o (intr_pattgen_done_ch1), - // [9]: fatal_fault - .alert_tx_o ( alert_tx[9:9] ), - .alert_rx_i ( alert_rx[9:9] ), + // [10]: fatal_fault + .alert_tx_o ( alert_tx[10:10] ), + .alert_rx_i ( alert_rx[10:10] ), // Inter-module signals .tl_i(pattgen_tl_req), @@ -1365,14 +1437,14 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); rv_timer #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[11:11]) ) u_rv_timer ( // Interrupt .intr_timer_expired_hart0_timer0_o (intr_rv_timer_timer_expired_hart0_timer0), - // [10]: fatal_fault - .alert_tx_o ( alert_tx[10:10] ), - .alert_rx_i ( alert_rx[10:10] ), + // [11]: fatal_fault + .alert_tx_o ( alert_tx[11:11] ), + .alert_rx_i ( alert_rx[11:11] ), // Inter-module signals .tl_i(rv_timer_tl_req), @@ -1383,7 +1455,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); otp_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:11]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:12]), .MemInitFile(OtpCtrlMemInitFile), .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed), .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm), @@ -1397,13 +1469,13 @@ module top_earlgrey #( // Interrupt .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done), .intr_otp_error_o (intr_otp_ctrl_otp_error), - // [11]: fatal_macro_error - // [12]: fatal_check_error - // [13]: fatal_bus_integ_error - // [14]: fatal_prim_otp_alert - // [15]: recov_prim_otp_alert - .alert_tx_o ( alert_tx[15:11] ), - .alert_rx_i ( alert_rx[15:11] ), + // [12]: fatal_macro_error + // [13]: fatal_check_error + // [14]: fatal_bus_integ_error + // [15]: fatal_prim_otp_alert + // [16]: recov_prim_otp_alert + .alert_tx_o ( alert_tx[16:12] ), + .alert_rx_i ( alert_rx[16:12] ), // Inter-module signals .otp_ext_voltage_h_io(otp_ext_voltage_h_io), @@ -1449,7 +1521,7 @@ module top_earlgrey #( .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); lc_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:16]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:17]), .SecVolatileRawUnlockEn(SecLcCtrlVolatileRawUnlockEn), .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid), .RndCnstLcKeymgrDivTestUnlocked(RndCnstLcCtrlLcKeymgrDivTestUnlocked), @@ -1462,11 +1534,11 @@ module top_earlgrey #( .RevisionId(LcCtrlRevisionId), .IdcodeValue(LcCtrlIdcodeValue) ) u_lc_ctrl ( - // [16]: fatal_prog_error - // [17]: fatal_state_error - // [18]: fatal_bus_integ_error - .alert_tx_o ( alert_tx[18:16] ), - .alert_rx_i ( alert_rx[18:16] ), + // [17]: fatal_prog_error + // [18]: fatal_state_error + // [19]: fatal_bus_integ_error + .alert_tx_o ( alert_tx[19:17] ), + .alert_rx_i ( alert_rx[19:17] ), // Inter-module signals .jtag_i(pinmux_aon_lc_jtag_req), @@ -1552,7 +1624,7 @@ module top_earlgrey #( .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); spi_host #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20]) ) u_spi_host0 ( // Input @@ -1569,9 +1641,9 @@ module top_earlgrey #( // Interrupt .intr_error_o (intr_spi_host0_error), .intr_spi_event_o (intr_spi_host0_spi_event), - // [19]: fatal_fault - .alert_tx_o ( alert_tx[19:19] ), - .alert_rx_i ( alert_rx[19:19] ), + // [20]: fatal_fault + .alert_tx_o ( alert_tx[20:20] ), + .alert_rx_i ( alert_rx[20:20] ), // Inter-module signals .passthrough_i(spi_device_passthrough_req), @@ -1584,7 +1656,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]) ); spi_host #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]) ) u_spi_host1 ( // Input @@ -1601,9 +1673,9 @@ module top_earlgrey #( // Interrupt .intr_error_o (intr_spi_host1_error), .intr_spi_event_o (intr_spi_host1_spi_event), - // [20]: fatal_fault - .alert_tx_o ( alert_tx[20:20] ), - .alert_rx_i ( alert_rx[20:20] ), + // [21]: fatal_fault + .alert_tx_o ( alert_tx[21:21] ), + .alert_rx_i ( alert_rx[21:21] ), // Inter-module signals .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT), @@ -1616,7 +1688,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]) ); usbdev #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22]), .Stub(UsbdevStub), .RcvrWakeTimeUs(UsbdevRcvrWakeTimeUs) ) u_usbdev ( @@ -1651,9 +1723,9 @@ module top_earlgrey #( .intr_powered_o (intr_usbdev_powered), .intr_link_out_err_o (intr_usbdev_link_out_err), .intr_av_setup_empty_o (intr_usbdev_av_setup_empty), - // [21]: fatal_fault - .alert_tx_o ( alert_tx[21:21] ), - .alert_rx_i ( alert_rx[21:21] ), + // [22]: fatal_fault + .alert_tx_o ( alert_tx[22:22] ), + .alert_rx_i ( alert_rx[22:22] ), // Inter-module signals .usb_rx_d_i(usbdev_usb_rx_d_i), @@ -1681,14 +1753,14 @@ module top_earlgrey #( .rst_aon_ni (rstmgr_aon_resets.rst_usb_aon_n[rstmgr_pkg::Domain0Sel]) ); pwrmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:23]) ) u_pwrmgr_aon ( // Interrupt .intr_wakeup_o (intr_pwrmgr_aon_wakeup), - // [22]: fatal_fault - .alert_tx_o ( alert_tx[22:22] ), - .alert_rx_i ( alert_rx[22:22] ), + // [23]: fatal_fault + .alert_tx_o ( alert_tx[23:23] ), + .alert_rx_i ( alert_rx[23:23] ), // Inter-module signals .pwr_ast_o(pwrmgr_ast_req_o), @@ -1730,14 +1802,14 @@ module top_earlgrey #( .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]) ); rstmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:23]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:24]), .SecCheck(SecRstmgrAonCheck), .SecMaxSyncDelay(SecRstmgrAonMaxSyncDelay) ) u_rstmgr_aon ( - // [23]: fatal_fault - // [24]: fatal_cnsty_fault - .alert_tx_o ( alert_tx[24:23] ), - .alert_rx_i ( alert_rx[24:23] ), + // [24]: fatal_fault + // [25]: fatal_cnsty_fault + .alert_tx_o ( alert_tx[25:24] ), + .alert_rx_i ( alert_rx[25:24] ), // Inter-module signals .por_n_i(por_n_i), @@ -1766,12 +1838,12 @@ module top_earlgrey #( .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]) ); clkmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:26]) ) u_clkmgr_aon ( - // [25]: recov_fault - // [26]: fatal_fault - .alert_tx_o ( alert_tx[26:25] ), - .alert_rx_i ( alert_rx[26:25] ), + // [26]: recov_fault + // [27]: fatal_fault + .alert_tx_o ( alert_tx[27:26] ), + .alert_rx_i ( alert_rx[27:26] ), // Inter-module signals .clocks_o(clkmgr_aon_clocks), @@ -1816,7 +1888,7 @@ module top_earlgrey #( .rst_root_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]) ); sysrst_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28]) ) u_sysrst_ctrl_aon ( // Input @@ -1849,9 +1921,9 @@ module top_earlgrey #( // Interrupt .intr_event_detected_o (intr_sysrst_ctrl_aon_event_detected), - // [27]: fatal_fault - .alert_tx_o ( alert_tx[27:27] ), - .alert_rx_i ( alert_rx[27:27] ), + // [28]: fatal_fault + .alert_tx_o ( alert_tx[28:28] ), + .alert_rx_i ( alert_rx[28:28] ), // Inter-module signals .wkup_req_o(pwrmgr_aon_wakeups[0]), @@ -1866,14 +1938,14 @@ module top_earlgrey #( .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) ); adc_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29]) ) u_adc_ctrl_aon ( // Interrupt .intr_match_done_o (intr_adc_ctrl_aon_match_done), - // [28]: fatal_fault - .alert_tx_o ( alert_tx[28:28] ), - .alert_rx_i ( alert_rx[28:28] ), + // [29]: fatal_fault + .alert_tx_o ( alert_tx[29:29] ), + .alert_rx_i ( alert_rx[29:29] ), // Inter-module signals .adc_o(adc_req_o), @@ -1889,15 +1961,15 @@ module top_earlgrey #( .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) ); pwm #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]) ) u_pwm_aon ( // Output .cio_pwm_o (cio_pwm_aon_pwm_d2p), .cio_pwm_en_o (cio_pwm_aon_pwm_en_d2p), - // [29]: fatal_fault - .alert_tx_o ( alert_tx[29:29] ), - .alert_rx_i ( alert_rx[29:29] ), + // [30]: fatal_fault + .alert_tx_o ( alert_tx[30:30] ), + .alert_rx_i ( alert_rx[30:30] ), // Inter-module signals .tl_i(pwm_aon_tl_req), @@ -1910,13 +1982,13 @@ module top_earlgrey #( .rst_core_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) ); pinmux #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31]), .SecVolatileRawUnlockEn(SecPinmuxAonVolatileRawUnlockEn), .TargetCfg(PinmuxAonTargetCfg) ) u_pinmux_aon ( - // [30]: fatal_fault - .alert_tx_o ( alert_tx[30:30] ), - .alert_rx_i ( alert_rx[30:30] ), + // [31]: fatal_fault + .alert_tx_o ( alert_tx[31:31] ), + .alert_rx_i ( alert_rx[31:31] ), // Inter-module signals .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), @@ -1977,15 +2049,15 @@ module top_earlgrey #( .rst_sys_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]) ); aon_timer #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[32:32]) ) u_aon_timer_aon ( // Interrupt .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired), .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark), - // [31]: fatal_fault - .alert_tx_o ( alert_tx[31:31] ), - .alert_rx_i ( alert_rx[31:31] ), + // [32]: fatal_fault + .alert_tx_o ( alert_tx[32:32] ), + .alert_rx_i ( alert_rx[32:32] ), // Inter-module signals .nmi_wdog_timer_bark_o(aon_timer_aon_nmi_wdog_timer_bark), @@ -2003,7 +2075,7 @@ module top_earlgrey #( .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) ); sensor_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:33]) ) u_sensor_ctrl_aon ( // Output @@ -2013,10 +2085,10 @@ module top_earlgrey #( // Interrupt .intr_io_status_change_o (intr_sensor_ctrl_aon_io_status_change), .intr_init_status_change_o (intr_sensor_ctrl_aon_init_status_change), - // [32]: recov_alert - // [33]: fatal_alert - .alert_tx_o ( alert_tx[33:32] ), - .alert_rx_i ( alert_rx[33:32] ), + // [33]: recov_alert + // [34]: fatal_alert + .alert_tx_o ( alert_tx[34:33] ), + .alert_rx_i ( alert_rx[34:33] ), // Inter-module signals .ast_alert_i(sensor_ctrl_ast_alert_req_i), @@ -2035,7 +2107,7 @@ module top_earlgrey #( .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:35]), .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey), .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce), .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), @@ -2043,9 +2115,9 @@ module top_earlgrey #( .MemSizeRam(4096), .InstrExec(SramCtrlRetAonInstrExec) ) u_sram_ctrl_ret_aon ( - // [34]: fatal_error - .alert_tx_o ( alert_tx[34:34] ), - .alert_rx_i ( alert_rx[34:34] ), + // [35]: fatal_error + .alert_tx_o ( alert_tx[35:35] ), + .alert_rx_i ( alert_rx[35:35] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), @@ -2066,7 +2138,7 @@ module top_earlgrey #( .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]) ); flash_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:35]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:36]), .RndCnstAddrKey(RndCnstFlashCtrlAddrKey), .RndCnstDataKey(RndCnstFlashCtrlDataKey), .RndCnstAllSeeds(RndCnstFlashCtrlAllSeeds), @@ -2093,13 +2165,13 @@ module top_earlgrey #( .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl), .intr_op_done_o (intr_flash_ctrl_op_done), .intr_corr_err_o (intr_flash_ctrl_corr_err), - // [35]: recov_err - // [36]: fatal_std_err - // [37]: fatal_err - // [38]: fatal_prim_flash_alert - // [39]: recov_prim_flash_alert - .alert_tx_o ( alert_tx[39:35] ), - .alert_rx_i ( alert_rx[39:35] ), + // [36]: recov_err + // [37]: fatal_std_err + // [38]: fatal_err + // [39]: fatal_prim_flash_alert + // [40]: recov_prim_flash_alert + .alert_tx_o ( alert_tx[40:36] ), + .alert_rx_i ( alert_rx[40:36] ), // Inter-module signals .otp_o(flash_ctrl_otp_req), @@ -2141,12 +2213,12 @@ module top_earlgrey #( .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); rv_dm #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41]), .IdcodeValue(RvDmIdcodeValue) ) u_rv_dm ( - // [40]: fatal_fault - .alert_tx_o ( alert_tx[40:40] ), - .alert_rx_i ( alert_rx[40:40] ), + // [41]: fatal_fault + .alert_tx_o ( alert_tx[41:41] ), + .alert_rx_i ( alert_rx[41:41] ), // Inter-module signals .jtag_i(pinmux_aon_rv_jtag_req), @@ -2171,11 +2243,11 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); rv_plic #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:42]) ) u_rv_plic ( - // [41]: fatal_fault - .alert_tx_o ( alert_tx[41:41] ), - .alert_rx_i ( alert_rx[41:41] ), + // [42]: fatal_fault + .alert_tx_o ( alert_tx[42:42] ), + .alert_rx_i ( alert_rx[42:42] ), // Inter-module signals .irq_o(rv_plic_irq), @@ -2190,7 +2262,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); aes #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]), .AES192Enable(1'b1), .SecMasking(SecAesMasking), .SecSBoxImpl(SecAesSBoxImpl), @@ -2203,10 +2275,10 @@ module top_earlgrey #( .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm) ) u_aes ( - // [42]: recov_ctrl_update_err - // [43]: fatal_fault - .alert_tx_o ( alert_tx[43:42] ), - .alert_rx_i ( alert_rx[43:42] ), + // [43]: recov_ctrl_update_err + // [44]: fatal_fault + .alert_tx_o ( alert_tx[44:43] ), + .alert_rx_i ( alert_rx[44:43] ), // Inter-module signals .idle_o(clkmgr_aon_idle[0]), @@ -2225,16 +2297,16 @@ module top_earlgrey #( .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); hmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:45]) ) u_hmac ( // Interrupt .intr_hmac_done_o (intr_hmac_hmac_done), .intr_fifo_empty_o (intr_hmac_fifo_empty), .intr_hmac_err_o (intr_hmac_hmac_err), - // [44]: fatal_fault - .alert_tx_o ( alert_tx[44:44] ), - .alert_rx_i ( alert_rx[44:44] ), + // [45]: fatal_fault + .alert_tx_o ( alert_tx[45:45] ), + .alert_rx_i ( alert_rx[45:45] ), // Inter-module signals .idle_o(clkmgr_aon_idle[1]), @@ -2246,7 +2318,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); kmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:46]), .EnMasking(KmacEnMasking), .SwKeyMasked(KmacSwKeyMasked), .SecCmdDelay(SecKmacCmdDelay), @@ -2261,10 +2333,10 @@ module top_earlgrey #( .intr_kmac_done_o (intr_kmac_kmac_done), .intr_fifo_empty_o (intr_kmac_fifo_empty), .intr_kmac_err_o (intr_kmac_kmac_err), - // [45]: recov_operation_err - // [46]: fatal_fault_err - .alert_tx_o ( alert_tx[46:45] ), - .alert_rx_i ( alert_rx[46:45] ), + // [46]: recov_operation_err + // [47]: fatal_fault_err + .alert_tx_o ( alert_tx[47:46] ), + .alert_rx_i ( alert_rx[47:46] ), // Inter-module signals .keymgr_key_i(keymgr_kmac_key), @@ -2286,7 +2358,7 @@ module top_earlgrey #( .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48]), .Stub(OtbnStub), .RegFile(OtbnRegFile), .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed), @@ -2298,10 +2370,10 @@ module top_earlgrey #( // Interrupt .intr_done_o (intr_otbn_done), - // [47]: fatal - // [48]: recov - .alert_tx_o ( alert_tx[48:47] ), - .alert_rx_i ( alert_rx[48:47] ), + // [48]: fatal + // [49]: recov + .alert_tx_o ( alert_tx[49:48] ), + .alert_rx_i ( alert_rx[49:48] ), // Inter-module signals .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), @@ -2328,7 +2400,7 @@ module top_earlgrey #( .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); keymgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:50]), .UseOtpSeedsInsteadOfFlash(KeymgrUseOtpSeedsInsteadOfFlash), .KmacEnMasking(KeymgrKmacEnMasking), .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed), @@ -2349,10 +2421,10 @@ module top_earlgrey #( // Interrupt .intr_op_done_o (intr_keymgr_op_done), - // [49]: recov_operation_err - // [50]: fatal_fault_err - .alert_tx_o ( alert_tx[50:49] ), - .alert_rx_i ( alert_rx[50:49] ), + // [50]: recov_operation_err + // [51]: fatal_fault_err + .alert_tx_o ( alert_tx[51:50] ), + .alert_rx_i ( alert_rx[51:50] ), // Inter-module signals .edn_o(edn0_edn_req[0]), @@ -2380,7 +2452,7 @@ module top_earlgrey #( .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); csrng #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:52]), .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), .SBoxImpl(CsrngSBoxImpl) @@ -2391,10 +2463,10 @@ module top_earlgrey #( .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), - // [51]: recov_alert - // [52]: fatal_alert - .alert_tx_o ( alert_tx[52:51] ), - .alert_rx_i ( alert_rx[52:51] ), + // [52]: recov_alert + // [53]: fatal_alert + .alert_tx_o ( alert_tx[53:52] ), + .alert_rx_i ( alert_rx[53:52] ), // Inter-module signals .csrng_cmd_i(csrng_csrng_cmd_req), @@ -2413,7 +2485,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); entropy_src #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:54]), .EsFifoDepth(EntropySrcEsFifoDepth), .Stub(EntropySrcStub) ) u_entropy_src ( @@ -2423,10 +2495,10 @@ module top_earlgrey #( .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed), .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready), .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), - // [53]: recov_alert - // [54]: fatal_alert - .alert_tx_o ( alert_tx[54:53] ), - .alert_rx_i ( alert_rx[54:53] ), + // [54]: recov_alert + // [55]: fatal_alert + .alert_tx_o ( alert_tx[55:54] ), + .alert_rx_i ( alert_rx[55:54] ), // Inter-module signals .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), @@ -2448,16 +2520,16 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:56]) ) u_edn0 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), - // [55]: recov_alert - // [56]: fatal_alert - .alert_tx_o ( alert_tx[56:55] ), - .alert_rx_i ( alert_rx[56:55] ), + // [56]: recov_alert + // [57]: fatal_alert + .alert_tx_o ( alert_tx[57:56] ), + .alert_rx_i ( alert_rx[57:56] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[0]), @@ -2472,16 +2544,16 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:57]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:58]) ) u_edn1 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), - // [57]: recov_alert - // [58]: fatal_alert - .alert_tx_o ( alert_tx[58:57] ), - .alert_rx_i ( alert_rx[58:57] ), + // [58]: recov_alert + // [59]: fatal_alert + .alert_tx_o ( alert_tx[59:58] ), + .alert_rx_i ( alert_rx[59:58] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[1]), @@ -2496,7 +2568,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:59]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]), .RndCnstSramKey(RndCnstSramCtrlMainSramKey), .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), @@ -2504,9 +2576,9 @@ module top_earlgrey #( .MemSizeRam(131072), .InstrExec(SramCtrlMainInstrExec) ) u_sram_ctrl_main ( - // [59]: fatal_error - .alert_tx_o ( alert_tx[59:59] ), - .alert_rx_i ( alert_rx[59:59] ), + // [60]: fatal_error + .alert_tx_o ( alert_tx[60:60] ), + .alert_rx_i ( alert_rx[60:60] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), @@ -2527,15 +2599,15 @@ module top_earlgrey #( .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); rom_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:61]), .BootRomInitFile(RomCtrlBootRomInitFile), .RndCnstScrNonce(RndCnstRomCtrlScrNonce), .RndCnstScrKey(RndCnstRomCtrlScrKey), .SecDisableScrambling(SecRomCtrlDisableScrambling) ) u_rom_ctrl ( - // [60]: fatal - .alert_tx_o ( alert_tx[60:60] ), - .alert_rx_i ( alert_rx[60:60] ), + // [61]: fatal + .alert_tx_o ( alert_tx[61:61] ), + .alert_rx_i ( alert_rx[61:61] ), // Inter-module signals .rom_cfg_i(ast_rom_cfg), @@ -2553,7 +2625,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); rv_core_ibex #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64:61]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[65:62]), .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed), .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm), .RndCnstIbexKeyDefault(RndCnstRvCoreIbexIbexKeyDefault), @@ -2580,12 +2652,12 @@ module top_earlgrey #( .DmExceptionAddr(RvCoreIbexDmExceptionAddr), .PipeLine(RvCoreIbexPipeLine) ) u_rv_core_ibex ( - // [61]: fatal_sw_err - // [62]: recov_sw_err - // [63]: fatal_hw_err - // [64]: recov_hw_err - .alert_tx_o ( alert_tx[64:61] ), - .alert_rx_i ( alert_rx[64:61] ), + // [62]: fatal_sw_err + // [63]: recov_sw_err + // [64]: fatal_hw_err + // [65]: recov_hw_err + .alert_tx_o ( alert_tx[65:62] ), + .alert_rx_i ( alert_rx[65:62] ), // Inter-module signals .rst_cpu_n_o(), @@ -2629,70 +2701,85 @@ module top_earlgrey #( ); // interrupt assignments assign intr_vector = { - intr_edn1_edn_fatal_err, // IDs [181 +: 1] - intr_edn1_edn_cmd_req_done, // IDs [180 +: 1] - intr_edn0_edn_fatal_err, // IDs [179 +: 1] - intr_edn0_edn_cmd_req_done, // IDs [178 +: 1] - intr_entropy_src_es_fatal_err, // IDs [177 +: 1] - intr_entropy_src_es_observe_fifo_ready, // IDs [176 +: 1] - intr_entropy_src_es_health_test_failed, // IDs [175 +: 1] - intr_entropy_src_es_entropy_valid, // IDs [174 +: 1] - intr_csrng_cs_fatal_err, // IDs [173 +: 1] - intr_csrng_cs_hw_inst_exc, // IDs [172 +: 1] - intr_csrng_cs_entropy_req, // IDs [171 +: 1] - intr_csrng_cs_cmd_req_done, // IDs [170 +: 1] - intr_keymgr_op_done, // IDs [169 +: 1] - intr_otbn_done, // IDs [168 +: 1] - intr_kmac_kmac_err, // IDs [167 +: 1] - intr_kmac_fifo_empty, // IDs [166 +: 1] - intr_kmac_kmac_done, // IDs [165 +: 1] - intr_hmac_hmac_err, // IDs [164 +: 1] - intr_hmac_fifo_empty, // IDs [163 +: 1] - intr_hmac_hmac_done, // IDs [162 +: 1] - intr_flash_ctrl_corr_err, // IDs [161 +: 1] - intr_flash_ctrl_op_done, // IDs [160 +: 1] - intr_flash_ctrl_rd_lvl, // IDs [159 +: 1] - intr_flash_ctrl_rd_full, // IDs [158 +: 1] - intr_flash_ctrl_prog_lvl, // IDs [157 +: 1] - intr_flash_ctrl_prog_empty, // IDs [156 +: 1] - intr_sensor_ctrl_aon_init_status_change, // IDs [155 +: 1] - intr_sensor_ctrl_aon_io_status_change, // IDs [154 +: 1] - intr_aon_timer_aon_wdog_timer_bark, // IDs [153 +: 1] - intr_aon_timer_aon_wkup_timer_expired, // IDs [152 +: 1] - intr_adc_ctrl_aon_match_done, // IDs [151 +: 1] - intr_sysrst_ctrl_aon_event_detected, // IDs [150 +: 1] - intr_pwrmgr_aon_wakeup, // IDs [149 +: 1] - intr_usbdev_av_setup_empty, // IDs [148 +: 1] - intr_usbdev_link_out_err, // IDs [147 +: 1] - intr_usbdev_powered, // IDs [146 +: 1] - intr_usbdev_frame, // IDs [145 +: 1] - intr_usbdev_rx_bitstuff_err, // IDs [144 +: 1] - intr_usbdev_rx_pid_err, // IDs [143 +: 1] - intr_usbdev_rx_crc_err, // IDs [142 +: 1] - intr_usbdev_link_in_err, // IDs [141 +: 1] - intr_usbdev_av_overflow, // IDs [140 +: 1] - intr_usbdev_rx_full, // IDs [139 +: 1] - intr_usbdev_av_out_empty, // IDs [138 +: 1] - intr_usbdev_link_resume, // IDs [137 +: 1] - intr_usbdev_link_suspend, // IDs [136 +: 1] - intr_usbdev_link_reset, // IDs [135 +: 1] - intr_usbdev_host_lost, // IDs [134 +: 1] - intr_usbdev_disconnected, // IDs [133 +: 1] - intr_usbdev_pkt_sent, // IDs [132 +: 1] - intr_usbdev_pkt_received, // IDs [131 +: 1] - intr_spi_host1_spi_event, // IDs [130 +: 1] - intr_spi_host1_error, // IDs [129 +: 1] - intr_spi_host0_spi_event, // IDs [128 +: 1] - intr_spi_host0_error, // IDs [127 +: 1] - intr_alert_handler_classd, // IDs [126 +: 1] - intr_alert_handler_classc, // IDs [125 +: 1] - intr_alert_handler_classb, // IDs [124 +: 1] - intr_alert_handler_classa, // IDs [123 +: 1] - intr_otp_ctrl_otp_error, // IDs [122 +: 1] - intr_otp_ctrl_otp_operation_done, // IDs [121 +: 1] - intr_rv_timer_timer_expired_hart0_timer0, // IDs [120 +: 1] - intr_pattgen_done_ch1, // IDs [119 +: 1] - intr_pattgen_done_ch0, // IDs [118 +: 1] + intr_edn1_edn_fatal_err, // IDs [196 +: 1] + intr_edn1_edn_cmd_req_done, // IDs [195 +: 1] + intr_edn0_edn_fatal_err, // IDs [194 +: 1] + intr_edn0_edn_cmd_req_done, // IDs [193 +: 1] + intr_entropy_src_es_fatal_err, // IDs [192 +: 1] + intr_entropy_src_es_observe_fifo_ready, // IDs [191 +: 1] + intr_entropy_src_es_health_test_failed, // IDs [190 +: 1] + intr_entropy_src_es_entropy_valid, // IDs [189 +: 1] + intr_csrng_cs_fatal_err, // IDs [188 +: 1] + intr_csrng_cs_hw_inst_exc, // IDs [187 +: 1] + intr_csrng_cs_entropy_req, // IDs [186 +: 1] + intr_csrng_cs_cmd_req_done, // IDs [185 +: 1] + intr_keymgr_op_done, // IDs [184 +: 1] + intr_otbn_done, // IDs [183 +: 1] + intr_kmac_kmac_err, // IDs [182 +: 1] + intr_kmac_fifo_empty, // IDs [181 +: 1] + intr_kmac_kmac_done, // IDs [180 +: 1] + intr_hmac_hmac_err, // IDs [179 +: 1] + intr_hmac_fifo_empty, // IDs [178 +: 1] + intr_hmac_hmac_done, // IDs [177 +: 1] + intr_flash_ctrl_corr_err, // IDs [176 +: 1] + intr_flash_ctrl_op_done, // IDs [175 +: 1] + intr_flash_ctrl_rd_lvl, // IDs [174 +: 1] + intr_flash_ctrl_rd_full, // IDs [173 +: 1] + intr_flash_ctrl_prog_lvl, // IDs [172 +: 1] + intr_flash_ctrl_prog_empty, // IDs [171 +: 1] + intr_sensor_ctrl_aon_init_status_change, // IDs [170 +: 1] + intr_sensor_ctrl_aon_io_status_change, // IDs [169 +: 1] + intr_aon_timer_aon_wdog_timer_bark, // IDs [168 +: 1] + intr_aon_timer_aon_wkup_timer_expired, // IDs [167 +: 1] + intr_adc_ctrl_aon_match_done, // IDs [166 +: 1] + intr_sysrst_ctrl_aon_event_detected, // IDs [165 +: 1] + intr_pwrmgr_aon_wakeup, // IDs [164 +: 1] + intr_usbdev_av_setup_empty, // IDs [163 +: 1] + intr_usbdev_link_out_err, // IDs [162 +: 1] + intr_usbdev_powered, // IDs [161 +: 1] + intr_usbdev_frame, // IDs [160 +: 1] + intr_usbdev_rx_bitstuff_err, // IDs [159 +: 1] + intr_usbdev_rx_pid_err, // IDs [158 +: 1] + intr_usbdev_rx_crc_err, // IDs [157 +: 1] + intr_usbdev_link_in_err, // IDs [156 +: 1] + intr_usbdev_av_overflow, // IDs [155 +: 1] + intr_usbdev_rx_full, // IDs [154 +: 1] + intr_usbdev_av_out_empty, // IDs [153 +: 1] + intr_usbdev_link_resume, // IDs [152 +: 1] + intr_usbdev_link_suspend, // IDs [151 +: 1] + intr_usbdev_link_reset, // IDs [150 +: 1] + intr_usbdev_host_lost, // IDs [149 +: 1] + intr_usbdev_disconnected, // IDs [148 +: 1] + intr_usbdev_pkt_sent, // IDs [147 +: 1] + intr_usbdev_pkt_received, // IDs [146 +: 1] + intr_spi_host1_spi_event, // IDs [145 +: 1] + intr_spi_host1_error, // IDs [144 +: 1] + intr_spi_host0_spi_event, // IDs [143 +: 1] + intr_spi_host0_error, // IDs [142 +: 1] + intr_alert_handler_classd, // IDs [141 +: 1] + intr_alert_handler_classc, // IDs [140 +: 1] + intr_alert_handler_classb, // IDs [139 +: 1] + intr_alert_handler_classa, // IDs [138 +: 1] + intr_otp_ctrl_otp_error, // IDs [137 +: 1] + intr_otp_ctrl_otp_operation_done, // IDs [136 +: 1] + intr_rv_timer_timer_expired_hart0_timer0, // IDs [135 +: 1] + intr_pattgen_done_ch1, // IDs [134 +: 1] + intr_pattgen_done_ch0, // IDs [133 +: 1] + intr_i2c3_host_timeout, // IDs [132 +: 1] + intr_i2c3_unexp_stop, // IDs [131 +: 1] + intr_i2c3_acq_full, // IDs [130 +: 1] + intr_i2c3_tx_overflow, // IDs [129 +: 1] + intr_i2c3_tx_stretch, // IDs [128 +: 1] + intr_i2c3_cmd_complete, // IDs [127 +: 1] + intr_i2c3_sda_unstable, // IDs [126 +: 1] + intr_i2c3_stretch_timeout, // IDs [125 +: 1] + intr_i2c3_sda_interference, // IDs [124 +: 1] + intr_i2c3_scl_interference, // IDs [123 +: 1] + intr_i2c3_nak, // IDs [122 +: 1] + intr_i2c3_rx_overflow, // IDs [121 +: 1] + intr_i2c3_fmt_overflow, // IDs [120 +: 1] + intr_i2c3_rx_threshold, // IDs [119 +: 1] + intr_i2c3_fmt_threshold, // IDs [118 +: 1] intr_i2c2_host_timeout, // IDs [117 +: 1] intr_i2c2_unexp_stop, // IDs [116 +: 1] intr_i2c2_acq_full, // IDs [115 +: 1] @@ -2942,6 +3029,10 @@ module top_earlgrey #( .tl_i2c2_o(i2c2_tl_req), .tl_i2c2_i(i2c2_tl_rsp), + // port: tl_i2c3 + .tl_i2c3_o(i2c3_tl_req), + .tl_i2c3_i(i2c3_tl_rsp), + // port: tl_pattgen .tl_pattgen_o(pattgen_tl_req), .tl_pattgen_i(pattgen_tl_rsp), @@ -3066,6 +3157,8 @@ module top_earlgrey #( assign cio_i2c1_scl_p2d = mio_p2d[MioInI2c1Scl]; assign cio_i2c2_sda_p2d = mio_p2d[MioInI2c2Sda]; assign cio_i2c2_scl_p2d = mio_p2d[MioInI2c2Scl]; + assign cio_i2c3_sda_p2d = mio_p2d[MioInI2c3Sda]; + assign cio_i2c3_scl_p2d = mio_p2d[MioInI2c3Scl]; assign cio_spi_host1_sd_p2d[0] = mio_p2d[MioInSpiHost1Sd0]; assign cio_spi_host1_sd_p2d[1] = mio_p2d[MioInSpiHost1Sd1]; assign cio_spi_host1_sd_p2d[2] = mio_p2d[MioInSpiHost1Sd2]; @@ -3125,6 +3218,8 @@ module top_earlgrey #( assign mio_d2p[MioOutI2c1Scl] = cio_i2c1_scl_d2p; assign mio_d2p[MioOutI2c2Sda] = cio_i2c2_sda_d2p; assign mio_d2p[MioOutI2c2Scl] = cio_i2c2_scl_d2p; + assign mio_d2p[MioOutI2c3Sda] = cio_i2c3_sda_d2p; + assign mio_d2p[MioOutI2c3Scl] = cio_i2c3_scl_d2p; assign mio_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_d2p[0]; assign mio_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_d2p[1]; assign mio_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_d2p[2]; @@ -3202,6 +3297,8 @@ module top_earlgrey #( assign mio_en_d2p[MioOutI2c1Scl] = cio_i2c1_scl_en_d2p; assign mio_en_d2p[MioOutI2c2Sda] = cio_i2c2_sda_en_d2p; assign mio_en_d2p[MioOutI2c2Scl] = cio_i2c2_scl_en_d2p; + assign mio_en_d2p[MioOutI2c3Sda] = cio_i2c3_sda_en_d2p; + assign mio_en_d2p[MioOutI2c3Scl] = cio_i2c3_scl_en_d2p; assign mio_en_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_en_d2p[0]; assign mio_en_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_en_d2p[1]; assign mio_en_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_en_d2p[2]; diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index d03a33c2c425e2..bdcd67ae66fda7 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -101,6 +101,16 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_I2C2_SIZE_BYTES = 32'h80; + /** + * Peripheral base address for i2c3 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C3_BASE_ADDR = 32'h400B0000; + + /** + * Peripheral size in bytes for i2c3 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C3_SIZE_BYTES = 32'h80; + /** * Peripheral base address for pattgen in top earlgrey. */ @@ -563,38 +573,39 @@ package top_earlgrey_pkg; TopEarlgreyAlertPeripheralI2c0 = 6, TopEarlgreyAlertPeripheralI2c1 = 7, TopEarlgreyAlertPeripheralI2c2 = 8, - TopEarlgreyAlertPeripheralPattgen = 9, - TopEarlgreyAlertPeripheralRvTimer = 10, - TopEarlgreyAlertPeripheralOtpCtrl = 11, - TopEarlgreyAlertPeripheralLcCtrl = 12, - TopEarlgreyAlertPeripheralSpiHost0 = 13, - TopEarlgreyAlertPeripheralSpiHost1 = 14, - TopEarlgreyAlertPeripheralUsbdev = 15, - TopEarlgreyAlertPeripheralPwrmgrAon = 16, - TopEarlgreyAlertPeripheralRstmgrAon = 17, - TopEarlgreyAlertPeripheralClkmgrAon = 18, - TopEarlgreyAlertPeripheralSysrstCtrlAon = 19, - TopEarlgreyAlertPeripheralAdcCtrlAon = 20, - TopEarlgreyAlertPeripheralPwmAon = 21, - TopEarlgreyAlertPeripheralPinmuxAon = 22, - TopEarlgreyAlertPeripheralAonTimerAon = 23, - TopEarlgreyAlertPeripheralSensorCtrlAon = 24, - TopEarlgreyAlertPeripheralSramCtrlRetAon = 25, - TopEarlgreyAlertPeripheralFlashCtrl = 26, - TopEarlgreyAlertPeripheralRvDm = 27, - TopEarlgreyAlertPeripheralRvPlic = 28, - TopEarlgreyAlertPeripheralAes = 29, - TopEarlgreyAlertPeripheralHmac = 30, - TopEarlgreyAlertPeripheralKmac = 31, - TopEarlgreyAlertPeripheralOtbn = 32, - TopEarlgreyAlertPeripheralKeymgr = 33, - TopEarlgreyAlertPeripheralCsrng = 34, - TopEarlgreyAlertPeripheralEntropySrc = 35, - TopEarlgreyAlertPeripheralEdn0 = 36, - TopEarlgreyAlertPeripheralEdn1 = 37, - TopEarlgreyAlertPeripheralSramCtrlMain = 38, - TopEarlgreyAlertPeripheralRomCtrl = 39, - TopEarlgreyAlertPeripheralRvCoreIbex = 40, + TopEarlgreyAlertPeripheralI2c3 = 9, + TopEarlgreyAlertPeripheralPattgen = 10, + TopEarlgreyAlertPeripheralRvTimer = 11, + TopEarlgreyAlertPeripheralOtpCtrl = 12, + TopEarlgreyAlertPeripheralLcCtrl = 13, + TopEarlgreyAlertPeripheralSpiHost0 = 14, + TopEarlgreyAlertPeripheralSpiHost1 = 15, + TopEarlgreyAlertPeripheralUsbdev = 16, + TopEarlgreyAlertPeripheralPwrmgrAon = 17, + TopEarlgreyAlertPeripheralRstmgrAon = 18, + TopEarlgreyAlertPeripheralClkmgrAon = 19, + TopEarlgreyAlertPeripheralSysrstCtrlAon = 20, + TopEarlgreyAlertPeripheralAdcCtrlAon = 21, + TopEarlgreyAlertPeripheralPwmAon = 22, + TopEarlgreyAlertPeripheralPinmuxAon = 23, + TopEarlgreyAlertPeripheralAonTimerAon = 24, + TopEarlgreyAlertPeripheralSensorCtrlAon = 25, + TopEarlgreyAlertPeripheralSramCtrlRetAon = 26, + TopEarlgreyAlertPeripheralFlashCtrl = 27, + TopEarlgreyAlertPeripheralRvDm = 28, + TopEarlgreyAlertPeripheralRvPlic = 29, + TopEarlgreyAlertPeripheralAes = 30, + TopEarlgreyAlertPeripheralHmac = 31, + TopEarlgreyAlertPeripheralKmac = 32, + TopEarlgreyAlertPeripheralOtbn = 33, + TopEarlgreyAlertPeripheralKeymgr = 34, + TopEarlgreyAlertPeripheralCsrng = 35, + TopEarlgreyAlertPeripheralEntropySrc = 36, + TopEarlgreyAlertPeripheralEdn0 = 37, + TopEarlgreyAlertPeripheralEdn1 = 38, + TopEarlgreyAlertPeripheralSramCtrlMain = 39, + TopEarlgreyAlertPeripheralRomCtrl = 40, + TopEarlgreyAlertPeripheralRvCoreIbex = 41, TopEarlgreyAlertPeripheralCount } alert_peripheral_e; @@ -609,62 +620,63 @@ package top_earlgrey_pkg; TopEarlgreyAlertIdI2c0FatalFault = 6, TopEarlgreyAlertIdI2c1FatalFault = 7, TopEarlgreyAlertIdI2c2FatalFault = 8, - TopEarlgreyAlertIdPattgenFatalFault = 9, - TopEarlgreyAlertIdRvTimerFatalFault = 10, - TopEarlgreyAlertIdOtpCtrlFatalMacroError = 11, - TopEarlgreyAlertIdOtpCtrlFatalCheckError = 12, - TopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 13, - TopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 14, - TopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 15, - TopEarlgreyAlertIdLcCtrlFatalProgError = 16, - TopEarlgreyAlertIdLcCtrlFatalStateError = 17, - TopEarlgreyAlertIdLcCtrlFatalBusIntegError = 18, - TopEarlgreyAlertIdSpiHost0FatalFault = 19, - TopEarlgreyAlertIdSpiHost1FatalFault = 20, - TopEarlgreyAlertIdUsbdevFatalFault = 21, - TopEarlgreyAlertIdPwrmgrAonFatalFault = 22, - TopEarlgreyAlertIdRstmgrAonFatalFault = 23, - TopEarlgreyAlertIdRstmgrAonFatalCnstyFault = 24, - TopEarlgreyAlertIdClkmgrAonRecovFault = 25, - TopEarlgreyAlertIdClkmgrAonFatalFault = 26, - TopEarlgreyAlertIdSysrstCtrlAonFatalFault = 27, - TopEarlgreyAlertIdAdcCtrlAonFatalFault = 28, - TopEarlgreyAlertIdPwmAonFatalFault = 29, - TopEarlgreyAlertIdPinmuxAonFatalFault = 30, - TopEarlgreyAlertIdAonTimerAonFatalFault = 31, - TopEarlgreyAlertIdSensorCtrlAonRecovAlert = 32, - TopEarlgreyAlertIdSensorCtrlAonFatalAlert = 33, - TopEarlgreyAlertIdSramCtrlRetAonFatalError = 34, - TopEarlgreyAlertIdFlashCtrlRecovErr = 35, - TopEarlgreyAlertIdFlashCtrlFatalStdErr = 36, - TopEarlgreyAlertIdFlashCtrlFatalErr = 37, - TopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 38, - TopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 39, - TopEarlgreyAlertIdRvDmFatalFault = 40, - TopEarlgreyAlertIdRvPlicFatalFault = 41, - TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 42, - TopEarlgreyAlertIdAesFatalFault = 43, - TopEarlgreyAlertIdHmacFatalFault = 44, - TopEarlgreyAlertIdKmacRecovOperationErr = 45, - TopEarlgreyAlertIdKmacFatalFaultErr = 46, - TopEarlgreyAlertIdOtbnFatal = 47, - TopEarlgreyAlertIdOtbnRecov = 48, - TopEarlgreyAlertIdKeymgrRecovOperationErr = 49, - TopEarlgreyAlertIdKeymgrFatalFaultErr = 50, - TopEarlgreyAlertIdCsrngRecovAlert = 51, - TopEarlgreyAlertIdCsrngFatalAlert = 52, - TopEarlgreyAlertIdEntropySrcRecovAlert = 53, - TopEarlgreyAlertIdEntropySrcFatalAlert = 54, - TopEarlgreyAlertIdEdn0RecovAlert = 55, - TopEarlgreyAlertIdEdn0FatalAlert = 56, - TopEarlgreyAlertIdEdn1RecovAlert = 57, - TopEarlgreyAlertIdEdn1FatalAlert = 58, - TopEarlgreyAlertIdSramCtrlMainFatalError = 59, - TopEarlgreyAlertIdRomCtrlFatal = 60, - TopEarlgreyAlertIdRvCoreIbexFatalSwErr = 61, - TopEarlgreyAlertIdRvCoreIbexRecovSwErr = 62, - TopEarlgreyAlertIdRvCoreIbexFatalHwErr = 63, - TopEarlgreyAlertIdRvCoreIbexRecovHwErr = 64, + TopEarlgreyAlertIdI2c3FatalFault = 9, + TopEarlgreyAlertIdPattgenFatalFault = 10, + TopEarlgreyAlertIdRvTimerFatalFault = 11, + TopEarlgreyAlertIdOtpCtrlFatalMacroError = 12, + TopEarlgreyAlertIdOtpCtrlFatalCheckError = 13, + TopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 14, + TopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 15, + TopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 16, + TopEarlgreyAlertIdLcCtrlFatalProgError = 17, + TopEarlgreyAlertIdLcCtrlFatalStateError = 18, + TopEarlgreyAlertIdLcCtrlFatalBusIntegError = 19, + TopEarlgreyAlertIdSpiHost0FatalFault = 20, + TopEarlgreyAlertIdSpiHost1FatalFault = 21, + TopEarlgreyAlertIdUsbdevFatalFault = 22, + TopEarlgreyAlertIdPwrmgrAonFatalFault = 23, + TopEarlgreyAlertIdRstmgrAonFatalFault = 24, + TopEarlgreyAlertIdRstmgrAonFatalCnstyFault = 25, + TopEarlgreyAlertIdClkmgrAonRecovFault = 26, + TopEarlgreyAlertIdClkmgrAonFatalFault = 27, + TopEarlgreyAlertIdSysrstCtrlAonFatalFault = 28, + TopEarlgreyAlertIdAdcCtrlAonFatalFault = 29, + TopEarlgreyAlertIdPwmAonFatalFault = 30, + TopEarlgreyAlertIdPinmuxAonFatalFault = 31, + TopEarlgreyAlertIdAonTimerAonFatalFault = 32, + TopEarlgreyAlertIdSensorCtrlAonRecovAlert = 33, + TopEarlgreyAlertIdSensorCtrlAonFatalAlert = 34, + TopEarlgreyAlertIdSramCtrlRetAonFatalError = 35, + TopEarlgreyAlertIdFlashCtrlRecovErr = 36, + TopEarlgreyAlertIdFlashCtrlFatalStdErr = 37, + TopEarlgreyAlertIdFlashCtrlFatalErr = 38, + TopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 39, + TopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 40, + TopEarlgreyAlertIdRvDmFatalFault = 41, + TopEarlgreyAlertIdRvPlicFatalFault = 42, + TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 43, + TopEarlgreyAlertIdAesFatalFault = 44, + TopEarlgreyAlertIdHmacFatalFault = 45, + TopEarlgreyAlertIdKmacRecovOperationErr = 46, + TopEarlgreyAlertIdKmacFatalFaultErr = 47, + TopEarlgreyAlertIdOtbnFatal = 48, + TopEarlgreyAlertIdOtbnRecov = 49, + TopEarlgreyAlertIdKeymgrRecovOperationErr = 50, + TopEarlgreyAlertIdKeymgrFatalFaultErr = 51, + TopEarlgreyAlertIdCsrngRecovAlert = 52, + TopEarlgreyAlertIdCsrngFatalAlert = 53, + TopEarlgreyAlertIdEntropySrcRecovAlert = 54, + TopEarlgreyAlertIdEntropySrcFatalAlert = 55, + TopEarlgreyAlertIdEdn0RecovAlert = 56, + TopEarlgreyAlertIdEdn0FatalAlert = 57, + TopEarlgreyAlertIdEdn1RecovAlert = 58, + TopEarlgreyAlertIdEdn1FatalAlert = 59, + TopEarlgreyAlertIdSramCtrlMainFatalError = 60, + TopEarlgreyAlertIdRomCtrlFatal = 61, + TopEarlgreyAlertIdRvCoreIbexFatalSwErr = 62, + TopEarlgreyAlertIdRvCoreIbexRecovSwErr = 63, + TopEarlgreyAlertIdRvCoreIbexFatalHwErr = 64, + TopEarlgreyAlertIdRvCoreIbexRecovHwErr = 65, TopEarlgreyAlertIdCount } alert_id_e; @@ -718,26 +730,28 @@ package top_earlgrey_pkg; MioInI2c1Scl = 35, MioInI2c2Sda = 36, MioInI2c2Scl = 37, - MioInSpiHost1Sd0 = 38, - MioInSpiHost1Sd1 = 39, - MioInSpiHost1Sd2 = 40, - MioInSpiHost1Sd3 = 41, - MioInUart0Rx = 42, - MioInUart1Rx = 43, - MioInUart2Rx = 44, - MioInUart3Rx = 45, - MioInSpiDeviceTpmCsb = 46, - MioInFlashCtrlTck = 47, - MioInFlashCtrlTms = 48, - MioInFlashCtrlTdi = 49, - MioInSysrstCtrlAonAcPresent = 50, - MioInSysrstCtrlAonKey0In = 51, - MioInSysrstCtrlAonKey1In = 52, - MioInSysrstCtrlAonKey2In = 53, - MioInSysrstCtrlAonPwrbIn = 54, - MioInSysrstCtrlAonLidOpen = 55, - MioInUsbdevSense = 56, - MioInCount = 57 + MioInI2c3Sda = 38, + MioInI2c3Scl = 39, + MioInSpiHost1Sd0 = 40, + MioInSpiHost1Sd1 = 41, + MioInSpiHost1Sd2 = 42, + MioInSpiHost1Sd3 = 43, + MioInUart0Rx = 44, + MioInUart1Rx = 45, + MioInUart2Rx = 46, + MioInUart3Rx = 47, + MioInSpiDeviceTpmCsb = 48, + MioInFlashCtrlTck = 49, + MioInFlashCtrlTms = 50, + MioInFlashCtrlTdi = 51, + MioInSysrstCtrlAonAcPresent = 52, + MioInSysrstCtrlAonKey0In = 53, + MioInSysrstCtrlAonKey1In = 54, + MioInSysrstCtrlAonKey2In = 55, + MioInSysrstCtrlAonPwrbIn = 56, + MioInSysrstCtrlAonLidOpen = 57, + MioInUsbdevSense = 58, + MioInCount = 59 } mio_in_e; typedef enum { @@ -779,44 +793,46 @@ package top_earlgrey_pkg; MioOutI2c1Scl = 35, MioOutI2c2Sda = 36, MioOutI2c2Scl = 37, - MioOutSpiHost1Sd0 = 38, - MioOutSpiHost1Sd1 = 39, - MioOutSpiHost1Sd2 = 40, - MioOutSpiHost1Sd3 = 41, - MioOutUart0Tx = 42, - MioOutUart1Tx = 43, - MioOutUart2Tx = 44, - MioOutUart3Tx = 45, - MioOutPattgenPda0Tx = 46, - MioOutPattgenPcl0Tx = 47, - MioOutPattgenPda1Tx = 48, - MioOutPattgenPcl1Tx = 49, - MioOutSpiHost1Sck = 50, - MioOutSpiHost1Csb = 51, - MioOutFlashCtrlTdo = 52, - MioOutSensorCtrlAonAstDebugOut0 = 53, - MioOutSensorCtrlAonAstDebugOut1 = 54, - MioOutSensorCtrlAonAstDebugOut2 = 55, - MioOutSensorCtrlAonAstDebugOut3 = 56, - MioOutSensorCtrlAonAstDebugOut4 = 57, - MioOutSensorCtrlAonAstDebugOut5 = 58, - MioOutSensorCtrlAonAstDebugOut6 = 59, - MioOutSensorCtrlAonAstDebugOut7 = 60, - MioOutSensorCtrlAonAstDebugOut8 = 61, - MioOutPwmAonPwm0 = 62, - MioOutPwmAonPwm1 = 63, - MioOutPwmAonPwm2 = 64, - MioOutPwmAonPwm3 = 65, - MioOutPwmAonPwm4 = 66, - MioOutPwmAonPwm5 = 67, - MioOutOtpCtrlTest0 = 68, - MioOutSysrstCtrlAonBatDisable = 69, - MioOutSysrstCtrlAonKey0Out = 70, - MioOutSysrstCtrlAonKey1Out = 71, - MioOutSysrstCtrlAonKey2Out = 72, - MioOutSysrstCtrlAonPwrbOut = 73, - MioOutSysrstCtrlAonZ3Wakeup = 74, - MioOutCount = 75 + MioOutI2c3Sda = 38, + MioOutI2c3Scl = 39, + MioOutSpiHost1Sd0 = 40, + MioOutSpiHost1Sd1 = 41, + MioOutSpiHost1Sd2 = 42, + MioOutSpiHost1Sd3 = 43, + MioOutUart0Tx = 44, + MioOutUart1Tx = 45, + MioOutUart2Tx = 46, + MioOutUart3Tx = 47, + MioOutPattgenPda0Tx = 48, + MioOutPattgenPcl0Tx = 49, + MioOutPattgenPda1Tx = 50, + MioOutPattgenPcl1Tx = 51, + MioOutSpiHost1Sck = 52, + MioOutSpiHost1Csb = 53, + MioOutFlashCtrlTdo = 54, + MioOutSensorCtrlAonAstDebugOut0 = 55, + MioOutSensorCtrlAonAstDebugOut1 = 56, + MioOutSensorCtrlAonAstDebugOut2 = 57, + MioOutSensorCtrlAonAstDebugOut3 = 58, + MioOutSensorCtrlAonAstDebugOut4 = 59, + MioOutSensorCtrlAonAstDebugOut5 = 60, + MioOutSensorCtrlAonAstDebugOut6 = 61, + MioOutSensorCtrlAonAstDebugOut7 = 62, + MioOutSensorCtrlAonAstDebugOut8 = 63, + MioOutPwmAonPwm0 = 64, + MioOutPwmAonPwm1 = 65, + MioOutPwmAonPwm2 = 66, + MioOutPwmAonPwm3 = 67, + MioOutPwmAonPwm4 = 68, + MioOutPwmAonPwm5 = 69, + MioOutOtpCtrlTest0 = 70, + MioOutSysrstCtrlAonBatDisable = 71, + MioOutSysrstCtrlAonKey0Out = 72, + MioOutSysrstCtrlAonKey1Out = 73, + MioOutSysrstCtrlAonKey2Out = 74, + MioOutSysrstCtrlAonPwrbOut = 75, + MioOutSysrstCtrlAonZ3Wakeup = 76, + MioOutCount = 77 } mio_out_e; // Enumeration for DIO signals, used on both the top and chip-levels. @@ -945,6 +961,7 @@ package top_earlgrey_pkg; PeripheralI2c0, PeripheralI2c1, PeripheralI2c2, + PeripheralI2c3, PeripheralKeymgr, PeripheralKmac, PeripheralLcCtrl, diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index a98cf5852e9d82..bfb06fff7b69a3 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -147,6 +147,20 @@ pub const I2C2_BASE_ADDR: usize = 0x400A0000; /// `I2C2_BASE_ADDR + I2C2_SIZE_BYTES`. pub const I2C2_SIZE_BYTES: usize = 0x80; +/// Peripheral base address for i2c3 in top earlgrey. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const I2C3_BASE_ADDR: usize = 0x400B0000; + +/// Peripheral size for i2c3 in top earlgrey. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #I2C3_BASE_ADDR and +/// `I2C3_BASE_ADDR + I2C3_SIZE_BYTES`. +pub const I2C3_SIZE_BYTES: usize = 0x80; + /// Peripheral base address for pattgen in top earlgrey. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped @@ -772,48 +786,50 @@ pub enum PlicPeripheral { I2c1 = 8, /// i2c2 I2c2 = 9, + /// i2c3 + I2c3 = 10, /// pattgen - Pattgen = 10, + Pattgen = 11, /// rv_timer - RvTimer = 11, + RvTimer = 12, /// otp_ctrl - OtpCtrl = 12, + OtpCtrl = 13, /// alert_handler - AlertHandler = 13, + AlertHandler = 14, /// spi_host0 - SpiHost0 = 14, + SpiHost0 = 15, /// spi_host1 - SpiHost1 = 15, + SpiHost1 = 16, /// usbdev - Usbdev = 16, + Usbdev = 17, /// pwrmgr_aon - PwrmgrAon = 17, + PwrmgrAon = 18, /// sysrst_ctrl_aon - SysrstCtrlAon = 18, + SysrstCtrlAon = 19, /// adc_ctrl_aon - AdcCtrlAon = 19, + AdcCtrlAon = 20, /// aon_timer_aon - AonTimerAon = 20, + AonTimerAon = 21, /// sensor_ctrl_aon - SensorCtrlAon = 21, + SensorCtrlAon = 22, /// flash_ctrl - FlashCtrl = 22, + FlashCtrl = 23, /// hmac - Hmac = 23, + Hmac = 24, /// kmac - Kmac = 24, + Kmac = 25, /// otbn - Otbn = 25, + Otbn = 26, /// keymgr - Keymgr = 26, + Keymgr = 27, /// csrng - Csrng = 27, + Csrng = 28, /// entropy_src - EntropySrc = 28, + EntropySrc = 29, /// edn0 - Edn0 = 29, + Edn0 = 30, /// edn1 - Edn1 = 30, + Edn1 = 31, } impl TryFrom for PlicPeripheral { @@ -830,27 +846,28 @@ impl TryFrom for PlicPeripheral { 7 => Ok(Self::I2c0), 8 => Ok(Self::I2c1), 9 => Ok(Self::I2c2), - 10 => Ok(Self::Pattgen), - 11 => Ok(Self::RvTimer), - 12 => Ok(Self::OtpCtrl), - 13 => Ok(Self::AlertHandler), - 14 => Ok(Self::SpiHost0), - 15 => Ok(Self::SpiHost1), - 16 => Ok(Self::Usbdev), - 17 => Ok(Self::PwrmgrAon), - 18 => Ok(Self::SysrstCtrlAon), - 19 => Ok(Self::AdcCtrlAon), - 20 => Ok(Self::AonTimerAon), - 21 => Ok(Self::SensorCtrlAon), - 22 => Ok(Self::FlashCtrl), - 23 => Ok(Self::Hmac), - 24 => Ok(Self::Kmac), - 25 => Ok(Self::Otbn), - 26 => Ok(Self::Keymgr), - 27 => Ok(Self::Csrng), - 28 => Ok(Self::EntropySrc), - 29 => Ok(Self::Edn0), - 30 => Ok(Self::Edn1), + 10 => Ok(Self::I2c3), + 11 => Ok(Self::Pattgen), + 12 => Ok(Self::RvTimer), + 13 => Ok(Self::OtpCtrl), + 14 => Ok(Self::AlertHandler), + 15 => Ok(Self::SpiHost0), + 16 => Ok(Self::SpiHost1), + 17 => Ok(Self::Usbdev), + 18 => Ok(Self::PwrmgrAon), + 19 => Ok(Self::SysrstCtrlAon), + 20 => Ok(Self::AdcCtrlAon), + 21 => Ok(Self::AonTimerAon), + 22 => Ok(Self::SensorCtrlAon), + 23 => Ok(Self::FlashCtrl), + 24 => Ok(Self::Hmac), + 25 => Ok(Self::Kmac), + 26 => Ok(Self::Otbn), + 27 => Ok(Self::Keymgr), + 28 => Ok(Self::Csrng), + 29 => Ok(Self::EntropySrc), + 30 => Ok(Self::Edn0), + 31 => Ok(Self::Edn1), _ => Err(val), } } @@ -1099,134 +1116,164 @@ pub enum PlicIrqId { I2c2UnexpStop = 116, /// i2c2_host_timeout I2c2HostTimeout = 117, + /// i2c3_fmt_threshold + I2c3FmtThreshold = 118, + /// i2c3_rx_threshold + I2c3RxThreshold = 119, + /// i2c3_fmt_overflow + I2c3FmtOverflow = 120, + /// i2c3_rx_overflow + I2c3RxOverflow = 121, + /// i2c3_nak + I2c3Nak = 122, + /// i2c3_scl_interference + I2c3SclInterference = 123, + /// i2c3_sda_interference + I2c3SdaInterference = 124, + /// i2c3_stretch_timeout + I2c3StretchTimeout = 125, + /// i2c3_sda_unstable + I2c3SdaUnstable = 126, + /// i2c3_cmd_complete + I2c3CmdComplete = 127, + /// i2c3_tx_stretch + I2c3TxStretch = 128, + /// i2c3_tx_overflow + I2c3TxOverflow = 129, + /// i2c3_acq_full + I2c3AcqFull = 130, + /// i2c3_unexp_stop + I2c3UnexpStop = 131, + /// i2c3_host_timeout + I2c3HostTimeout = 132, /// pattgen_done_ch0 - PattgenDoneCh0 = 118, + PattgenDoneCh0 = 133, /// pattgen_done_ch1 - PattgenDoneCh1 = 119, + PattgenDoneCh1 = 134, /// rv_timer_timer_expired_hart0_timer0 - RvTimerTimerExpiredHart0Timer0 = 120, + RvTimerTimerExpiredHart0Timer0 = 135, /// otp_ctrl_otp_operation_done - OtpCtrlOtpOperationDone = 121, + OtpCtrlOtpOperationDone = 136, /// otp_ctrl_otp_error - OtpCtrlOtpError = 122, + OtpCtrlOtpError = 137, /// alert_handler_classa - AlertHandlerClassa = 123, + AlertHandlerClassa = 138, /// alert_handler_classb - AlertHandlerClassb = 124, + AlertHandlerClassb = 139, /// alert_handler_classc - AlertHandlerClassc = 125, + AlertHandlerClassc = 140, /// alert_handler_classd - AlertHandlerClassd = 126, + AlertHandlerClassd = 141, /// spi_host0_error - SpiHost0Error = 127, + SpiHost0Error = 142, /// spi_host0_spi_event - SpiHost0SpiEvent = 128, + SpiHost0SpiEvent = 143, /// spi_host1_error - SpiHost1Error = 129, + SpiHost1Error = 144, /// spi_host1_spi_event - SpiHost1SpiEvent = 130, + SpiHost1SpiEvent = 145, /// usbdev_pkt_received - UsbdevPktReceived = 131, + UsbdevPktReceived = 146, /// usbdev_pkt_sent - UsbdevPktSent = 132, + UsbdevPktSent = 147, /// usbdev_disconnected - UsbdevDisconnected = 133, + UsbdevDisconnected = 148, /// usbdev_host_lost - UsbdevHostLost = 134, + UsbdevHostLost = 149, /// usbdev_link_reset - UsbdevLinkReset = 135, + UsbdevLinkReset = 150, /// usbdev_link_suspend - UsbdevLinkSuspend = 136, + UsbdevLinkSuspend = 151, /// usbdev_link_resume - UsbdevLinkResume = 137, + UsbdevLinkResume = 152, /// usbdev_av_out_empty - UsbdevAvOutEmpty = 138, + UsbdevAvOutEmpty = 153, /// usbdev_rx_full - UsbdevRxFull = 139, + UsbdevRxFull = 154, /// usbdev_av_overflow - UsbdevAvOverflow = 140, + UsbdevAvOverflow = 155, /// usbdev_link_in_err - UsbdevLinkInErr = 141, + UsbdevLinkInErr = 156, /// usbdev_rx_crc_err - UsbdevRxCrcErr = 142, + UsbdevRxCrcErr = 157, /// usbdev_rx_pid_err - UsbdevRxPidErr = 143, + UsbdevRxPidErr = 158, /// usbdev_rx_bitstuff_err - UsbdevRxBitstuffErr = 144, + UsbdevRxBitstuffErr = 159, /// usbdev_frame - UsbdevFrame = 145, + UsbdevFrame = 160, /// usbdev_powered - UsbdevPowered = 146, + UsbdevPowered = 161, /// usbdev_link_out_err - UsbdevLinkOutErr = 147, + UsbdevLinkOutErr = 162, /// usbdev_av_setup_empty - UsbdevAvSetupEmpty = 148, + UsbdevAvSetupEmpty = 163, /// pwrmgr_aon_wakeup - PwrmgrAonWakeup = 149, + PwrmgrAonWakeup = 164, /// sysrst_ctrl_aon_event_detected - SysrstCtrlAonEventDetected = 150, + SysrstCtrlAonEventDetected = 165, /// adc_ctrl_aon_match_done - AdcCtrlAonMatchDone = 151, + AdcCtrlAonMatchDone = 166, /// aon_timer_aon_wkup_timer_expired - AonTimerAonWkupTimerExpired = 152, + AonTimerAonWkupTimerExpired = 167, /// aon_timer_aon_wdog_timer_bark - AonTimerAonWdogTimerBark = 153, + AonTimerAonWdogTimerBark = 168, /// sensor_ctrl_aon_io_status_change - SensorCtrlAonIoStatusChange = 154, + SensorCtrlAonIoStatusChange = 169, /// sensor_ctrl_aon_init_status_change - SensorCtrlAonInitStatusChange = 155, + SensorCtrlAonInitStatusChange = 170, /// flash_ctrl_prog_empty - FlashCtrlProgEmpty = 156, + FlashCtrlProgEmpty = 171, /// flash_ctrl_prog_lvl - FlashCtrlProgLvl = 157, + FlashCtrlProgLvl = 172, /// flash_ctrl_rd_full - FlashCtrlRdFull = 158, + FlashCtrlRdFull = 173, /// flash_ctrl_rd_lvl - FlashCtrlRdLvl = 159, + FlashCtrlRdLvl = 174, /// flash_ctrl_op_done - FlashCtrlOpDone = 160, + FlashCtrlOpDone = 175, /// flash_ctrl_corr_err - FlashCtrlCorrErr = 161, + FlashCtrlCorrErr = 176, /// hmac_hmac_done - HmacHmacDone = 162, + HmacHmacDone = 177, /// hmac_fifo_empty - HmacFifoEmpty = 163, + HmacFifoEmpty = 178, /// hmac_hmac_err - HmacHmacErr = 164, + HmacHmacErr = 179, /// kmac_kmac_done - KmacKmacDone = 165, + KmacKmacDone = 180, /// kmac_fifo_empty - KmacFifoEmpty = 166, + KmacFifoEmpty = 181, /// kmac_kmac_err - KmacKmacErr = 167, + KmacKmacErr = 182, /// otbn_done - OtbnDone = 168, + OtbnDone = 183, /// keymgr_op_done - KeymgrOpDone = 169, + KeymgrOpDone = 184, /// csrng_cs_cmd_req_done - CsrngCsCmdReqDone = 170, + CsrngCsCmdReqDone = 185, /// csrng_cs_entropy_req - CsrngCsEntropyReq = 171, + CsrngCsEntropyReq = 186, /// csrng_cs_hw_inst_exc - CsrngCsHwInstExc = 172, + CsrngCsHwInstExc = 187, /// csrng_cs_fatal_err - CsrngCsFatalErr = 173, + CsrngCsFatalErr = 188, /// entropy_src_es_entropy_valid - EntropySrcEsEntropyValid = 174, + EntropySrcEsEntropyValid = 189, /// entropy_src_es_health_test_failed - EntropySrcEsHealthTestFailed = 175, + EntropySrcEsHealthTestFailed = 190, /// entropy_src_es_observe_fifo_ready - EntropySrcEsObserveFifoReady = 176, + EntropySrcEsObserveFifoReady = 191, /// entropy_src_es_fatal_err - EntropySrcEsFatalErr = 177, + EntropySrcEsFatalErr = 192, /// edn0_edn_cmd_req_done - Edn0EdnCmdReqDone = 178, + Edn0EdnCmdReqDone = 193, /// edn0_edn_fatal_err - Edn0EdnFatalErr = 179, + Edn0EdnFatalErr = 194, /// edn1_edn_cmd_req_done - Edn1EdnCmdReqDone = 180, + Edn1EdnCmdReqDone = 195, /// edn1_edn_fatal_err - Edn1EdnFatalErr = 181, + Edn1EdnFatalErr = 196, } impl TryFrom for PlicIrqId { @@ -1351,70 +1398,85 @@ impl TryFrom for PlicIrqId { 115 => Ok(Self::I2c2AcqFull), 116 => Ok(Self::I2c2UnexpStop), 117 => Ok(Self::I2c2HostTimeout), - 118 => Ok(Self::PattgenDoneCh0), - 119 => Ok(Self::PattgenDoneCh1), - 120 => Ok(Self::RvTimerTimerExpiredHart0Timer0), - 121 => Ok(Self::OtpCtrlOtpOperationDone), - 122 => Ok(Self::OtpCtrlOtpError), - 123 => Ok(Self::AlertHandlerClassa), - 124 => Ok(Self::AlertHandlerClassb), - 125 => Ok(Self::AlertHandlerClassc), - 126 => Ok(Self::AlertHandlerClassd), - 127 => Ok(Self::SpiHost0Error), - 128 => Ok(Self::SpiHost0SpiEvent), - 129 => Ok(Self::SpiHost1Error), - 130 => Ok(Self::SpiHost1SpiEvent), - 131 => Ok(Self::UsbdevPktReceived), - 132 => Ok(Self::UsbdevPktSent), - 133 => Ok(Self::UsbdevDisconnected), - 134 => Ok(Self::UsbdevHostLost), - 135 => Ok(Self::UsbdevLinkReset), - 136 => Ok(Self::UsbdevLinkSuspend), - 137 => Ok(Self::UsbdevLinkResume), - 138 => Ok(Self::UsbdevAvOutEmpty), - 139 => Ok(Self::UsbdevRxFull), - 140 => Ok(Self::UsbdevAvOverflow), - 141 => Ok(Self::UsbdevLinkInErr), - 142 => Ok(Self::UsbdevRxCrcErr), - 143 => Ok(Self::UsbdevRxPidErr), - 144 => Ok(Self::UsbdevRxBitstuffErr), - 145 => Ok(Self::UsbdevFrame), - 146 => Ok(Self::UsbdevPowered), - 147 => Ok(Self::UsbdevLinkOutErr), - 148 => Ok(Self::UsbdevAvSetupEmpty), - 149 => Ok(Self::PwrmgrAonWakeup), - 150 => Ok(Self::SysrstCtrlAonEventDetected), - 151 => Ok(Self::AdcCtrlAonMatchDone), - 152 => Ok(Self::AonTimerAonWkupTimerExpired), - 153 => Ok(Self::AonTimerAonWdogTimerBark), - 154 => Ok(Self::SensorCtrlAonIoStatusChange), - 155 => Ok(Self::SensorCtrlAonInitStatusChange), - 156 => Ok(Self::FlashCtrlProgEmpty), - 157 => Ok(Self::FlashCtrlProgLvl), - 158 => Ok(Self::FlashCtrlRdFull), - 159 => Ok(Self::FlashCtrlRdLvl), - 160 => Ok(Self::FlashCtrlOpDone), - 161 => Ok(Self::FlashCtrlCorrErr), - 162 => Ok(Self::HmacHmacDone), - 163 => Ok(Self::HmacFifoEmpty), - 164 => Ok(Self::HmacHmacErr), - 165 => Ok(Self::KmacKmacDone), - 166 => Ok(Self::KmacFifoEmpty), - 167 => Ok(Self::KmacKmacErr), - 168 => Ok(Self::OtbnDone), - 169 => Ok(Self::KeymgrOpDone), - 170 => Ok(Self::CsrngCsCmdReqDone), - 171 => Ok(Self::CsrngCsEntropyReq), - 172 => Ok(Self::CsrngCsHwInstExc), - 173 => Ok(Self::CsrngCsFatalErr), - 174 => Ok(Self::EntropySrcEsEntropyValid), - 175 => Ok(Self::EntropySrcEsHealthTestFailed), - 176 => Ok(Self::EntropySrcEsObserveFifoReady), - 177 => Ok(Self::EntropySrcEsFatalErr), - 178 => Ok(Self::Edn0EdnCmdReqDone), - 179 => Ok(Self::Edn0EdnFatalErr), - 180 => Ok(Self::Edn1EdnCmdReqDone), - 181 => Ok(Self::Edn1EdnFatalErr), + 118 => Ok(Self::I2c3FmtThreshold), + 119 => Ok(Self::I2c3RxThreshold), + 120 => Ok(Self::I2c3FmtOverflow), + 121 => Ok(Self::I2c3RxOverflow), + 122 => Ok(Self::I2c3Nak), + 123 => Ok(Self::I2c3SclInterference), + 124 => Ok(Self::I2c3SdaInterference), + 125 => Ok(Self::I2c3StretchTimeout), + 126 => Ok(Self::I2c3SdaUnstable), + 127 => Ok(Self::I2c3CmdComplete), + 128 => Ok(Self::I2c3TxStretch), + 129 => Ok(Self::I2c3TxOverflow), + 130 => Ok(Self::I2c3AcqFull), + 131 => Ok(Self::I2c3UnexpStop), + 132 => Ok(Self::I2c3HostTimeout), + 133 => Ok(Self::PattgenDoneCh0), + 134 => Ok(Self::PattgenDoneCh1), + 135 => Ok(Self::RvTimerTimerExpiredHart0Timer0), + 136 => Ok(Self::OtpCtrlOtpOperationDone), + 137 => Ok(Self::OtpCtrlOtpError), + 138 => Ok(Self::AlertHandlerClassa), + 139 => Ok(Self::AlertHandlerClassb), + 140 => Ok(Self::AlertHandlerClassc), + 141 => Ok(Self::AlertHandlerClassd), + 142 => Ok(Self::SpiHost0Error), + 143 => Ok(Self::SpiHost0SpiEvent), + 144 => Ok(Self::SpiHost1Error), + 145 => Ok(Self::SpiHost1SpiEvent), + 146 => Ok(Self::UsbdevPktReceived), + 147 => Ok(Self::UsbdevPktSent), + 148 => Ok(Self::UsbdevDisconnected), + 149 => Ok(Self::UsbdevHostLost), + 150 => Ok(Self::UsbdevLinkReset), + 151 => Ok(Self::UsbdevLinkSuspend), + 152 => Ok(Self::UsbdevLinkResume), + 153 => Ok(Self::UsbdevAvOutEmpty), + 154 => Ok(Self::UsbdevRxFull), + 155 => Ok(Self::UsbdevAvOverflow), + 156 => Ok(Self::UsbdevLinkInErr), + 157 => Ok(Self::UsbdevRxCrcErr), + 158 => Ok(Self::UsbdevRxPidErr), + 159 => Ok(Self::UsbdevRxBitstuffErr), + 160 => Ok(Self::UsbdevFrame), + 161 => Ok(Self::UsbdevPowered), + 162 => Ok(Self::UsbdevLinkOutErr), + 163 => Ok(Self::UsbdevAvSetupEmpty), + 164 => Ok(Self::PwrmgrAonWakeup), + 165 => Ok(Self::SysrstCtrlAonEventDetected), + 166 => Ok(Self::AdcCtrlAonMatchDone), + 167 => Ok(Self::AonTimerAonWkupTimerExpired), + 168 => Ok(Self::AonTimerAonWdogTimerBark), + 169 => Ok(Self::SensorCtrlAonIoStatusChange), + 170 => Ok(Self::SensorCtrlAonInitStatusChange), + 171 => Ok(Self::FlashCtrlProgEmpty), + 172 => Ok(Self::FlashCtrlProgLvl), + 173 => Ok(Self::FlashCtrlRdFull), + 174 => Ok(Self::FlashCtrlRdLvl), + 175 => Ok(Self::FlashCtrlOpDone), + 176 => Ok(Self::FlashCtrlCorrErr), + 177 => Ok(Self::HmacHmacDone), + 178 => Ok(Self::HmacFifoEmpty), + 179 => Ok(Self::HmacHmacErr), + 180 => Ok(Self::KmacKmacDone), + 181 => Ok(Self::KmacFifoEmpty), + 182 => Ok(Self::KmacKmacErr), + 183 => Ok(Self::OtbnDone), + 184 => Ok(Self::KeymgrOpDone), + 185 => Ok(Self::CsrngCsCmdReqDone), + 186 => Ok(Self::CsrngCsEntropyReq), + 187 => Ok(Self::CsrngCsHwInstExc), + 188 => Ok(Self::CsrngCsFatalErr), + 189 => Ok(Self::EntropySrcEsEntropyValid), + 190 => Ok(Self::EntropySrcEsHealthTestFailed), + 191 => Ok(Self::EntropySrcEsObserveFifoReady), + 192 => Ok(Self::EntropySrcEsFatalErr), + 193 => Ok(Self::Edn0EdnCmdReqDone), + 194 => Ok(Self::Edn0EdnFatalErr), + 195 => Ok(Self::Edn1EdnCmdReqDone), + 196 => Ok(Self::Edn1EdnFatalErr), _ => Err(val), } } @@ -1456,70 +1518,72 @@ pub enum AlertPeripheral { I2c1 = 7, /// i2c2 I2c2 = 8, + /// i2c3 + I2c3 = 9, /// pattgen - Pattgen = 9, + Pattgen = 10, /// rv_timer - RvTimer = 10, + RvTimer = 11, /// otp_ctrl - OtpCtrl = 11, + OtpCtrl = 12, /// lc_ctrl - LcCtrl = 12, + LcCtrl = 13, /// spi_host0 - SpiHost0 = 13, + SpiHost0 = 14, /// spi_host1 - SpiHost1 = 14, + SpiHost1 = 15, /// usbdev - Usbdev = 15, + Usbdev = 16, /// pwrmgr_aon - PwrmgrAon = 16, + PwrmgrAon = 17, /// rstmgr_aon - RstmgrAon = 17, + RstmgrAon = 18, /// clkmgr_aon - ClkmgrAon = 18, + ClkmgrAon = 19, /// sysrst_ctrl_aon - SysrstCtrlAon = 19, + SysrstCtrlAon = 20, /// adc_ctrl_aon - AdcCtrlAon = 20, + AdcCtrlAon = 21, /// pwm_aon - PwmAon = 21, + PwmAon = 22, /// pinmux_aon - PinmuxAon = 22, + PinmuxAon = 23, /// aon_timer_aon - AonTimerAon = 23, + AonTimerAon = 24, /// sensor_ctrl_aon - SensorCtrlAon = 24, + SensorCtrlAon = 25, /// sram_ctrl_ret_aon - SramCtrlRetAon = 25, + SramCtrlRetAon = 26, /// flash_ctrl - FlashCtrl = 26, + FlashCtrl = 27, /// rv_dm - RvDm = 27, + RvDm = 28, /// rv_plic - RvPlic = 28, + RvPlic = 29, /// aes - Aes = 29, + Aes = 30, /// hmac - Hmac = 30, + Hmac = 31, /// kmac - Kmac = 31, + Kmac = 32, /// otbn - Otbn = 32, + Otbn = 33, /// keymgr - Keymgr = 33, + Keymgr = 34, /// csrng - Csrng = 34, + Csrng = 35, /// entropy_src - EntropySrc = 35, + EntropySrc = 36, /// edn0 - Edn0 = 36, + Edn0 = 37, /// edn1 - Edn1 = 37, + Edn1 = 38, /// sram_ctrl_main - SramCtrlMain = 38, + SramCtrlMain = 39, /// rom_ctrl - RomCtrl = 39, + RomCtrl = 40, /// rv_core_ibex - RvCoreIbex = 40, + RvCoreIbex = 41, } /// Alert Handler Alert Source. @@ -1547,118 +1611,120 @@ pub enum AlertId { I2c1FatalFault = 7, /// i2c2_fatal_fault I2c2FatalFault = 8, + /// i2c3_fatal_fault + I2c3FatalFault = 9, /// pattgen_fatal_fault - PattgenFatalFault = 9, + PattgenFatalFault = 10, /// rv_timer_fatal_fault - RvTimerFatalFault = 10, + RvTimerFatalFault = 11, /// otp_ctrl_fatal_macro_error - OtpCtrlFatalMacroError = 11, + OtpCtrlFatalMacroError = 12, /// otp_ctrl_fatal_check_error - OtpCtrlFatalCheckError = 12, + OtpCtrlFatalCheckError = 13, /// otp_ctrl_fatal_bus_integ_error - OtpCtrlFatalBusIntegError = 13, + OtpCtrlFatalBusIntegError = 14, /// otp_ctrl_fatal_prim_otp_alert - OtpCtrlFatalPrimOtpAlert = 14, + OtpCtrlFatalPrimOtpAlert = 15, /// otp_ctrl_recov_prim_otp_alert - OtpCtrlRecovPrimOtpAlert = 15, + OtpCtrlRecovPrimOtpAlert = 16, /// lc_ctrl_fatal_prog_error - LcCtrlFatalProgError = 16, + LcCtrlFatalProgError = 17, /// lc_ctrl_fatal_state_error - LcCtrlFatalStateError = 17, + LcCtrlFatalStateError = 18, /// lc_ctrl_fatal_bus_integ_error - LcCtrlFatalBusIntegError = 18, + LcCtrlFatalBusIntegError = 19, /// spi_host0_fatal_fault - SpiHost0FatalFault = 19, + SpiHost0FatalFault = 20, /// spi_host1_fatal_fault - SpiHost1FatalFault = 20, + SpiHost1FatalFault = 21, /// usbdev_fatal_fault - UsbdevFatalFault = 21, + UsbdevFatalFault = 22, /// pwrmgr_aon_fatal_fault - PwrmgrAonFatalFault = 22, + PwrmgrAonFatalFault = 23, /// rstmgr_aon_fatal_fault - RstmgrAonFatalFault = 23, + RstmgrAonFatalFault = 24, /// rstmgr_aon_fatal_cnsty_fault - RstmgrAonFatalCnstyFault = 24, + RstmgrAonFatalCnstyFault = 25, /// clkmgr_aon_recov_fault - ClkmgrAonRecovFault = 25, + ClkmgrAonRecovFault = 26, /// clkmgr_aon_fatal_fault - ClkmgrAonFatalFault = 26, + ClkmgrAonFatalFault = 27, /// sysrst_ctrl_aon_fatal_fault - SysrstCtrlAonFatalFault = 27, + SysrstCtrlAonFatalFault = 28, /// adc_ctrl_aon_fatal_fault - AdcCtrlAonFatalFault = 28, + AdcCtrlAonFatalFault = 29, /// pwm_aon_fatal_fault - PwmAonFatalFault = 29, + PwmAonFatalFault = 30, /// pinmux_aon_fatal_fault - PinmuxAonFatalFault = 30, + PinmuxAonFatalFault = 31, /// aon_timer_aon_fatal_fault - AonTimerAonFatalFault = 31, + AonTimerAonFatalFault = 32, /// sensor_ctrl_aon_recov_alert - SensorCtrlAonRecovAlert = 32, + SensorCtrlAonRecovAlert = 33, /// sensor_ctrl_aon_fatal_alert - SensorCtrlAonFatalAlert = 33, + SensorCtrlAonFatalAlert = 34, /// sram_ctrl_ret_aon_fatal_error - SramCtrlRetAonFatalError = 34, + SramCtrlRetAonFatalError = 35, /// flash_ctrl_recov_err - FlashCtrlRecovErr = 35, + FlashCtrlRecovErr = 36, /// flash_ctrl_fatal_std_err - FlashCtrlFatalStdErr = 36, + FlashCtrlFatalStdErr = 37, /// flash_ctrl_fatal_err - FlashCtrlFatalErr = 37, + FlashCtrlFatalErr = 38, /// flash_ctrl_fatal_prim_flash_alert - FlashCtrlFatalPrimFlashAlert = 38, + FlashCtrlFatalPrimFlashAlert = 39, /// flash_ctrl_recov_prim_flash_alert - FlashCtrlRecovPrimFlashAlert = 39, + FlashCtrlRecovPrimFlashAlert = 40, /// rv_dm_fatal_fault - RvDmFatalFault = 40, + RvDmFatalFault = 41, /// rv_plic_fatal_fault - RvPlicFatalFault = 41, + RvPlicFatalFault = 42, /// aes_recov_ctrl_update_err - AesRecovCtrlUpdateErr = 42, + AesRecovCtrlUpdateErr = 43, /// aes_fatal_fault - AesFatalFault = 43, + AesFatalFault = 44, /// hmac_fatal_fault - HmacFatalFault = 44, + HmacFatalFault = 45, /// kmac_recov_operation_err - KmacRecovOperationErr = 45, + KmacRecovOperationErr = 46, /// kmac_fatal_fault_err - KmacFatalFaultErr = 46, + KmacFatalFaultErr = 47, /// otbn_fatal - OtbnFatal = 47, + OtbnFatal = 48, /// otbn_recov - OtbnRecov = 48, + OtbnRecov = 49, /// keymgr_recov_operation_err - KeymgrRecovOperationErr = 49, + KeymgrRecovOperationErr = 50, /// keymgr_fatal_fault_err - KeymgrFatalFaultErr = 50, + KeymgrFatalFaultErr = 51, /// csrng_recov_alert - CsrngRecovAlert = 51, + CsrngRecovAlert = 52, /// csrng_fatal_alert - CsrngFatalAlert = 52, + CsrngFatalAlert = 53, /// entropy_src_recov_alert - EntropySrcRecovAlert = 53, + EntropySrcRecovAlert = 54, /// entropy_src_fatal_alert - EntropySrcFatalAlert = 54, + EntropySrcFatalAlert = 55, /// edn0_recov_alert - Edn0RecovAlert = 55, + Edn0RecovAlert = 56, /// edn0_fatal_alert - Edn0FatalAlert = 56, + Edn0FatalAlert = 57, /// edn1_recov_alert - Edn1RecovAlert = 57, + Edn1RecovAlert = 58, /// edn1_fatal_alert - Edn1FatalAlert = 58, + Edn1FatalAlert = 59, /// sram_ctrl_main_fatal_error - SramCtrlMainFatalError = 59, + SramCtrlMainFatalError = 60, /// rom_ctrl_fatal - RomCtrlFatal = 60, + RomCtrlFatal = 61, /// rv_core_ibex_fatal_sw_err - RvCoreIbexFatalSwErr = 61, + RvCoreIbexFatalSwErr = 62, /// rv_core_ibex_recov_sw_err - RvCoreIbexRecovSwErr = 62, + RvCoreIbexRecovSwErr = 63, /// rv_core_ibex_fatal_hw_err - RvCoreIbexFatalHwErr = 63, + RvCoreIbexFatalHwErr = 64, /// rv_core_ibex_recov_hw_err - RvCoreIbexRecovHwErr = 64, + RvCoreIbexRecovHwErr = 65, } impl TryFrom for AlertId { @@ -1674,62 +1740,63 @@ impl TryFrom for AlertId { 6 => Ok(Self::I2c0FatalFault), 7 => Ok(Self::I2c1FatalFault), 8 => Ok(Self::I2c2FatalFault), - 9 => Ok(Self::PattgenFatalFault), - 10 => Ok(Self::RvTimerFatalFault), - 11 => Ok(Self::OtpCtrlFatalMacroError), - 12 => Ok(Self::OtpCtrlFatalCheckError), - 13 => Ok(Self::OtpCtrlFatalBusIntegError), - 14 => Ok(Self::OtpCtrlFatalPrimOtpAlert), - 15 => Ok(Self::OtpCtrlRecovPrimOtpAlert), - 16 => Ok(Self::LcCtrlFatalProgError), - 17 => Ok(Self::LcCtrlFatalStateError), - 18 => Ok(Self::LcCtrlFatalBusIntegError), - 19 => Ok(Self::SpiHost0FatalFault), - 20 => Ok(Self::SpiHost1FatalFault), - 21 => Ok(Self::UsbdevFatalFault), - 22 => Ok(Self::PwrmgrAonFatalFault), - 23 => Ok(Self::RstmgrAonFatalFault), - 24 => Ok(Self::RstmgrAonFatalCnstyFault), - 25 => Ok(Self::ClkmgrAonRecovFault), - 26 => Ok(Self::ClkmgrAonFatalFault), - 27 => Ok(Self::SysrstCtrlAonFatalFault), - 28 => Ok(Self::AdcCtrlAonFatalFault), - 29 => Ok(Self::PwmAonFatalFault), - 30 => Ok(Self::PinmuxAonFatalFault), - 31 => Ok(Self::AonTimerAonFatalFault), - 32 => Ok(Self::SensorCtrlAonRecovAlert), - 33 => Ok(Self::SensorCtrlAonFatalAlert), - 34 => Ok(Self::SramCtrlRetAonFatalError), - 35 => Ok(Self::FlashCtrlRecovErr), - 36 => Ok(Self::FlashCtrlFatalStdErr), - 37 => Ok(Self::FlashCtrlFatalErr), - 38 => Ok(Self::FlashCtrlFatalPrimFlashAlert), - 39 => Ok(Self::FlashCtrlRecovPrimFlashAlert), - 40 => Ok(Self::RvDmFatalFault), - 41 => Ok(Self::RvPlicFatalFault), - 42 => Ok(Self::AesRecovCtrlUpdateErr), - 43 => Ok(Self::AesFatalFault), - 44 => Ok(Self::HmacFatalFault), - 45 => Ok(Self::KmacRecovOperationErr), - 46 => Ok(Self::KmacFatalFaultErr), - 47 => Ok(Self::OtbnFatal), - 48 => Ok(Self::OtbnRecov), - 49 => Ok(Self::KeymgrRecovOperationErr), - 50 => Ok(Self::KeymgrFatalFaultErr), - 51 => Ok(Self::CsrngRecovAlert), - 52 => Ok(Self::CsrngFatalAlert), - 53 => Ok(Self::EntropySrcRecovAlert), - 54 => Ok(Self::EntropySrcFatalAlert), - 55 => Ok(Self::Edn0RecovAlert), - 56 => Ok(Self::Edn0FatalAlert), - 57 => Ok(Self::Edn1RecovAlert), - 58 => Ok(Self::Edn1FatalAlert), - 59 => Ok(Self::SramCtrlMainFatalError), - 60 => Ok(Self::RomCtrlFatal), - 61 => Ok(Self::RvCoreIbexFatalSwErr), - 62 => Ok(Self::RvCoreIbexRecovSwErr), - 63 => Ok(Self::RvCoreIbexFatalHwErr), - 64 => Ok(Self::RvCoreIbexRecovHwErr), + 9 => Ok(Self::I2c3FatalFault), + 10 => Ok(Self::PattgenFatalFault), + 11 => Ok(Self::RvTimerFatalFault), + 12 => Ok(Self::OtpCtrlFatalMacroError), + 13 => Ok(Self::OtpCtrlFatalCheckError), + 14 => Ok(Self::OtpCtrlFatalBusIntegError), + 15 => Ok(Self::OtpCtrlFatalPrimOtpAlert), + 16 => Ok(Self::OtpCtrlRecovPrimOtpAlert), + 17 => Ok(Self::LcCtrlFatalProgError), + 18 => Ok(Self::LcCtrlFatalStateError), + 19 => Ok(Self::LcCtrlFatalBusIntegError), + 20 => Ok(Self::SpiHost0FatalFault), + 21 => Ok(Self::SpiHost1FatalFault), + 22 => Ok(Self::UsbdevFatalFault), + 23 => Ok(Self::PwrmgrAonFatalFault), + 24 => Ok(Self::RstmgrAonFatalFault), + 25 => Ok(Self::RstmgrAonFatalCnstyFault), + 26 => Ok(Self::ClkmgrAonRecovFault), + 27 => Ok(Self::ClkmgrAonFatalFault), + 28 => Ok(Self::SysrstCtrlAonFatalFault), + 29 => Ok(Self::AdcCtrlAonFatalFault), + 30 => Ok(Self::PwmAonFatalFault), + 31 => Ok(Self::PinmuxAonFatalFault), + 32 => Ok(Self::AonTimerAonFatalFault), + 33 => Ok(Self::SensorCtrlAonRecovAlert), + 34 => Ok(Self::SensorCtrlAonFatalAlert), + 35 => Ok(Self::SramCtrlRetAonFatalError), + 36 => Ok(Self::FlashCtrlRecovErr), + 37 => Ok(Self::FlashCtrlFatalStdErr), + 38 => Ok(Self::FlashCtrlFatalErr), + 39 => Ok(Self::FlashCtrlFatalPrimFlashAlert), + 40 => Ok(Self::FlashCtrlRecovPrimFlashAlert), + 41 => Ok(Self::RvDmFatalFault), + 42 => Ok(Self::RvPlicFatalFault), + 43 => Ok(Self::AesRecovCtrlUpdateErr), + 44 => Ok(Self::AesFatalFault), + 45 => Ok(Self::HmacFatalFault), + 46 => Ok(Self::KmacRecovOperationErr), + 47 => Ok(Self::KmacFatalFaultErr), + 48 => Ok(Self::OtbnFatal), + 49 => Ok(Self::OtbnRecov), + 50 => Ok(Self::KeymgrRecovOperationErr), + 51 => Ok(Self::KeymgrFatalFaultErr), + 52 => Ok(Self::CsrngRecovAlert), + 53 => Ok(Self::CsrngFatalAlert), + 54 => Ok(Self::EntropySrcRecovAlert), + 55 => Ok(Self::EntropySrcFatalAlert), + 56 => Ok(Self::Edn0RecovAlert), + 57 => Ok(Self::Edn0FatalAlert), + 58 => Ok(Self::Edn1RecovAlert), + 59 => Ok(Self::Edn1FatalAlert), + 60 => Ok(Self::SramCtrlMainFatalError), + 61 => Ok(Self::RomCtrlFatal), + 62 => Ok(Self::RvCoreIbexFatalSwErr), + 63 => Ok(Self::RvCoreIbexRecovSwErr), + 64 => Ok(Self::RvCoreIbexFatalHwErr), + 65 => Ok(Self::RvCoreIbexRecovHwErr), _ => Err(val), } } @@ -1739,7 +1806,7 @@ impl TryFrom for AlertId { /// /// This array is a mapping from `PlicIrqId` to /// `PlicPeripheral`. -pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 182] = [ +pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 197] = [ // None -> PlicPeripheral::Unknown PlicPeripheral::Unknown, // Uart0TxWatermark -> PlicPeripheral::Uart0 @@ -1976,6 +2043,36 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 182] = [ PlicPeripheral::I2c2, // I2c2HostTimeout -> PlicPeripheral::I2c2 PlicPeripheral::I2c2, + // I2c3FmtThreshold -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3RxThreshold -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3FmtOverflow -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3RxOverflow -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3Nak -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3SclInterference -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3SdaInterference -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3StretchTimeout -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3SdaUnstable -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3CmdComplete -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3TxStretch -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3TxOverflow -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3AcqFull -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3UnexpStop -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, + // I2c3HostTimeout -> PlicPeripheral::I2c3 + PlicPeripheral::I2c3, // PattgenDoneCh0 -> PlicPeripheral::Pattgen PlicPeripheral::Pattgen, // PattgenDoneCh1 -> PlicPeripheral::Pattgen @@ -2110,7 +2207,7 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 182] = [ /// /// This array is a mapping from `AlertId` to /// `AlertPeripheral`. -pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 65] = [ +pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 66] = [ // Uart0FatalFault -> AlertPeripheral::Uart0 AlertPeripheral::Uart0, // Uart1FatalFault -> AlertPeripheral::Uart1 @@ -2129,6 +2226,8 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 65] = [ AlertPeripheral::I2c1, // I2c2FatalFault -> AlertPeripheral::I2c2 AlertPeripheral::I2c2, + // I2c3FatalFault -> AlertPeripheral::I2c3 + AlertPeripheral::I2c3, // PattgenFatalFault -> AlertPeripheral::Pattgen AlertPeripheral::Pattgen, // RvTimerFatalFault -> AlertPeripheral::RvTimer @@ -2332,43 +2431,47 @@ pub enum PinmuxPeripheralIn { /// Peripheral Input 37 I2c2Scl = 37, /// Peripheral Input 38 - SpiHost1Sd0 = 38, + I2c3Sda = 38, /// Peripheral Input 39 - SpiHost1Sd1 = 39, + I2c3Scl = 39, /// Peripheral Input 40 - SpiHost1Sd2 = 40, + SpiHost1Sd0 = 40, /// Peripheral Input 41 - SpiHost1Sd3 = 41, + SpiHost1Sd1 = 41, /// Peripheral Input 42 - Uart0Rx = 42, + SpiHost1Sd2 = 42, /// Peripheral Input 43 - Uart1Rx = 43, + SpiHost1Sd3 = 43, /// Peripheral Input 44 - Uart2Rx = 44, + Uart0Rx = 44, /// Peripheral Input 45 - Uart3Rx = 45, + Uart1Rx = 45, /// Peripheral Input 46 - SpiDeviceTpmCsb = 46, + Uart2Rx = 46, /// Peripheral Input 47 - FlashCtrlTck = 47, + Uart3Rx = 47, /// Peripheral Input 48 - FlashCtrlTms = 48, + SpiDeviceTpmCsb = 48, /// Peripheral Input 49 - FlashCtrlTdi = 49, + FlashCtrlTck = 49, /// Peripheral Input 50 - SysrstCtrlAonAcPresent = 50, + FlashCtrlTms = 50, /// Peripheral Input 51 - SysrstCtrlAonKey0In = 51, + FlashCtrlTdi = 51, /// Peripheral Input 52 - SysrstCtrlAonKey1In = 52, + SysrstCtrlAonAcPresent = 52, /// Peripheral Input 53 - SysrstCtrlAonKey2In = 53, + SysrstCtrlAonKey0In = 53, /// Peripheral Input 54 - SysrstCtrlAonPwrbIn = 54, + SysrstCtrlAonKey1In = 54, /// Peripheral Input 55 - SysrstCtrlAonLidOpen = 55, + SysrstCtrlAonKey2In = 55, /// Peripheral Input 56 - UsbdevSense = 56, + SysrstCtrlAonPwrbIn = 56, + /// Peripheral Input 57 + SysrstCtrlAonLidOpen = 57, + /// Peripheral Input 58 + UsbdevSense = 58, } impl TryFrom for PinmuxPeripheralIn { @@ -2413,25 +2516,27 @@ impl TryFrom for PinmuxPeripheralIn { 35 => Ok(Self::I2c1Scl), 36 => Ok(Self::I2c2Sda), 37 => Ok(Self::I2c2Scl), - 38 => Ok(Self::SpiHost1Sd0), - 39 => Ok(Self::SpiHost1Sd1), - 40 => Ok(Self::SpiHost1Sd2), - 41 => Ok(Self::SpiHost1Sd3), - 42 => Ok(Self::Uart0Rx), - 43 => Ok(Self::Uart1Rx), - 44 => Ok(Self::Uart2Rx), - 45 => Ok(Self::Uart3Rx), - 46 => Ok(Self::SpiDeviceTpmCsb), - 47 => Ok(Self::FlashCtrlTck), - 48 => Ok(Self::FlashCtrlTms), - 49 => Ok(Self::FlashCtrlTdi), - 50 => Ok(Self::SysrstCtrlAonAcPresent), - 51 => Ok(Self::SysrstCtrlAonKey0In), - 52 => Ok(Self::SysrstCtrlAonKey1In), - 53 => Ok(Self::SysrstCtrlAonKey2In), - 54 => Ok(Self::SysrstCtrlAonPwrbIn), - 55 => Ok(Self::SysrstCtrlAonLidOpen), - 56 => Ok(Self::UsbdevSense), + 38 => Ok(Self::I2c3Sda), + 39 => Ok(Self::I2c3Scl), + 40 => Ok(Self::SpiHost1Sd0), + 41 => Ok(Self::SpiHost1Sd1), + 42 => Ok(Self::SpiHost1Sd2), + 43 => Ok(Self::SpiHost1Sd3), + 44 => Ok(Self::Uart0Rx), + 45 => Ok(Self::Uart1Rx), + 46 => Ok(Self::Uart2Rx), + 47 => Ok(Self::Uart3Rx), + 48 => Ok(Self::SpiDeviceTpmCsb), + 49 => Ok(Self::FlashCtrlTck), + 50 => Ok(Self::FlashCtrlTms), + 51 => Ok(Self::FlashCtrlTdi), + 52 => Ok(Self::SysrstCtrlAonAcPresent), + 53 => Ok(Self::SysrstCtrlAonKey0In), + 54 => Ok(Self::SysrstCtrlAonKey1In), + 55 => Ok(Self::SysrstCtrlAonKey2In), + 56 => Ok(Self::SysrstCtrlAonPwrbIn), + 57 => Ok(Self::SysrstCtrlAonLidOpen), + 58 => Ok(Self::UsbdevSense), _ => Err(val), } } @@ -2842,79 +2947,83 @@ pub enum PinmuxOutsel { /// Peripheral Output 37 I2c2Scl = 40, /// Peripheral Output 38 - SpiHost1Sd0 = 41, + I2c3Sda = 41, /// Peripheral Output 39 - SpiHost1Sd1 = 42, + I2c3Scl = 42, /// Peripheral Output 40 - SpiHost1Sd2 = 43, + SpiHost1Sd0 = 43, /// Peripheral Output 41 - SpiHost1Sd3 = 44, + SpiHost1Sd1 = 44, /// Peripheral Output 42 - Uart0Tx = 45, + SpiHost1Sd2 = 45, /// Peripheral Output 43 - Uart1Tx = 46, + SpiHost1Sd3 = 46, /// Peripheral Output 44 - Uart2Tx = 47, + Uart0Tx = 47, /// Peripheral Output 45 - Uart3Tx = 48, + Uart1Tx = 48, /// Peripheral Output 46 - PattgenPda0Tx = 49, + Uart2Tx = 49, /// Peripheral Output 47 - PattgenPcl0Tx = 50, + Uart3Tx = 50, /// Peripheral Output 48 - PattgenPda1Tx = 51, + PattgenPda0Tx = 51, /// Peripheral Output 49 - PattgenPcl1Tx = 52, + PattgenPcl0Tx = 52, /// Peripheral Output 50 - SpiHost1Sck = 53, + PattgenPda1Tx = 53, /// Peripheral Output 51 - SpiHost1Csb = 54, + PattgenPcl1Tx = 54, /// Peripheral Output 52 - FlashCtrlTdo = 55, + SpiHost1Sck = 55, /// Peripheral Output 53 - SensorCtrlAonAstDebugOut0 = 56, + SpiHost1Csb = 56, /// Peripheral Output 54 - SensorCtrlAonAstDebugOut1 = 57, + FlashCtrlTdo = 57, /// Peripheral Output 55 - SensorCtrlAonAstDebugOut2 = 58, + SensorCtrlAonAstDebugOut0 = 58, /// Peripheral Output 56 - SensorCtrlAonAstDebugOut3 = 59, + SensorCtrlAonAstDebugOut1 = 59, /// Peripheral Output 57 - SensorCtrlAonAstDebugOut4 = 60, + SensorCtrlAonAstDebugOut2 = 60, /// Peripheral Output 58 - SensorCtrlAonAstDebugOut5 = 61, + SensorCtrlAonAstDebugOut3 = 61, /// Peripheral Output 59 - SensorCtrlAonAstDebugOut6 = 62, + SensorCtrlAonAstDebugOut4 = 62, /// Peripheral Output 60 - SensorCtrlAonAstDebugOut7 = 63, + SensorCtrlAonAstDebugOut5 = 63, /// Peripheral Output 61 - SensorCtrlAonAstDebugOut8 = 64, + SensorCtrlAonAstDebugOut6 = 64, /// Peripheral Output 62 - PwmAonPwm0 = 65, + SensorCtrlAonAstDebugOut7 = 65, /// Peripheral Output 63 - PwmAonPwm1 = 66, + SensorCtrlAonAstDebugOut8 = 66, /// Peripheral Output 64 - PwmAonPwm2 = 67, + PwmAonPwm0 = 67, /// Peripheral Output 65 - PwmAonPwm3 = 68, + PwmAonPwm1 = 68, /// Peripheral Output 66 - PwmAonPwm4 = 69, + PwmAonPwm2 = 69, /// Peripheral Output 67 - PwmAonPwm5 = 70, + PwmAonPwm3 = 70, /// Peripheral Output 68 - OtpCtrlTest0 = 71, + PwmAonPwm4 = 71, /// Peripheral Output 69 - SysrstCtrlAonBatDisable = 72, + PwmAonPwm5 = 72, /// Peripheral Output 70 - SysrstCtrlAonKey0Out = 73, + OtpCtrlTest0 = 73, /// Peripheral Output 71 - SysrstCtrlAonKey1Out = 74, + SysrstCtrlAonBatDisable = 74, /// Peripheral Output 72 - SysrstCtrlAonKey2Out = 75, + SysrstCtrlAonKey0Out = 75, /// Peripheral Output 73 - SysrstCtrlAonPwrbOut = 76, + SysrstCtrlAonKey1Out = 76, /// Peripheral Output 74 - SysrstCtrlAonZ3Wakeup = 77, + SysrstCtrlAonKey2Out = 77, + /// Peripheral Output 75 + SysrstCtrlAonPwrbOut = 78, + /// Peripheral Output 76 + SysrstCtrlAonZ3Wakeup = 79, } impl TryFrom for PinmuxOutsel { @@ -2962,43 +3071,45 @@ impl TryFrom for PinmuxOutsel { 38 => Ok(Self::I2c1Scl), 39 => Ok(Self::I2c2Sda), 40 => Ok(Self::I2c2Scl), - 41 => Ok(Self::SpiHost1Sd0), - 42 => Ok(Self::SpiHost1Sd1), - 43 => Ok(Self::SpiHost1Sd2), - 44 => Ok(Self::SpiHost1Sd3), - 45 => Ok(Self::Uart0Tx), - 46 => Ok(Self::Uart1Tx), - 47 => Ok(Self::Uart2Tx), - 48 => Ok(Self::Uart3Tx), - 49 => Ok(Self::PattgenPda0Tx), - 50 => Ok(Self::PattgenPcl0Tx), - 51 => Ok(Self::PattgenPda1Tx), - 52 => Ok(Self::PattgenPcl1Tx), - 53 => Ok(Self::SpiHost1Sck), - 54 => Ok(Self::SpiHost1Csb), - 55 => Ok(Self::FlashCtrlTdo), - 56 => Ok(Self::SensorCtrlAonAstDebugOut0), - 57 => Ok(Self::SensorCtrlAonAstDebugOut1), - 58 => Ok(Self::SensorCtrlAonAstDebugOut2), - 59 => Ok(Self::SensorCtrlAonAstDebugOut3), - 60 => Ok(Self::SensorCtrlAonAstDebugOut4), - 61 => Ok(Self::SensorCtrlAonAstDebugOut5), - 62 => Ok(Self::SensorCtrlAonAstDebugOut6), - 63 => Ok(Self::SensorCtrlAonAstDebugOut7), - 64 => Ok(Self::SensorCtrlAonAstDebugOut8), - 65 => Ok(Self::PwmAonPwm0), - 66 => Ok(Self::PwmAonPwm1), - 67 => Ok(Self::PwmAonPwm2), - 68 => Ok(Self::PwmAonPwm3), - 69 => Ok(Self::PwmAonPwm4), - 70 => Ok(Self::PwmAonPwm5), - 71 => Ok(Self::OtpCtrlTest0), - 72 => Ok(Self::SysrstCtrlAonBatDisable), - 73 => Ok(Self::SysrstCtrlAonKey0Out), - 74 => Ok(Self::SysrstCtrlAonKey1Out), - 75 => Ok(Self::SysrstCtrlAonKey2Out), - 76 => Ok(Self::SysrstCtrlAonPwrbOut), - 77 => Ok(Self::SysrstCtrlAonZ3Wakeup), + 41 => Ok(Self::I2c3Sda), + 42 => Ok(Self::I2c3Scl), + 43 => Ok(Self::SpiHost1Sd0), + 44 => Ok(Self::SpiHost1Sd1), + 45 => Ok(Self::SpiHost1Sd2), + 46 => Ok(Self::SpiHost1Sd3), + 47 => Ok(Self::Uart0Tx), + 48 => Ok(Self::Uart1Tx), + 49 => Ok(Self::Uart2Tx), + 50 => Ok(Self::Uart3Tx), + 51 => Ok(Self::PattgenPda0Tx), + 52 => Ok(Self::PattgenPcl0Tx), + 53 => Ok(Self::PattgenPda1Tx), + 54 => Ok(Self::PattgenPcl1Tx), + 55 => Ok(Self::SpiHost1Sck), + 56 => Ok(Self::SpiHost1Csb), + 57 => Ok(Self::FlashCtrlTdo), + 58 => Ok(Self::SensorCtrlAonAstDebugOut0), + 59 => Ok(Self::SensorCtrlAonAstDebugOut1), + 60 => Ok(Self::SensorCtrlAonAstDebugOut2), + 61 => Ok(Self::SensorCtrlAonAstDebugOut3), + 62 => Ok(Self::SensorCtrlAonAstDebugOut4), + 63 => Ok(Self::SensorCtrlAonAstDebugOut5), + 64 => Ok(Self::SensorCtrlAonAstDebugOut6), + 65 => Ok(Self::SensorCtrlAonAstDebugOut7), + 66 => Ok(Self::SensorCtrlAonAstDebugOut8), + 67 => Ok(Self::PwmAonPwm0), + 68 => Ok(Self::PwmAonPwm1), + 69 => Ok(Self::PwmAonPwm2), + 70 => Ok(Self::PwmAonPwm3), + 71 => Ok(Self::PwmAonPwm4), + 72 => Ok(Self::PwmAonPwm5), + 73 => Ok(Self::OtpCtrlTest0), + 74 => Ok(Self::SysrstCtrlAonBatDisable), + 75 => Ok(Self::SysrstCtrlAonKey0Out), + 76 => Ok(Self::SysrstCtrlAonKey1Out), + 77 => Ok(Self::SysrstCtrlAonKey2Out), + 78 => Ok(Self::SysrstCtrlAonPwrbOut), + 79 => Ok(Self::SysrstCtrlAonZ3Wakeup), _ => Err(val), } } @@ -3184,6 +3295,7 @@ pub enum ResetManagerSwResets { I2c0 = 5, I2c1 = 6, I2c2 = 7, + I2c3 = 8, } /// Power Manager Reset Request Signals diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index 7a71342dec3095..1ce9f9498d4010 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c @@ -11,7 +11,7 @@ * `top_earlgrey_plic_peripheral_t`. */ const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[182] = { + top_earlgrey_plic_interrupt_for_peripheral[197] = { [kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown, [kTopEarlgreyPlicIrqIdUart0TxWatermark] = kTopEarlgreyPlicPeripheralUart0, [kTopEarlgreyPlicIrqIdUart0RxWatermark] = kTopEarlgreyPlicPeripheralUart0, @@ -130,6 +130,21 @@ const top_earlgrey_plic_peripheral_t [kTopEarlgreyPlicIrqIdI2c2AcqFull] = kTopEarlgreyPlicPeripheralI2c2, [kTopEarlgreyPlicIrqIdI2c2UnexpStop] = kTopEarlgreyPlicPeripheralI2c2, [kTopEarlgreyPlicIrqIdI2c2HostTimeout] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c3FmtThreshold] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3RxThreshold] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3FmtOverflow] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3RxOverflow] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3Nak] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3SclInterference] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3SdaInterference] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3StretchTimeout] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3SdaUnstable] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3CmdComplete] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3TxStretch] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3TxOverflow] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3AcqFull] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3UnexpStop] = kTopEarlgreyPlicPeripheralI2c3, + [kTopEarlgreyPlicIrqIdI2c3HostTimeout] = kTopEarlgreyPlicPeripheralI2c3, [kTopEarlgreyPlicIrqIdPattgenDoneCh0] = kTopEarlgreyPlicPeripheralPattgen, [kTopEarlgreyPlicIrqIdPattgenDoneCh1] = kTopEarlgreyPlicPeripheralPattgen, [kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0] = kTopEarlgreyPlicPeripheralRvTimer, @@ -204,7 +219,7 @@ const top_earlgrey_plic_peripheral_t * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[65] = { + top_earlgrey_alert_for_peripheral[66] = { [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0, [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1, [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2, @@ -214,6 +229,7 @@ const top_earlgrey_alert_peripheral_t [kTopEarlgreyAlertIdI2c0FatalFault] = kTopEarlgreyAlertPeripheralI2c0, [kTopEarlgreyAlertIdI2c1FatalFault] = kTopEarlgreyAlertPeripheralI2c1, [kTopEarlgreyAlertIdI2c2FatalFault] = kTopEarlgreyAlertPeripheralI2c2, + [kTopEarlgreyAlertIdI2c3FatalFault] = kTopEarlgreyAlertPeripheralI2c3, [kTopEarlgreyAlertIdPattgenFatalFault] = kTopEarlgreyAlertPeripheralPattgen, [kTopEarlgreyAlertIdRvTimerFatalFault] = kTopEarlgreyAlertPeripheralRvTimer, [kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl, diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 6de97dbbac19ca..75d6cd1bf90361 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -187,6 +187,24 @@ extern "C" { */ #define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80u +/** + * Peripheral base address for i2c3 in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_I2C3_BASE_ADDR 0x400B0000u + +/** + * Peripheral size for i2c3 in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_I2C3_BASE_ADDR and + * `TOP_EARLGREY_I2C3_BASE_ADDR + TOP_EARLGREY_I2C3_SIZE_BYTES`. + */ +#define TOP_EARLGREY_I2C3_SIZE_BYTES 0x80u + /** * Peripheral base address for pattgen in top earlgrey. * @@ -984,28 +1002,29 @@ typedef enum top_earlgrey_plic_peripheral { kTopEarlgreyPlicPeripheralI2c0 = 7, /**< i2c0 */ kTopEarlgreyPlicPeripheralI2c1 = 8, /**< i2c1 */ kTopEarlgreyPlicPeripheralI2c2 = 9, /**< i2c2 */ - kTopEarlgreyPlicPeripheralPattgen = 10, /**< pattgen */ - kTopEarlgreyPlicPeripheralRvTimer = 11, /**< rv_timer */ - kTopEarlgreyPlicPeripheralOtpCtrl = 12, /**< otp_ctrl */ - kTopEarlgreyPlicPeripheralAlertHandler = 13, /**< alert_handler */ - kTopEarlgreyPlicPeripheralSpiHost0 = 14, /**< spi_host0 */ - kTopEarlgreyPlicPeripheralSpiHost1 = 15, /**< spi_host1 */ - kTopEarlgreyPlicPeripheralUsbdev = 16, /**< usbdev */ - kTopEarlgreyPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */ - kTopEarlgreyPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */ - kTopEarlgreyPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */ - kTopEarlgreyPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */ - kTopEarlgreyPlicPeripheralSensorCtrlAon = 21, /**< sensor_ctrl_aon */ - kTopEarlgreyPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */ - kTopEarlgreyPlicPeripheralHmac = 23, /**< hmac */ - kTopEarlgreyPlicPeripheralKmac = 24, /**< kmac */ - kTopEarlgreyPlicPeripheralOtbn = 25, /**< otbn */ - kTopEarlgreyPlicPeripheralKeymgr = 26, /**< keymgr */ - kTopEarlgreyPlicPeripheralCsrng = 27, /**< csrng */ - kTopEarlgreyPlicPeripheralEntropySrc = 28, /**< entropy_src */ - kTopEarlgreyPlicPeripheralEdn0 = 29, /**< edn0 */ - kTopEarlgreyPlicPeripheralEdn1 = 30, /**< edn1 */ - kTopEarlgreyPlicPeripheralLast = 30, /**< \internal Final PLIC peripheral */ + kTopEarlgreyPlicPeripheralI2c3 = 10, /**< i2c3 */ + kTopEarlgreyPlicPeripheralPattgen = 11, /**< pattgen */ + kTopEarlgreyPlicPeripheralRvTimer = 12, /**< rv_timer */ + kTopEarlgreyPlicPeripheralOtpCtrl = 13, /**< otp_ctrl */ + kTopEarlgreyPlicPeripheralAlertHandler = 14, /**< alert_handler */ + kTopEarlgreyPlicPeripheralSpiHost0 = 15, /**< spi_host0 */ + kTopEarlgreyPlicPeripheralSpiHost1 = 16, /**< spi_host1 */ + kTopEarlgreyPlicPeripheralUsbdev = 17, /**< usbdev */ + kTopEarlgreyPlicPeripheralPwrmgrAon = 18, /**< pwrmgr_aon */ + kTopEarlgreyPlicPeripheralSysrstCtrlAon = 19, /**< sysrst_ctrl_aon */ + kTopEarlgreyPlicPeripheralAdcCtrlAon = 20, /**< adc_ctrl_aon */ + kTopEarlgreyPlicPeripheralAonTimerAon = 21, /**< aon_timer_aon */ + kTopEarlgreyPlicPeripheralSensorCtrlAon = 22, /**< sensor_ctrl_aon */ + kTopEarlgreyPlicPeripheralFlashCtrl = 23, /**< flash_ctrl */ + kTopEarlgreyPlicPeripheralHmac = 24, /**< hmac */ + kTopEarlgreyPlicPeripheralKmac = 25, /**< kmac */ + kTopEarlgreyPlicPeripheralOtbn = 26, /**< otbn */ + kTopEarlgreyPlicPeripheralKeymgr = 27, /**< keymgr */ + kTopEarlgreyPlicPeripheralCsrng = 28, /**< csrng */ + kTopEarlgreyPlicPeripheralEntropySrc = 29, /**< entropy_src */ + kTopEarlgreyPlicPeripheralEdn0 = 30, /**< edn0 */ + kTopEarlgreyPlicPeripheralEdn1 = 31, /**< edn1 */ + kTopEarlgreyPlicPeripheralLast = 31, /**< \internal Final PLIC peripheral */ } top_earlgrey_plic_peripheral_t; /** @@ -1133,71 +1152,86 @@ typedef enum top_earlgrey_plic_irq_id { kTopEarlgreyPlicIrqIdI2c2AcqFull = 115, /**< i2c2_acq_full */ kTopEarlgreyPlicIrqIdI2c2UnexpStop = 116, /**< i2c2_unexp_stop */ kTopEarlgreyPlicIrqIdI2c2HostTimeout = 117, /**< i2c2_host_timeout */ - kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 118, /**< pattgen_done_ch0 */ - kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 119, /**< pattgen_done_ch1 */ - kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 120, /**< rv_timer_timer_expired_hart0_timer0 */ - kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 121, /**< otp_ctrl_otp_operation_done */ - kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 122, /**< otp_ctrl_otp_error */ - kTopEarlgreyPlicIrqIdAlertHandlerClassa = 123, /**< alert_handler_classa */ - kTopEarlgreyPlicIrqIdAlertHandlerClassb = 124, /**< alert_handler_classb */ - kTopEarlgreyPlicIrqIdAlertHandlerClassc = 125, /**< alert_handler_classc */ - kTopEarlgreyPlicIrqIdAlertHandlerClassd = 126, /**< alert_handler_classd */ - kTopEarlgreyPlicIrqIdSpiHost0Error = 127, /**< spi_host0_error */ - kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 128, /**< spi_host0_spi_event */ - kTopEarlgreyPlicIrqIdSpiHost1Error = 129, /**< spi_host1_error */ - kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 130, /**< spi_host1_spi_event */ - kTopEarlgreyPlicIrqIdUsbdevPktReceived = 131, /**< usbdev_pkt_received */ - kTopEarlgreyPlicIrqIdUsbdevPktSent = 132, /**< usbdev_pkt_sent */ - kTopEarlgreyPlicIrqIdUsbdevDisconnected = 133, /**< usbdev_disconnected */ - kTopEarlgreyPlicIrqIdUsbdevHostLost = 134, /**< usbdev_host_lost */ - kTopEarlgreyPlicIrqIdUsbdevLinkReset = 135, /**< usbdev_link_reset */ - kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 136, /**< usbdev_link_suspend */ - kTopEarlgreyPlicIrqIdUsbdevLinkResume = 137, /**< usbdev_link_resume */ - kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty = 138, /**< usbdev_av_out_empty */ - kTopEarlgreyPlicIrqIdUsbdevRxFull = 139, /**< usbdev_rx_full */ - kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 140, /**< usbdev_av_overflow */ - kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 141, /**< usbdev_link_in_err */ - kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 142, /**< usbdev_rx_crc_err */ - kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 143, /**< usbdev_rx_pid_err */ - kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 144, /**< usbdev_rx_bitstuff_err */ - kTopEarlgreyPlicIrqIdUsbdevFrame = 145, /**< usbdev_frame */ - kTopEarlgreyPlicIrqIdUsbdevPowered = 146, /**< usbdev_powered */ - kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 147, /**< usbdev_link_out_err */ - kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty = 148, /**< usbdev_av_setup_empty */ - kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 149, /**< pwrmgr_aon_wakeup */ - kTopEarlgreyPlicIrqIdSysrstCtrlAonEventDetected = 150, /**< sysrst_ctrl_aon_event_detected */ - kTopEarlgreyPlicIrqIdAdcCtrlAonMatchDone = 151, /**< adc_ctrl_aon_match_done */ - kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired = 152, /**< aon_timer_aon_wkup_timer_expired */ - kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark = 153, /**< aon_timer_aon_wdog_timer_bark */ - kTopEarlgreyPlicIrqIdSensorCtrlAonIoStatusChange = 154, /**< sensor_ctrl_aon_io_status_change */ - kTopEarlgreyPlicIrqIdSensorCtrlAonInitStatusChange = 155, /**< sensor_ctrl_aon_init_status_change */ - kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 156, /**< flash_ctrl_prog_empty */ - kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 157, /**< flash_ctrl_prog_lvl */ - kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 158, /**< flash_ctrl_rd_full */ - kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 159, /**< flash_ctrl_rd_lvl */ - kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 160, /**< flash_ctrl_op_done */ - kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 161, /**< flash_ctrl_corr_err */ - kTopEarlgreyPlicIrqIdHmacHmacDone = 162, /**< hmac_hmac_done */ - kTopEarlgreyPlicIrqIdHmacFifoEmpty = 163, /**< hmac_fifo_empty */ - kTopEarlgreyPlicIrqIdHmacHmacErr = 164, /**< hmac_hmac_err */ - kTopEarlgreyPlicIrqIdKmacKmacDone = 165, /**< kmac_kmac_done */ - kTopEarlgreyPlicIrqIdKmacFifoEmpty = 166, /**< kmac_fifo_empty */ - kTopEarlgreyPlicIrqIdKmacKmacErr = 167, /**< kmac_kmac_err */ - kTopEarlgreyPlicIrqIdOtbnDone = 168, /**< otbn_done */ - kTopEarlgreyPlicIrqIdKeymgrOpDone = 169, /**< keymgr_op_done */ - kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 170, /**< csrng_cs_cmd_req_done */ - kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 171, /**< csrng_cs_entropy_req */ - kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 172, /**< csrng_cs_hw_inst_exc */ - kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 173, /**< csrng_cs_fatal_err */ - kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 174, /**< entropy_src_es_entropy_valid */ - kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 175, /**< entropy_src_es_health_test_failed */ - kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 176, /**< entropy_src_es_observe_fifo_ready */ - kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 177, /**< entropy_src_es_fatal_err */ - kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 178, /**< edn0_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 179, /**< edn0_edn_fatal_err */ - kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 180, /**< edn1_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 181, /**< edn1_edn_fatal_err */ - kTopEarlgreyPlicIrqIdLast = 181, /**< \internal The Last Valid Interrupt ID. */ + kTopEarlgreyPlicIrqIdI2c3FmtThreshold = 118, /**< i2c3_fmt_threshold */ + kTopEarlgreyPlicIrqIdI2c3RxThreshold = 119, /**< i2c3_rx_threshold */ + kTopEarlgreyPlicIrqIdI2c3FmtOverflow = 120, /**< i2c3_fmt_overflow */ + kTopEarlgreyPlicIrqIdI2c3RxOverflow = 121, /**< i2c3_rx_overflow */ + kTopEarlgreyPlicIrqIdI2c3Nak = 122, /**< i2c3_nak */ + kTopEarlgreyPlicIrqIdI2c3SclInterference = 123, /**< i2c3_scl_interference */ + kTopEarlgreyPlicIrqIdI2c3SdaInterference = 124, /**< i2c3_sda_interference */ + kTopEarlgreyPlicIrqIdI2c3StretchTimeout = 125, /**< i2c3_stretch_timeout */ + kTopEarlgreyPlicIrqIdI2c3SdaUnstable = 126, /**< i2c3_sda_unstable */ + kTopEarlgreyPlicIrqIdI2c3CmdComplete = 127, /**< i2c3_cmd_complete */ + kTopEarlgreyPlicIrqIdI2c3TxStretch = 128, /**< i2c3_tx_stretch */ + kTopEarlgreyPlicIrqIdI2c3TxOverflow = 129, /**< i2c3_tx_overflow */ + kTopEarlgreyPlicIrqIdI2c3AcqFull = 130, /**< i2c3_acq_full */ + kTopEarlgreyPlicIrqIdI2c3UnexpStop = 131, /**< i2c3_unexp_stop */ + kTopEarlgreyPlicIrqIdI2c3HostTimeout = 132, /**< i2c3_host_timeout */ + kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 133, /**< pattgen_done_ch0 */ + kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 134, /**< pattgen_done_ch1 */ + kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 135, /**< rv_timer_timer_expired_hart0_timer0 */ + kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 136, /**< otp_ctrl_otp_operation_done */ + kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 137, /**< otp_ctrl_otp_error */ + kTopEarlgreyPlicIrqIdAlertHandlerClassa = 138, /**< alert_handler_classa */ + kTopEarlgreyPlicIrqIdAlertHandlerClassb = 139, /**< alert_handler_classb */ + kTopEarlgreyPlicIrqIdAlertHandlerClassc = 140, /**< alert_handler_classc */ + kTopEarlgreyPlicIrqIdAlertHandlerClassd = 141, /**< alert_handler_classd */ + kTopEarlgreyPlicIrqIdSpiHost0Error = 142, /**< spi_host0_error */ + kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 143, /**< spi_host0_spi_event */ + kTopEarlgreyPlicIrqIdSpiHost1Error = 144, /**< spi_host1_error */ + kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 145, /**< spi_host1_spi_event */ + kTopEarlgreyPlicIrqIdUsbdevPktReceived = 146, /**< usbdev_pkt_received */ + kTopEarlgreyPlicIrqIdUsbdevPktSent = 147, /**< usbdev_pkt_sent */ + kTopEarlgreyPlicIrqIdUsbdevDisconnected = 148, /**< usbdev_disconnected */ + kTopEarlgreyPlicIrqIdUsbdevHostLost = 149, /**< usbdev_host_lost */ + kTopEarlgreyPlicIrqIdUsbdevLinkReset = 150, /**< usbdev_link_reset */ + kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 151, /**< usbdev_link_suspend */ + kTopEarlgreyPlicIrqIdUsbdevLinkResume = 152, /**< usbdev_link_resume */ + kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty = 153, /**< usbdev_av_out_empty */ + kTopEarlgreyPlicIrqIdUsbdevRxFull = 154, /**< usbdev_rx_full */ + kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 155, /**< usbdev_av_overflow */ + kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 156, /**< usbdev_link_in_err */ + kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 157, /**< usbdev_rx_crc_err */ + kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 158, /**< usbdev_rx_pid_err */ + kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 159, /**< usbdev_rx_bitstuff_err */ + kTopEarlgreyPlicIrqIdUsbdevFrame = 160, /**< usbdev_frame */ + kTopEarlgreyPlicIrqIdUsbdevPowered = 161, /**< usbdev_powered */ + kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 162, /**< usbdev_link_out_err */ + kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty = 163, /**< usbdev_av_setup_empty */ + kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 164, /**< pwrmgr_aon_wakeup */ + kTopEarlgreyPlicIrqIdSysrstCtrlAonEventDetected = 165, /**< sysrst_ctrl_aon_event_detected */ + kTopEarlgreyPlicIrqIdAdcCtrlAonMatchDone = 166, /**< adc_ctrl_aon_match_done */ + kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired = 167, /**< aon_timer_aon_wkup_timer_expired */ + kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark = 168, /**< aon_timer_aon_wdog_timer_bark */ + kTopEarlgreyPlicIrqIdSensorCtrlAonIoStatusChange = 169, /**< sensor_ctrl_aon_io_status_change */ + kTopEarlgreyPlicIrqIdSensorCtrlAonInitStatusChange = 170, /**< sensor_ctrl_aon_init_status_change */ + kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 171, /**< flash_ctrl_prog_empty */ + kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 172, /**< flash_ctrl_prog_lvl */ + kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 173, /**< flash_ctrl_rd_full */ + kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 174, /**< flash_ctrl_rd_lvl */ + kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 175, /**< flash_ctrl_op_done */ + kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 176, /**< flash_ctrl_corr_err */ + kTopEarlgreyPlicIrqIdHmacHmacDone = 177, /**< hmac_hmac_done */ + kTopEarlgreyPlicIrqIdHmacFifoEmpty = 178, /**< hmac_fifo_empty */ + kTopEarlgreyPlicIrqIdHmacHmacErr = 179, /**< hmac_hmac_err */ + kTopEarlgreyPlicIrqIdKmacKmacDone = 180, /**< kmac_kmac_done */ + kTopEarlgreyPlicIrqIdKmacFifoEmpty = 181, /**< kmac_fifo_empty */ + kTopEarlgreyPlicIrqIdKmacKmacErr = 182, /**< kmac_kmac_err */ + kTopEarlgreyPlicIrqIdOtbnDone = 183, /**< otbn_done */ + kTopEarlgreyPlicIrqIdKeymgrOpDone = 184, /**< keymgr_op_done */ + kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 185, /**< csrng_cs_cmd_req_done */ + kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 186, /**< csrng_cs_entropy_req */ + kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 187, /**< csrng_cs_hw_inst_exc */ + kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 188, /**< csrng_cs_fatal_err */ + kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 189, /**< entropy_src_es_entropy_valid */ + kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 190, /**< entropy_src_es_health_test_failed */ + kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 191, /**< entropy_src_es_observe_fifo_ready */ + kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 192, /**< entropy_src_es_fatal_err */ + kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 193, /**< edn0_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 194, /**< edn0_edn_fatal_err */ + kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 195, /**< edn1_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 196, /**< edn1_edn_fatal_err */ + kTopEarlgreyPlicIrqIdLast = 196, /**< \internal The Last Valid Interrupt ID. */ } top_earlgrey_plic_irq_id_t; /** @@ -1207,7 +1241,7 @@ typedef enum top_earlgrey_plic_irq_id { * `top_earlgrey_plic_peripheral_t`. */ extern const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[182]; + top_earlgrey_plic_interrupt_for_peripheral[197]; /** * PLIC Interrupt Target. @@ -1236,39 +1270,40 @@ typedef enum top_earlgrey_alert_peripheral { kTopEarlgreyAlertPeripheralI2c0 = 6, /**< i2c0 */ kTopEarlgreyAlertPeripheralI2c1 = 7, /**< i2c1 */ kTopEarlgreyAlertPeripheralI2c2 = 8, /**< i2c2 */ - kTopEarlgreyAlertPeripheralPattgen = 9, /**< pattgen */ - kTopEarlgreyAlertPeripheralRvTimer = 10, /**< rv_timer */ - kTopEarlgreyAlertPeripheralOtpCtrl = 11, /**< otp_ctrl */ - kTopEarlgreyAlertPeripheralLcCtrl = 12, /**< lc_ctrl */ - kTopEarlgreyAlertPeripheralSpiHost0 = 13, /**< spi_host0 */ - kTopEarlgreyAlertPeripheralSpiHost1 = 14, /**< spi_host1 */ - kTopEarlgreyAlertPeripheralUsbdev = 15, /**< usbdev */ - kTopEarlgreyAlertPeripheralPwrmgrAon = 16, /**< pwrmgr_aon */ - kTopEarlgreyAlertPeripheralRstmgrAon = 17, /**< rstmgr_aon */ - kTopEarlgreyAlertPeripheralClkmgrAon = 18, /**< clkmgr_aon */ - kTopEarlgreyAlertPeripheralSysrstCtrlAon = 19, /**< sysrst_ctrl_aon */ - kTopEarlgreyAlertPeripheralAdcCtrlAon = 20, /**< adc_ctrl_aon */ - kTopEarlgreyAlertPeripheralPwmAon = 21, /**< pwm_aon */ - kTopEarlgreyAlertPeripheralPinmuxAon = 22, /**< pinmux_aon */ - kTopEarlgreyAlertPeripheralAonTimerAon = 23, /**< aon_timer_aon */ - kTopEarlgreyAlertPeripheralSensorCtrlAon = 24, /**< sensor_ctrl_aon */ - kTopEarlgreyAlertPeripheralSramCtrlRetAon = 25, /**< sram_ctrl_ret_aon */ - kTopEarlgreyAlertPeripheralFlashCtrl = 26, /**< flash_ctrl */ - kTopEarlgreyAlertPeripheralRvDm = 27, /**< rv_dm */ - kTopEarlgreyAlertPeripheralRvPlic = 28, /**< rv_plic */ - kTopEarlgreyAlertPeripheralAes = 29, /**< aes */ - kTopEarlgreyAlertPeripheralHmac = 30, /**< hmac */ - kTopEarlgreyAlertPeripheralKmac = 31, /**< kmac */ - kTopEarlgreyAlertPeripheralOtbn = 32, /**< otbn */ - kTopEarlgreyAlertPeripheralKeymgr = 33, /**< keymgr */ - kTopEarlgreyAlertPeripheralCsrng = 34, /**< csrng */ - kTopEarlgreyAlertPeripheralEntropySrc = 35, /**< entropy_src */ - kTopEarlgreyAlertPeripheralEdn0 = 36, /**< edn0 */ - kTopEarlgreyAlertPeripheralEdn1 = 37, /**< edn1 */ - kTopEarlgreyAlertPeripheralSramCtrlMain = 38, /**< sram_ctrl_main */ - kTopEarlgreyAlertPeripheralRomCtrl = 39, /**< rom_ctrl */ - kTopEarlgreyAlertPeripheralRvCoreIbex = 40, /**< rv_core_ibex */ - kTopEarlgreyAlertPeripheralLast = 40, /**< \internal Final Alert peripheral */ + kTopEarlgreyAlertPeripheralI2c3 = 9, /**< i2c3 */ + kTopEarlgreyAlertPeripheralPattgen = 10, /**< pattgen */ + kTopEarlgreyAlertPeripheralRvTimer = 11, /**< rv_timer */ + kTopEarlgreyAlertPeripheralOtpCtrl = 12, /**< otp_ctrl */ + kTopEarlgreyAlertPeripheralLcCtrl = 13, /**< lc_ctrl */ + kTopEarlgreyAlertPeripheralSpiHost0 = 14, /**< spi_host0 */ + kTopEarlgreyAlertPeripheralSpiHost1 = 15, /**< spi_host1 */ + kTopEarlgreyAlertPeripheralUsbdev = 16, /**< usbdev */ + kTopEarlgreyAlertPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */ + kTopEarlgreyAlertPeripheralRstmgrAon = 18, /**< rstmgr_aon */ + kTopEarlgreyAlertPeripheralClkmgrAon = 19, /**< clkmgr_aon */ + kTopEarlgreyAlertPeripheralSysrstCtrlAon = 20, /**< sysrst_ctrl_aon */ + kTopEarlgreyAlertPeripheralAdcCtrlAon = 21, /**< adc_ctrl_aon */ + kTopEarlgreyAlertPeripheralPwmAon = 22, /**< pwm_aon */ + kTopEarlgreyAlertPeripheralPinmuxAon = 23, /**< pinmux_aon */ + kTopEarlgreyAlertPeripheralAonTimerAon = 24, /**< aon_timer_aon */ + kTopEarlgreyAlertPeripheralSensorCtrlAon = 25, /**< sensor_ctrl_aon */ + kTopEarlgreyAlertPeripheralSramCtrlRetAon = 26, /**< sram_ctrl_ret_aon */ + kTopEarlgreyAlertPeripheralFlashCtrl = 27, /**< flash_ctrl */ + kTopEarlgreyAlertPeripheralRvDm = 28, /**< rv_dm */ + kTopEarlgreyAlertPeripheralRvPlic = 29, /**< rv_plic */ + kTopEarlgreyAlertPeripheralAes = 30, /**< aes */ + kTopEarlgreyAlertPeripheralHmac = 31, /**< hmac */ + kTopEarlgreyAlertPeripheralKmac = 32, /**< kmac */ + kTopEarlgreyAlertPeripheralOtbn = 33, /**< otbn */ + kTopEarlgreyAlertPeripheralKeymgr = 34, /**< keymgr */ + kTopEarlgreyAlertPeripheralCsrng = 35, /**< csrng */ + kTopEarlgreyAlertPeripheralEntropySrc = 36, /**< entropy_src */ + kTopEarlgreyAlertPeripheralEdn0 = 37, /**< edn0 */ + kTopEarlgreyAlertPeripheralEdn1 = 38, /**< edn1 */ + kTopEarlgreyAlertPeripheralSramCtrlMain = 39, /**< sram_ctrl_main */ + kTopEarlgreyAlertPeripheralRomCtrl = 40, /**< rom_ctrl */ + kTopEarlgreyAlertPeripheralRvCoreIbex = 41, /**< rv_core_ibex */ + kTopEarlgreyAlertPeripheralLast = 41, /**< \internal Final Alert peripheral */ } top_earlgrey_alert_peripheral_t; /** @@ -1287,63 +1322,64 @@ typedef enum top_earlgrey_alert_id { kTopEarlgreyAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */ kTopEarlgreyAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */ kTopEarlgreyAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */ - kTopEarlgreyAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */ - kTopEarlgreyAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */ - kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 11, /**< otp_ctrl_fatal_macro_error */ - kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 12, /**< otp_ctrl_fatal_check_error */ - kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 13, /**< otp_ctrl_fatal_bus_integ_error */ - kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 14, /**< otp_ctrl_fatal_prim_otp_alert */ - kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 15, /**< otp_ctrl_recov_prim_otp_alert */ - kTopEarlgreyAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */ - kTopEarlgreyAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */ - kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */ - kTopEarlgreyAlertIdSpiHost0FatalFault = 19, /**< spi_host0_fatal_fault */ - kTopEarlgreyAlertIdSpiHost1FatalFault = 20, /**< spi_host1_fatal_fault */ - kTopEarlgreyAlertIdUsbdevFatalFault = 21, /**< usbdev_fatal_fault */ - kTopEarlgreyAlertIdPwrmgrAonFatalFault = 22, /**< pwrmgr_aon_fatal_fault */ - kTopEarlgreyAlertIdRstmgrAonFatalFault = 23, /**< rstmgr_aon_fatal_fault */ - kTopEarlgreyAlertIdRstmgrAonFatalCnstyFault = 24, /**< rstmgr_aon_fatal_cnsty_fault */ - kTopEarlgreyAlertIdClkmgrAonRecovFault = 25, /**< clkmgr_aon_recov_fault */ - kTopEarlgreyAlertIdClkmgrAonFatalFault = 26, /**< clkmgr_aon_fatal_fault */ - kTopEarlgreyAlertIdSysrstCtrlAonFatalFault = 27, /**< sysrst_ctrl_aon_fatal_fault */ - kTopEarlgreyAlertIdAdcCtrlAonFatalFault = 28, /**< adc_ctrl_aon_fatal_fault */ - kTopEarlgreyAlertIdPwmAonFatalFault = 29, /**< pwm_aon_fatal_fault */ - kTopEarlgreyAlertIdPinmuxAonFatalFault = 30, /**< pinmux_aon_fatal_fault */ - kTopEarlgreyAlertIdAonTimerAonFatalFault = 31, /**< aon_timer_aon_fatal_fault */ - kTopEarlgreyAlertIdSensorCtrlAonRecovAlert = 32, /**< sensor_ctrl_aon_recov_alert */ - kTopEarlgreyAlertIdSensorCtrlAonFatalAlert = 33, /**< sensor_ctrl_aon_fatal_alert */ - kTopEarlgreyAlertIdSramCtrlRetAonFatalError = 34, /**< sram_ctrl_ret_aon_fatal_error */ - kTopEarlgreyAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */ - kTopEarlgreyAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */ - kTopEarlgreyAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */ - kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */ - kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */ - kTopEarlgreyAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */ - kTopEarlgreyAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */ - kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */ - kTopEarlgreyAlertIdAesFatalFault = 43, /**< aes_fatal_fault */ - kTopEarlgreyAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */ - kTopEarlgreyAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */ - kTopEarlgreyAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */ - kTopEarlgreyAlertIdOtbnFatal = 47, /**< otbn_fatal */ - kTopEarlgreyAlertIdOtbnRecov = 48, /**< otbn_recov */ - kTopEarlgreyAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */ - kTopEarlgreyAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */ - kTopEarlgreyAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */ - kTopEarlgreyAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */ - kTopEarlgreyAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */ - kTopEarlgreyAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */ - kTopEarlgreyAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */ - kTopEarlgreyAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */ - kTopEarlgreyAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */ - kTopEarlgreyAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */ - kTopEarlgreyAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */ - kTopEarlgreyAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */ - kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 61, /**< rv_core_ibex_fatal_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 62, /**< rv_core_ibex_recov_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 63, /**< rv_core_ibex_fatal_hw_err */ - kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 64, /**< rv_core_ibex_recov_hw_err */ - kTopEarlgreyAlertIdLast = 64, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdI2c3FatalFault = 9, /**< i2c3_fatal_fault */ + kTopEarlgreyAlertIdPattgenFatalFault = 10, /**< pattgen_fatal_fault */ + kTopEarlgreyAlertIdRvTimerFatalFault = 11, /**< rv_timer_fatal_fault */ + kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 12, /**< otp_ctrl_fatal_macro_error */ + kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 13, /**< otp_ctrl_fatal_check_error */ + kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 14, /**< otp_ctrl_fatal_bus_integ_error */ + kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 15, /**< otp_ctrl_fatal_prim_otp_alert */ + kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 16, /**< otp_ctrl_recov_prim_otp_alert */ + kTopEarlgreyAlertIdLcCtrlFatalProgError = 17, /**< lc_ctrl_fatal_prog_error */ + kTopEarlgreyAlertIdLcCtrlFatalStateError = 18, /**< lc_ctrl_fatal_state_error */ + kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 19, /**< lc_ctrl_fatal_bus_integ_error */ + kTopEarlgreyAlertIdSpiHost0FatalFault = 20, /**< spi_host0_fatal_fault */ + kTopEarlgreyAlertIdSpiHost1FatalFault = 21, /**< spi_host1_fatal_fault */ + kTopEarlgreyAlertIdUsbdevFatalFault = 22, /**< usbdev_fatal_fault */ + kTopEarlgreyAlertIdPwrmgrAonFatalFault = 23, /**< pwrmgr_aon_fatal_fault */ + kTopEarlgreyAlertIdRstmgrAonFatalFault = 24, /**< rstmgr_aon_fatal_fault */ + kTopEarlgreyAlertIdRstmgrAonFatalCnstyFault = 25, /**< rstmgr_aon_fatal_cnsty_fault */ + kTopEarlgreyAlertIdClkmgrAonRecovFault = 26, /**< clkmgr_aon_recov_fault */ + kTopEarlgreyAlertIdClkmgrAonFatalFault = 27, /**< clkmgr_aon_fatal_fault */ + kTopEarlgreyAlertIdSysrstCtrlAonFatalFault = 28, /**< sysrst_ctrl_aon_fatal_fault */ + kTopEarlgreyAlertIdAdcCtrlAonFatalFault = 29, /**< adc_ctrl_aon_fatal_fault */ + kTopEarlgreyAlertIdPwmAonFatalFault = 30, /**< pwm_aon_fatal_fault */ + kTopEarlgreyAlertIdPinmuxAonFatalFault = 31, /**< pinmux_aon_fatal_fault */ + kTopEarlgreyAlertIdAonTimerAonFatalFault = 32, /**< aon_timer_aon_fatal_fault */ + kTopEarlgreyAlertIdSensorCtrlAonRecovAlert = 33, /**< sensor_ctrl_aon_recov_alert */ + kTopEarlgreyAlertIdSensorCtrlAonFatalAlert = 34, /**< sensor_ctrl_aon_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlRetAonFatalError = 35, /**< sram_ctrl_ret_aon_fatal_error */ + kTopEarlgreyAlertIdFlashCtrlRecovErr = 36, /**< flash_ctrl_recov_err */ + kTopEarlgreyAlertIdFlashCtrlFatalStdErr = 37, /**< flash_ctrl_fatal_std_err */ + kTopEarlgreyAlertIdFlashCtrlFatalErr = 38, /**< flash_ctrl_fatal_err */ + kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 39, /**< flash_ctrl_fatal_prim_flash_alert */ + kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 40, /**< flash_ctrl_recov_prim_flash_alert */ + kTopEarlgreyAlertIdRvDmFatalFault = 41, /**< rv_dm_fatal_fault */ + kTopEarlgreyAlertIdRvPlicFatalFault = 42, /**< rv_plic_fatal_fault */ + kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 43, /**< aes_recov_ctrl_update_err */ + kTopEarlgreyAlertIdAesFatalFault = 44, /**< aes_fatal_fault */ + kTopEarlgreyAlertIdHmacFatalFault = 45, /**< hmac_fatal_fault */ + kTopEarlgreyAlertIdKmacRecovOperationErr = 46, /**< kmac_recov_operation_err */ + kTopEarlgreyAlertIdKmacFatalFaultErr = 47, /**< kmac_fatal_fault_err */ + kTopEarlgreyAlertIdOtbnFatal = 48, /**< otbn_fatal */ + kTopEarlgreyAlertIdOtbnRecov = 49, /**< otbn_recov */ + kTopEarlgreyAlertIdKeymgrRecovOperationErr = 50, /**< keymgr_recov_operation_err */ + kTopEarlgreyAlertIdKeymgrFatalFaultErr = 51, /**< keymgr_fatal_fault_err */ + kTopEarlgreyAlertIdCsrngRecovAlert = 52, /**< csrng_recov_alert */ + kTopEarlgreyAlertIdCsrngFatalAlert = 53, /**< csrng_fatal_alert */ + kTopEarlgreyAlertIdEntropySrcRecovAlert = 54, /**< entropy_src_recov_alert */ + kTopEarlgreyAlertIdEntropySrcFatalAlert = 55, /**< entropy_src_fatal_alert */ + kTopEarlgreyAlertIdEdn0RecovAlert = 56, /**< edn0_recov_alert */ + kTopEarlgreyAlertIdEdn0FatalAlert = 57, /**< edn0_fatal_alert */ + kTopEarlgreyAlertIdEdn1RecovAlert = 58, /**< edn1_recov_alert */ + kTopEarlgreyAlertIdEdn1FatalAlert = 59, /**< edn1_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlMainFatalError = 60, /**< sram_ctrl_main_fatal_error */ + kTopEarlgreyAlertIdRomCtrlFatal = 61, /**< rom_ctrl_fatal */ + kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 62, /**< rv_core_ibex_fatal_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 63, /**< rv_core_ibex_recov_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 64, /**< rv_core_ibex_fatal_hw_err */ + kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 65, /**< rv_core_ibex_recov_hw_err */ + kTopEarlgreyAlertIdLast = 65, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -1353,7 +1389,7 @@ typedef enum top_earlgrey_alert_id { * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[65]; + top_earlgrey_alert_for_peripheral[66]; #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2 @@ -1406,26 +1442,28 @@ typedef enum top_earlgrey_pinmux_peripheral_in { kTopEarlgreyPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */ kTopEarlgreyPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */ kTopEarlgreyPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */ - kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 38, /**< Peripheral Input 38 */ - kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 39, /**< Peripheral Input 39 */ - kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 40, /**< Peripheral Input 40 */ - kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 41, /**< Peripheral Input 41 */ - kTopEarlgreyPinmuxPeripheralInUart0Rx = 42, /**< Peripheral Input 42 */ - kTopEarlgreyPinmuxPeripheralInUart1Rx = 43, /**< Peripheral Input 43 */ - kTopEarlgreyPinmuxPeripheralInUart2Rx = 44, /**< Peripheral Input 44 */ - kTopEarlgreyPinmuxPeripheralInUart3Rx = 45, /**< Peripheral Input 45 */ - kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 46, /**< Peripheral Input 46 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 47, /**< Peripheral Input 47 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 48, /**< Peripheral Input 48 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 49, /**< Peripheral Input 49 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent = 50, /**< Peripheral Input 50 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In = 51, /**< Peripheral Input 51 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In = 52, /**< Peripheral Input 52 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey2In = 53, /**< Peripheral Input 53 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonPwrbIn = 54, /**< Peripheral Input 54 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonLidOpen = 55, /**< Peripheral Input 55 */ - kTopEarlgreyPinmuxPeripheralInUsbdevSense = 56, /**< Peripheral Input 56 */ - kTopEarlgreyPinmuxPeripheralInLast = 56, /**< \internal Last valid peripheral input */ + kTopEarlgreyPinmuxPeripheralInI2c3Sda = 38, /**< Peripheral Input 38 */ + kTopEarlgreyPinmuxPeripheralInI2c3Scl = 39, /**< Peripheral Input 39 */ + kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 40, /**< Peripheral Input 40 */ + kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 41, /**< Peripheral Input 41 */ + kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 42, /**< Peripheral Input 42 */ + kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 43, /**< Peripheral Input 43 */ + kTopEarlgreyPinmuxPeripheralInUart0Rx = 44, /**< Peripheral Input 44 */ + kTopEarlgreyPinmuxPeripheralInUart1Rx = 45, /**< Peripheral Input 45 */ + kTopEarlgreyPinmuxPeripheralInUart2Rx = 46, /**< Peripheral Input 46 */ + kTopEarlgreyPinmuxPeripheralInUart3Rx = 47, /**< Peripheral Input 47 */ + kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 48, /**< Peripheral Input 48 */ + kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 49, /**< Peripheral Input 49 */ + kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 50, /**< Peripheral Input 50 */ + kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 51, /**< Peripheral Input 51 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent = 52, /**< Peripheral Input 52 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In = 53, /**< Peripheral Input 53 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In = 54, /**< Peripheral Input 54 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey2In = 55, /**< Peripheral Input 55 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonPwrbIn = 56, /**< Peripheral Input 56 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonLidOpen = 57, /**< Peripheral Input 57 */ + kTopEarlgreyPinmuxPeripheralInUsbdevSense = 58, /**< Peripheral Input 58 */ + kTopEarlgreyPinmuxPeripheralInLast = 58, /**< \internal Last valid peripheral input */ } top_earlgrey_pinmux_peripheral_in_t; /** @@ -1583,44 +1621,46 @@ typedef enum top_earlgrey_pinmux_outsel { kTopEarlgreyPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */ kTopEarlgreyPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */ kTopEarlgreyPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */ - kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 41, /**< Peripheral Output 38 */ - kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 42, /**< Peripheral Output 39 */ - kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 43, /**< Peripheral Output 40 */ - kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 44, /**< Peripheral Output 41 */ - kTopEarlgreyPinmuxOutselUart0Tx = 45, /**< Peripheral Output 42 */ - kTopEarlgreyPinmuxOutselUart1Tx = 46, /**< Peripheral Output 43 */ - kTopEarlgreyPinmuxOutselUart2Tx = 47, /**< Peripheral Output 44 */ - kTopEarlgreyPinmuxOutselUart3Tx = 48, /**< Peripheral Output 45 */ - kTopEarlgreyPinmuxOutselPattgenPda0Tx = 49, /**< Peripheral Output 46 */ - kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 50, /**< Peripheral Output 47 */ - kTopEarlgreyPinmuxOutselPattgenPda1Tx = 51, /**< Peripheral Output 48 */ - kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 52, /**< Peripheral Output 49 */ - kTopEarlgreyPinmuxOutselSpiHost1Sck = 53, /**< Peripheral Output 50 */ - kTopEarlgreyPinmuxOutselSpiHost1Csb = 54, /**< Peripheral Output 51 */ - kTopEarlgreyPinmuxOutselFlashCtrlTdo = 55, /**< Peripheral Output 52 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 = 56, /**< Peripheral Output 53 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 = 57, /**< Peripheral Output 54 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 = 58, /**< Peripheral Output 55 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut3 = 59, /**< Peripheral Output 56 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut4 = 60, /**< Peripheral Output 57 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut5 = 61, /**< Peripheral Output 58 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut6 = 62, /**< Peripheral Output 59 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut7 = 63, /**< Peripheral Output 60 */ - kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut8 = 64, /**< Peripheral Output 61 */ - kTopEarlgreyPinmuxOutselPwmAonPwm0 = 65, /**< Peripheral Output 62 */ - kTopEarlgreyPinmuxOutselPwmAonPwm1 = 66, /**< Peripheral Output 63 */ - kTopEarlgreyPinmuxOutselPwmAonPwm2 = 67, /**< Peripheral Output 64 */ - kTopEarlgreyPinmuxOutselPwmAonPwm3 = 68, /**< Peripheral Output 65 */ - kTopEarlgreyPinmuxOutselPwmAonPwm4 = 69, /**< Peripheral Output 66 */ - kTopEarlgreyPinmuxOutselPwmAonPwm5 = 70, /**< Peripheral Output 67 */ - kTopEarlgreyPinmuxOutselOtpCtrlTest0 = 71, /**< Peripheral Output 68 */ - kTopEarlgreyPinmuxOutselSysrstCtrlAonBatDisable = 72, /**< Peripheral Output 69 */ - kTopEarlgreyPinmuxOutselSysrstCtrlAonKey0Out = 73, /**< Peripheral Output 70 */ - kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out = 74, /**< Peripheral Output 71 */ - kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out = 75, /**< Peripheral Output 72 */ - kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut = 76, /**< Peripheral Output 73 */ - kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup = 77, /**< Peripheral Output 74 */ - kTopEarlgreyPinmuxOutselLast = 77, /**< \internal Last valid outsel value */ + kTopEarlgreyPinmuxOutselI2c3Sda = 41, /**< Peripheral Output 38 */ + kTopEarlgreyPinmuxOutselI2c3Scl = 42, /**< Peripheral Output 39 */ + kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 43, /**< Peripheral Output 40 */ + kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 44, /**< Peripheral Output 41 */ + kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 45, /**< Peripheral Output 42 */ + kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 46, /**< Peripheral Output 43 */ + kTopEarlgreyPinmuxOutselUart0Tx = 47, /**< Peripheral Output 44 */ + kTopEarlgreyPinmuxOutselUart1Tx = 48, /**< Peripheral Output 45 */ + kTopEarlgreyPinmuxOutselUart2Tx = 49, /**< Peripheral Output 46 */ + kTopEarlgreyPinmuxOutselUart3Tx = 50, /**< Peripheral Output 47 */ + kTopEarlgreyPinmuxOutselPattgenPda0Tx = 51, /**< Peripheral Output 48 */ + kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 52, /**< Peripheral Output 49 */ + kTopEarlgreyPinmuxOutselPattgenPda1Tx = 53, /**< Peripheral Output 50 */ + kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 54, /**< Peripheral Output 51 */ + kTopEarlgreyPinmuxOutselSpiHost1Sck = 55, /**< Peripheral Output 52 */ + kTopEarlgreyPinmuxOutselSpiHost1Csb = 56, /**< Peripheral Output 53 */ + kTopEarlgreyPinmuxOutselFlashCtrlTdo = 57, /**< Peripheral Output 54 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 = 58, /**< Peripheral Output 55 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 = 59, /**< Peripheral Output 56 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 = 60, /**< Peripheral Output 57 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut3 = 61, /**< Peripheral Output 58 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut4 = 62, /**< Peripheral Output 59 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut5 = 63, /**< Peripheral Output 60 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut6 = 64, /**< Peripheral Output 61 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut7 = 65, /**< Peripheral Output 62 */ + kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut8 = 66, /**< Peripheral Output 63 */ + kTopEarlgreyPinmuxOutselPwmAonPwm0 = 67, /**< Peripheral Output 64 */ + kTopEarlgreyPinmuxOutselPwmAonPwm1 = 68, /**< Peripheral Output 65 */ + kTopEarlgreyPinmuxOutselPwmAonPwm2 = 69, /**< Peripheral Output 66 */ + kTopEarlgreyPinmuxOutselPwmAonPwm3 = 70, /**< Peripheral Output 67 */ + kTopEarlgreyPinmuxOutselPwmAonPwm4 = 71, /**< Peripheral Output 68 */ + kTopEarlgreyPinmuxOutselPwmAonPwm5 = 72, /**< Peripheral Output 69 */ + kTopEarlgreyPinmuxOutselOtpCtrlTest0 = 73, /**< Peripheral Output 70 */ + kTopEarlgreyPinmuxOutselSysrstCtrlAonBatDisable = 74, /**< Peripheral Output 71 */ + kTopEarlgreyPinmuxOutselSysrstCtrlAonKey0Out = 75, /**< Peripheral Output 72 */ + kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out = 76, /**< Peripheral Output 73 */ + kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out = 77, /**< Peripheral Output 74 */ + kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut = 78, /**< Peripheral Output 75 */ + kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup = 79, /**< Peripheral Output 76 */ + kTopEarlgreyPinmuxOutselLast = 79, /**< \internal Last valid outsel value */ } top_earlgrey_pinmux_outsel_t; /** @@ -1725,7 +1765,8 @@ typedef enum top_earlgrey_reset_manager_sw_resets { kTopEarlgreyResetManagerSwResetsI2c0 = 5, /**< */ kTopEarlgreyResetManagerSwResetsI2c1 = 6, /**< */ kTopEarlgreyResetManagerSwResetsI2c2 = 7, /**< */ - kTopEarlgreyResetManagerSwResetsLast = 7, /**< \internal Last valid rstmgr software reset request */ + kTopEarlgreyResetManagerSwResetsI2c3 = 8, /**< */ + kTopEarlgreyResetManagerSwResetsLast = 8, /**< \internal Last valid rstmgr software reset request */ } top_earlgrey_reset_manager_sw_resets_t; /** diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index 9225f62f0544a3..2303d8524723a4 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h @@ -216,6 +216,23 @@ * `TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES`. */ #define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80 +/** + * Peripheral base address for i2c3 in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_I2C3_BASE_ADDR 0x400B0000 + +/** + * Peripheral size for i2c3 in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_I2C3_BASE_ADDR and + * `TOP_EARLGREY_I2C3_BASE_ADDR + TOP_EARLGREY_I2C3_SIZE_BYTES`. + */ +#define TOP_EARLGREY_I2C3_SIZE_BYTES 0x80 /** * Peripheral base address for pattgen in top earlgrey. * diff --git a/rules/const.bzl b/rules/const.bzl index 328b5e27753e2f..7e7ca3436969fe 100644 --- a/rules/const.bzl +++ b/rules/const.bzl @@ -195,6 +195,7 @@ EARLGREY_ALERTS = [ "i2c0_fatal_fault", "i2c1_fatal_fault", "i2c2_fatal_fault", + "i2c3_fatal_fault", "pattgen_fatal_fault", "rv_timer_fatal_fault", "otp_ctrl_fatal_macro_error", @@ -251,7 +252,6 @@ EARLGREY_ALERTS = [ "rv_core_ibex_recov_sw_err", "rv_core_ibex_fatal_hw_err", "rv_core_ibex_recov_hw_err", - "dummy65", "dummy66", "dummy67", "dummy68", diff --git a/sw/device/lib/dif/dif_alert_handler_unittest.cc b/sw/device/lib/dif/dif_alert_handler_unittest.cc index 8f717593f3d784..432444d7089f1e 100644 --- a/sw/device/lib/dif/dif_alert_handler_unittest.cc +++ b/sw/device/lib/dif/dif_alert_handler_unittest.cc @@ -30,7 +30,7 @@ using ::testing::Return; // so if the number of alerts change, the digest will be changed // as well. This process is not yet automated, so the user // must be aware on how to update the value. -static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 65, +static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 66, "The number of alerts have changed."); constexpr int kAlerts = ALERT_HANDLER_PARAM_N_ALERTS; diff --git a/sw/device/lib/dif/dif_rstmgr.c b/sw/device/lib/dif/dif_rstmgr.c index 4dd6140d6ecf27..13558eb39e6a19 100644 --- a/sw/device/lib/dif/dif_rstmgr.c +++ b/sw/device/lib/dif/dif_rstmgr.c @@ -33,7 +33,7 @@ static_assert(kDifRstmgrResetInfoHwReq == (RSTMGR_RESET_INFO_HW_REQ_MASK "kDifRstmgrResetInfoHwReq must match the register definition!"); static_assert( - RSTMGR_PARAM_NUM_SW_RESETS == 8, + RSTMGR_PARAM_NUM_SW_RESETS == 9, "Number of software resets has changed, please update this file!"); // The Reset Manager implementation will have to be updated if the number diff --git a/sw/device/lib/dif/dif_rv_plic_unittest.cc b/sw/device/lib/dif/dif_rv_plic_unittest.cc index a12d660b937607..3b1a00122cbe8f 100644 --- a/sw/device/lib/dif/dif_rv_plic_unittest.cc +++ b/sw/device/lib/dif/dif_rv_plic_unittest.cc @@ -21,7 +21,7 @@ using testing::Test; // If either of these static assertions fail, then the unit-tests for related // API should be revisited. -static_assert(RV_PLIC_PARAM_NUM_SRC == 182, +static_assert(RV_PLIC_PARAM_NUM_SRC == 197, "PLIC instantiation parameters have changed."); static_assert(RV_PLIC_PARAM_NUM_TARGET == 1, "PLIC instantiation parameters have changed."); @@ -50,6 +50,7 @@ class ResetTest : public PlicTest { EXPECT_WRITE32(RV_PLIC_IE0_3_REG_OFFSET, 0); EXPECT_WRITE32(RV_PLIC_IE0_4_REG_OFFSET, 0); EXPECT_WRITE32(RV_PLIC_IE0_5_REG_OFFSET, 0); + EXPECT_WRITE32(RV_PLIC_IE0_6_REG_OFFSET, 0); // Target threshold registers. EXPECT_WRITE32(RV_PLIC_THRESHOLD0_REG_OFFSET, 0); @@ -100,7 +101,8 @@ class IrqTest : public PlicTest { {RV_PLIC_IE0_2_REG_OFFSET, RV_PLIC_IE0_2_E_95_BIT}, {RV_PLIC_IE0_3_REG_OFFSET, RV_PLIC_IE0_3_E_127_BIT}, {RV_PLIC_IE0_4_REG_OFFSET, RV_PLIC_IE0_4_E_159_BIT}, - {RV_PLIC_IE0_5_REG_OFFSET, RV_PLIC_IE0_5_E_181_BIT}, + {RV_PLIC_IE0_5_REG_OFFSET, RV_PLIC_IE0_5_E_191_BIT}, + {RV_PLIC_IE0_6_REG_OFFSET, RV_PLIC_IE0_6_E_196_BIT}, }}; static constexpr std::array kPendingRegisters{{ @@ -109,7 +111,8 @@ class IrqTest : public PlicTest { {RV_PLIC_IP_2_REG_OFFSET, RV_PLIC_IP_2_P_95_BIT}, {RV_PLIC_IP_3_REG_OFFSET, RV_PLIC_IP_3_P_127_BIT}, {RV_PLIC_IP_4_REG_OFFSET, RV_PLIC_IP_4_P_159_BIT}, - {RV_PLIC_IP_5_REG_OFFSET, RV_PLIC_IP_5_P_181_BIT}, + {RV_PLIC_IP_5_REG_OFFSET, RV_PLIC_IP_5_P_191_BIT}, + {RV_PLIC_IP_6_REG_OFFSET, RV_PLIC_IP_6_P_196_BIT}, }}; // Set enable/disable multireg expectations, one bit per call. diff --git a/sw/device/lib/testing/i2c_testutils.c b/sw/device/lib/testing/i2c_testutils.c index 91f22a61dbc24b..9e04c629394a0c 100644 --- a/sw/device/lib/testing/i2c_testutils.c +++ b/sw/device/lib/testing/i2c_testutils.c @@ -88,6 +88,17 @@ static const i2c_pinmux_pins_t kI2cPinmuxPins[] = { .peripheral_in = kTopEarlgreyPinmuxPeripheralInI2c2Scl, .outsel = kTopEarlgreyPinmuxOutselI2c2Scl, }}, + // I2C3. + {.sda = + { + .peripheral_in = kTopEarlgreyPinmuxPeripheralInI2c3Sda, + .outsel = kTopEarlgreyPinmuxOutselI2c3Sda, + }, + .scl = + { + .peripheral_in = kTopEarlgreyPinmuxPeripheralInI2c3Scl, + .outsel = kTopEarlgreyPinmuxOutselI2c3Scl, + }}, }; /** @@ -134,6 +145,20 @@ static status_t map_platform_to_pins(i2c_pinmux_platform_id_t platform, case 2: // I2C2 uses the same pins as CW310 PMOD TRY(map_platform_to_pins(I2cPinmuxPlatformIdCw310Pmod, i2c_id, pins)); break; + case 3: + *pins = (i2c_platform_pins_t){ + .sda = + { + .mio_out = kTopEarlgreyPinmuxMioOutIoc11, + .insel = kTopEarlgreyPinmuxInselIoc11, + }, + .scl = + { + .mio_out = kTopEarlgreyPinmuxMioOutIoc10, + .insel = kTopEarlgreyPinmuxInselIoc10, + }, + }; + break; default: TRY_CHECK(false, "invalid i2c_id: %0d", i2c_id); break; diff --git a/sw/device/lib/testing/json/pinmux.h b/sw/device/lib/testing/json/pinmux.h index ac30f6229b74c3..d58b6706e835b1 100644 --- a/sw/device/lib/testing/json/pinmux.h +++ b/sw/device/lib/testing/json/pinmux.h @@ -58,6 +58,8 @@ extern "C" { value(_, I2c1Scl, kTopEarlgreyPinmuxPeripheralInI2c1Scl) \ value(_, I2c2Sda, kTopEarlgreyPinmuxPeripheralInI2c2Sda) \ value(_, I2c2Scl, kTopEarlgreyPinmuxPeripheralInI2c2Scl) \ + value(_, I2c3Sda, kTopEarlgreyPinmuxPeripheralInI2c3Sda) \ + value(_, I2c3Scl, kTopEarlgreyPinmuxPeripheralInI2c3Scl) \ value(_, SpiHost1Sd0, kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0) \ value(_, SpiHost1Sd1, kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1) \ value(_, SpiHost1Sd2, kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2) \ @@ -226,6 +228,8 @@ C_ONLY(UJSON_SERDE_ENUM(PinmuxMioOut, pinmux_mio_out_t, TOP_EARLGREY_PINMUX_MIO_ value(_, I2c1Scl, kTopEarlgreyPinmuxOutselI2c1Scl) \ value(_, I2c2Sda, kTopEarlgreyPinmuxOutselI2c2Sda) \ value(_, I2c2Scl, kTopEarlgreyPinmuxOutselI2c2Scl) \ + value(_, I2c3Sda, kTopEarlgreyPinmuxOutselI2c3Sda) \ + value(_, I2c3Scl, kTopEarlgreyPinmuxOutselI2c3Scl) \ value(_, SpiHost1Sd0, kTopEarlgreyPinmuxOutselSpiHost1Sd0) \ value(_, SpiHost1Sd1, kTopEarlgreyPinmuxOutselSpiHost1Sd1) \ value(_, SpiHost1Sd2, kTopEarlgreyPinmuxOutselSpiHost1Sd2) \ diff --git a/sw/device/tests/alert_handler_lpg_reset_toggle.c b/sw/device/tests/alert_handler_lpg_reset_toggle.c index 0a4717413493ae..fc7ee855b465b0 100644 --- a/sw/device/tests/alert_handler_lpg_reset_toggle.c +++ b/sw/device/tests/alert_handler_lpg_reset_toggle.c @@ -47,6 +47,7 @@ static dif_usbdev_t usbdev; static dif_i2c_t i2c0; static dif_i2c_t i2c1; static dif_i2c_t i2c2; +static dif_i2c_t i2c3; static dif_rv_core_ibex_t ibex; static const uint32_t kPlicTarget = kTopEarlgreyPlicTargetIbex0; @@ -85,6 +86,9 @@ static void init_peripherals(void) { CHECK_DIF_OK( dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR), &i2c2)); + CHECK_DIF_OK( + dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C3_BASE_ADDR), &i2c3)); + mmio_region_t ibex_addr = mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR); CHECK_DIF_OK(dif_rv_core_ibex_init(ibex_addr, &ibex)); @@ -106,6 +110,7 @@ static const uint32_t usbdev_alerts[] = {kTopEarlgreyAlertIdUsbdevFatalFault}; static const uint32_t i2c0_alerts[] = {kTopEarlgreyAlertIdI2c0FatalFault}; static const uint32_t i2c1_alerts[] = {kTopEarlgreyAlertIdI2c1FatalFault}; static const uint32_t i2c2_alerts[] = {kTopEarlgreyAlertIdI2c2FatalFault}; +static const uint32_t i2c3_alerts[] = {kTopEarlgreyAlertIdI2c3FatalFault}; static const uint32_t num_spihost0_alerts = ARRAYSIZE(spihost0_alerts); static const uint32_t num_spihost1_alerts = ARRAYSIZE(spihost1_alerts); @@ -114,10 +119,12 @@ static const uint32_t num_spidev_alerts = ARRAYSIZE(spidev_alerts); static const uint32_t num_i2c0_alerts = ARRAYSIZE(i2c0_alerts); static const uint32_t num_i2c1_alerts = ARRAYSIZE(i2c1_alerts); static const uint32_t num_i2c2_alerts = ARRAYSIZE(i2c2_alerts); +static const uint32_t num_i2c3_alerts = ARRAYSIZE(i2c3_alerts); -static const size_t num_alerts = - num_spihost0_alerts + num_spihost1_alerts + num_usbdev_alerts + - num_i2c0_alerts + num_i2c1_alerts + num_i2c2_alerts + num_spidev_alerts; +static const size_t num_alerts = num_spihost0_alerts + num_spihost1_alerts + + num_usbdev_alerts + num_i2c0_alerts + + num_i2c1_alerts + num_i2c2_alerts + + num_i2c3_alerts + num_spidev_alerts; /** * A structure to keep the info for peripheral IPs @@ -207,6 +214,14 @@ static const test_t kPeripherals[] = { .num_alert_peri = num_i2c2_alerts, .reset_index = kTopEarlgreyResetManagerSwResetsI2c2, }, + { + .name = "I2C3", + .base = TOP_EARLGREY_I2C3_BASE_ADDR, + .dif = &i2c3, + .alert_ids = i2c3_alerts, + .num_alert_peri = num_i2c3_alerts, + .reset_index = kTopEarlgreyResetManagerSwResetsI2c3, + }, }; /** diff --git a/sw/device/tests/autogen/alert_test.c b/sw/device/tests/autogen/alert_test.c index f68c8aa5d35b13..1277fea259cded 100644 --- a/sw/device/tests/autogen/alert_test.c +++ b/sw/device/tests/autogen/alert_test.c @@ -68,6 +68,7 @@ static dif_hmac_t hmac; static dif_i2c_t i2c0; static dif_i2c_t i2c1; static dif_i2c_t i2c2; +static dif_i2c_t i2c3; static dif_keymgr_t keymgr; static dif_kmac_t kmac; static dif_lc_ctrl_t lc_ctrl; @@ -145,6 +146,9 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C3_BASE_ADDR); + CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c3)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR); CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr)); @@ -491,6 +495,21 @@ static void trigger_alert_test(void) { &alert_handler, exp_alert)); } + // Write i2c's alert_test reg and check alert_cause. + for (dif_i2c_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_i2c_alert_force(&i2c3, kDifI2cAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopEarlgreyAlertIdI2c3FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + // Write keymgr's alert_test reg and check alert_cause. for (dif_keymgr_alert_t i = 0; i < 2; ++i) { CHECK_DIF_OK(dif_keymgr_alert_force(&keymgr, kDifKeymgrAlertRecovOperationErr + i)); diff --git a/sw/device/tests/autogen/plic_all_irqs_test.c b/sw/device/tests/autogen/plic_all_irqs_test.c index 66ba2ed5ce9669..8d132c2921c934 100644 --- a/sw/device/tests/autogen/plic_all_irqs_test.c +++ b/sw/device/tests/autogen/plic_all_irqs_test.c @@ -113,6 +113,10 @@ static dif_i2c_t i2c1; static dif_i2c_t i2c2; #endif +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +static dif_i2c_t i2c3; +#endif + #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static dif_keymgr_t keymgr; #endif @@ -682,6 +686,30 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + case kTopEarlgreyPlicPeripheralI2c3: { + dif_i2c_irq_t irq = (dif_i2c_irq_t)( + plic_irq_id - + (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdI2c3FmtThreshold); + CHECK(irq == i2c_irq_expected, + "Incorrect i2c3 IRQ triggered: exp = %d, obs = %d", + i2c_irq_expected, irq); + i2c_irq_serviced = irq; + + dif_i2c_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c3, &snapshot)); + CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq), + "Only i2c3 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + // TODO: Check Interrupt type then clear INTR_TEST if needed. + CHECK_DIF_OK(dif_i2c_irq_force(&i2c3, irq, false)); + CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c3, irq)); + break; + } +#endif + #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralKeymgr: { dif_keymgr_irq_t irq = (dif_keymgr_irq_t)( @@ -1170,6 +1198,11 @@ static void peripherals_init(void) { CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2)); #endif +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C3_BASE_ADDR); + CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c3)); +#endif + #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR); CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr)); @@ -1315,6 +1348,10 @@ static void peripheral_irqs_clear(void) { CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c2)); #endif +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c3)); +#endif + #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_keymgr_irq_acknowledge_all(&keymgr)); #endif @@ -1560,6 +1597,11 @@ static void peripheral_irqs_enable(void) { dif_i2c_irq_restore_all(&i2c2, &i2c_irqs)); #endif +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK( + dif_i2c_irq_restore_all(&i2c3, &i2c_irqs)); +#endif + #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK( dif_keymgr_irq_restore_all(&keymgr, &keymgr_irqs)); @@ -1864,6 +1906,21 @@ static void peripheral_irqs_trigger(void) { } #endif +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEarlgreyPlicPeripheralI2c3; + for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; + irq <= kDifI2cIrqHostTimeout; ++irq) { + i2c_irq_expected = irq; + LOG_INFO("Triggering i2c3 IRQ %d.", irq); + CHECK_DIF_OK(dif_i2c_irq_force(&i2c3, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from i2c3 is serviced.", irq); + } +#endif + #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralKeymgr; for (dif_keymgr_irq_t irq = kDifKeymgrIrqOpDone; diff --git a/sw/device/tests/i2c_target_test.c b/sw/device/tests/i2c_target_test.c index 8218f1db9f196e..3a00744e615852 100644 --- a/sw/device/tests/i2c_target_test.c +++ b/sw/device/tests/i2c_target_test.c @@ -87,9 +87,9 @@ static status_t i2c_detach_instance(dif_i2c_t *i2c, dif_pinmux_t *pinmux, static status_t i2c_configure_instance(dif_i2c_t *i2c, dif_pinmux_t *pinmux, uint8_t i2c_instance) { - const uintptr_t kI2cBaseAddrTable[] = {TOP_EARLGREY_I2C0_BASE_ADDR, - TOP_EARLGREY_I2C1_BASE_ADDR, - TOP_EARLGREY_I2C2_BASE_ADDR}; + const uintptr_t kI2cBaseAddrTable[] = { + TOP_EARLGREY_I2C0_BASE_ADDR, TOP_EARLGREY_I2C1_BASE_ADDR, + TOP_EARLGREY_I2C2_BASE_ADDR, TOP_EARLGREY_I2C3_BASE_ADDR}; TRY_CHECK(i2c_instance < ARRAYSIZE(kI2cBaseAddrTable)); mmio_region_t base_addr = diff --git a/sw/device/tests/pmod/i2c_host_eeprom_test.c b/sw/device/tests/pmod/i2c_host_eeprom_test.c index 8314961b42d072..4fc915307c9faa 100644 --- a/sw/device/tests/pmod/i2c_host_eeprom_test.c +++ b/sw/device/tests/pmod/i2c_host_eeprom_test.c @@ -147,9 +147,9 @@ static status_t write_read_page_with_irq(dif_i2c_t *i2c) { static status_t i2c_configure(dif_i2c_t *i2c, dif_pinmux_t *pinmux, uint8_t i2c_instance, i2c_pinmux_platform_id_t platform) { - const uintptr_t kI2cBaseAddrTable[] = {TOP_EARLGREY_I2C0_BASE_ADDR, - TOP_EARLGREY_I2C1_BASE_ADDR, - TOP_EARLGREY_I2C2_BASE_ADDR}; + const uintptr_t kI2cBaseAddrTable[] = { + TOP_EARLGREY_I2C0_BASE_ADDR, TOP_EARLGREY_I2C1_BASE_ADDR, + TOP_EARLGREY_I2C2_BASE_ADDR, TOP_EARLGREY_I2C3_BASE_ADDR}; TRY_CHECK(i2c_instance < ARRAYSIZE(kI2cBaseAddrTable)); mmio_region_t base_addr = diff --git a/sw/device/tests/pmod/i2c_host_fram_test.c b/sw/device/tests/pmod/i2c_host_fram_test.c index 40bc23236665d9..b1e49f6d5176cc 100644 --- a/sw/device/tests/pmod/i2c_host_fram_test.c +++ b/sw/device/tests/pmod/i2c_host_fram_test.c @@ -176,9 +176,9 @@ static status_t throughput(dif_i2c_t *i2c, uint32_t expected_kbps) { static status_t i2c_configure(dif_i2c_t *i2c, dif_pinmux_t *pinmux, uint8_t i2c_instance, i2c_pinmux_platform_id_t platform) { - const uintptr_t kI2cBaseAddrTable[] = {TOP_EARLGREY_I2C0_BASE_ADDR, - TOP_EARLGREY_I2C1_BASE_ADDR, - TOP_EARLGREY_I2C2_BASE_ADDR}; + const uintptr_t kI2cBaseAddrTable[] = { + TOP_EARLGREY_I2C0_BASE_ADDR, TOP_EARLGREY_I2C1_BASE_ADDR, + TOP_EARLGREY_I2C2_BASE_ADDR, TOP_EARLGREY_I2C3_BASE_ADDR}; TRY_CHECK(i2c_instance < ARRAYSIZE(kI2cBaseAddrTable)); mmio_region_t base_addr = diff --git a/sw/device/tests/power_virus_systemtest.c b/sw/device/tests/power_virus_systemtest.c index f2c0856b466369..db551af1f6e990 100644 --- a/sw/device/tests/power_virus_systemtest.c +++ b/sw/device/tests/power_virus_systemtest.c @@ -70,6 +70,7 @@ static dif_otbn_t otbn; static dif_i2c_t i2c_0; static dif_i2c_t i2c_1; static dif_i2c_t i2c_2; +static dif_i2c_t i2c_3; static dif_spi_device_handle_t spi_device; static dif_spi_host_t spi_host_0; static dif_spi_host_t spi_host_1; @@ -81,7 +82,7 @@ static dif_pwm_t pwm; static dif_flash_ctrl_state_t flash_ctrl; static dif_rv_plic_t rv_plic; -static const dif_i2c_t *i2c_handles[] = {&i2c_0, &i2c_1, &i2c_2}; +static const dif_i2c_t *i2c_handles[] = {&i2c_0, &i2c_1, &i2c_2, &i2c_3}; static const dif_uart_t *uart_handles[] = {&uart_1, &uart_2, &uart_3}; static dif_kmac_operation_state_t kmac_operation_state; static const dif_pattgen_channel_t pattgen_channels[] = {kDifPattgenChannel0, @@ -141,9 +142,12 @@ enum { kI2c1DeviceAddress1 = 0x44, kI2c2DeviceAddress0 = 0x55, kI2c2DeviceAddress1 = 0x66, + kI2c3DeviceAddress0 = 0x77, + kI2c3DeviceAddress1 = 0x88, kI2c0TargetAddress = 0x01, kI2c1TargetAddress = 0x02, kI2c2TargetAddress = 0x03, + kI2c3TargetAddress = 0x04, /** * UART parameters. */ @@ -378,6 +382,8 @@ static void init_peripheral_handles(void) { dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C1_BASE_ADDR), &i2c_1)); CHECK_DIF_OK( dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR), &i2c_2)); + CHECK_DIF_OK( + dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C3_BASE_ADDR), &i2c_3)); CHECK_DIF_OK(dif_spi_device_init_handle( mmio_region_from_addr(TOP_EARLGREY_SPI_DEVICE_BASE_ADDR), &spi_device)); CHECK_DIF_OK(dif_spi_host_init( @@ -485,6 +491,20 @@ static void configure_pinmux(void) { CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopEarlgreyPinmuxMioOutIob12, kTopEarlgreyPinmuxOutselI2c2Sda)); + // I2C3: + // SCL on IOC10 + // SDA on IOC11 + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, + kTopEarlgreyPinmuxPeripheralInI2c3Scl, + kTopEarlgreyPinmuxInselIoc10)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, + kTopEarlgreyPinmuxPeripheralInI2c3Sda, + kTopEarlgreyPinmuxInselIoc11)); + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopEarlgreyPinmuxMioOutIoc10, + kTopEarlgreyPinmuxOutselI2c3Scl)); + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopEarlgreyPinmuxMioOutIoc11, + kTopEarlgreyPinmuxOutselI2c3Sda)); + // PATTGEN: // Channel 0 PDA on IOR0 // Channel 0 PCL on IOR1 @@ -1255,6 +1275,7 @@ static void max_power(void) { mmio_region_write32(i2c_0.base_addr, I2C_CTRL_REG_OFFSET, i2c_ctrl_reg); mmio_region_write32(i2c_1.base_addr, I2C_CTRL_REG_OFFSET, i2c_ctrl_reg); mmio_region_write32(i2c_2.base_addr, I2C_CTRL_REG_OFFSET, i2c_ctrl_reg); + mmio_region_write32(i2c_3.base_addr, I2C_CTRL_REG_OFFSET, i2c_ctrl_reg); // Issue OTBN start command. CHECK_STATUS_OK(otbn_testutils_rsa_modexp_f4_start( @@ -1444,6 +1465,7 @@ bool test_main(void) { configure_i2c(&i2c_0, kI2c0DeviceAddress0, kI2c0DeviceAddress1); configure_i2c(&i2c_1, kI2c1DeviceAddress0, kI2c1DeviceAddress1); configure_i2c(&i2c_2, kI2c2DeviceAddress0, kI2c2DeviceAddress1); + configure_i2c(&i2c_3, kI2c3DeviceAddress0, kI2c3DeviceAddress1); configure_spi_host(&spi_host_0, /*enable=*/true); // We don't enable SPI host 1 just yet, as we want to pre-load its FIFO with // data before enabling it at the last moment, to initiate max power draw. diff --git a/sw/device/tests/rstmgr_alert_info_test.c b/sw/device/tests/rstmgr_alert_info_test.c index 684e42ab263579..025d91e1d3c699 100644 --- a/sw/device/tests/rstmgr_alert_info_test.c +++ b/sw/device/tests/rstmgr_alert_info_test.c @@ -101,7 +101,7 @@ static dif_rv_plic_t plic; static dif_rv_core_ibex_t rv_core_ibex; static dif_aon_timer_t aon_timer; static dif_pwrmgr_t pwrmgr; -static dif_i2c_t i2c0, i2c1, i2c2; +static dif_i2c_t i2c0, i2c1, i2c2, i2c3; typedef struct node { const char *name; @@ -323,7 +323,7 @@ static void print_alert_cause(alert_handler_testutils_info_t info) { } /* - * Configure alert for i2c0..i2c2 s.t. + * Configure alert for i2c0..i2c3 s.t. * .alert class = class A * .escalation phase0,1 * .disable ping timer @@ -332,7 +332,7 @@ static void prgm_alert_handler_round1(void) { dif_alert_handler_class_t alert_class = kDifAlertHandlerClassA; for (int i = kTopEarlgreyAlertPeripheralI2c0; - i < kTopEarlgreyAlertPeripheralI2c2 + 1; ++i) { + i < kTopEarlgreyAlertPeripheralI2c3 + 1; ++i) { CHECK_DIF_OK(dif_alert_handler_configure_alert( &alert_handler, test_node[i].alert, test_node[i].class, /*enabled=*/kDifToggleEnabled, /*locked=*/kDifToggleEnabled)); @@ -520,6 +520,8 @@ static void peripheral_init(void) { dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C1_BASE_ADDR), &i2c1)); CHECK_DIF_OK( dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR), &i2c2)); + CHECK_DIF_OK( + dif_i2c_init(mmio_region_from_addr(TOP_EARLGREY_I2C3_BASE_ADDR), &i2c3)); CHECK_DIF_OK(dif_uart_init( mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR), &uart0)); CHECK_DIF_OK(dif_uart_init( @@ -669,6 +671,12 @@ static node_t test_node[kTopEarlgreyAlertPeripheralLast] = { .alert = kTopEarlgreyAlertIdI2c2FatalFault, .class = kDifAlertHandlerClassA, }, + [kTopEarlgreyAlertPeripheralI2c3] = + { + .name = "I2C3", + .alert = kTopEarlgreyAlertIdI2c3FatalFault, + .class = kDifAlertHandlerClassA, + }, }; static void init_expected_cause(void) { diff --git a/sw/device/tests/rstmgr_sw_rst_ctrl_test.c b/sw/device/tests/rstmgr_sw_rst_ctrl_test.c index 6357ea01dc4233..3dd99242746cae 100644 --- a/sw/device/tests/rstmgr_sw_rst_ctrl_test.c +++ b/sw/device/tests/rstmgr_sw_rst_ctrl_test.c @@ -42,6 +42,7 @@ OTTF_DEFINE_TEST_CONFIG(); * // 5 | I2C0 | TIMING0 | 0x0 | 0x8b00cfe * // 6 | I2C1 | TIMING1 | 0x0 | 0x114010d8 * // 7 | I2C2 | TIMING2 | 0x0 | 0x19ec1595 + * // 8 | I2C3 | TIMING3 | 0x0 | 0x0737032c * * 'test register' is a rw type register under each peripheral device. * These registers are programmed with arbitrary values ('prgm value') before @@ -130,6 +131,14 @@ static void i2c2_config(void *dif) { CHECK_DIF_OK(dif_i2c_configure(dif, cfg)); } +static void i2c3_config(void *dif) { + dif_i2c_config_t cfg = { + .data_signal_hold_cycles = 1847, + .data_signal_setup_cycles = 812, + }; + CHECK_DIF_OK(dif_i2c_configure(dif, cfg)); +} + static dif_spi_device_handle_t spi_dev; static dif_spi_host_t spi_host0; static dif_spi_host_t spi_host1; @@ -137,6 +146,7 @@ static dif_usbdev_t usbdev; static dif_i2c_t i2c0; static dif_i2c_t i2c1; static dif_i2c_t i2c2; +static dif_i2c_t i2c3; typedef struct test { /** @@ -248,6 +258,16 @@ static const test_t kPeripherals[] = { .program_val = 0x19ec1595, .reset_index = kTopEarlgreyResetManagerSwResetsI2c2, }, + { + .name = "I2C3", + .base = TOP_EARLGREY_I2C3_BASE_ADDR, + .offset = I2C_TIMING3_REG_OFFSET, + .dif = &i2c3, + .init = i2c_init, + .config = i2c3_config, + .program_val = 0x0737032c, + .reset_index = kTopEarlgreyResetManagerSwResetsI2c3, + }, }; /** diff --git a/sw/device/tests/sim_dv/all_escalation_resets_test.c b/sw/device/tests/sim_dv/all_escalation_resets_test.c index 89d9baf963f779..3e49b582f36e68 100644 --- a/sw/device/tests/sim_dv/all_escalation_resets_test.c +++ b/sw/device/tests/sim_dv/all_escalation_resets_test.c @@ -206,6 +206,7 @@ static const char *hmac_inst_name = "hmac"; static const char *i2c0_inst_name = "i2c0"; static const char *i2c1_inst_name = "i2c1"; static const char *i2c2_inst_name = "i2c2"; +static const char *i2c3_inst_name = "i2c3"; static const char *keymgr_inst_name = "keymgr"; static const char *kmac_inst_name = "kmac"; // TODO: test lc_ctrl fatal_state, alert 17. @@ -837,6 +838,10 @@ static void execute_test(const dif_aon_timer_t *aon_timer) { fault_checker_t fc = {trivial_fault_checker, i2c2_inst_name, we_check}; fault_checker = fc; } break; + case kTopEarlgreyAlertIdI2c3FatalFault: { + fault_checker_t fc = {trivial_fault_checker, i2c3_inst_name, we_check}; + fault_checker = fc; + } break; case kTopEarlgreyAlertIdKeymgrFatalFaultErr: { fault_checker_t fc = {trivial_fault_checker, keymgr_inst_name, we_check}; // TODO(#14518) diff --git a/sw/device/tests/sim_dv/i2c_device_tx_rx_test.c b/sw/device/tests/sim_dv/i2c_device_tx_rx_test.c index 68de535a313514..ff4cf7627f4de9 100644 --- a/sw/device/tests/sim_dv/i2c_device_tx_rx_test.c +++ b/sw/device/tests/sim_dv/i2c_device_tx_rx_test.c @@ -107,7 +107,15 @@ const i2c_conf_t i2c_configuration[] = { kTopEarlgreyPlicIrqIdI2c2TxOverflow, kTopEarlgreyPlicIrqIdI2c2AcqFull, kTopEarlgreyPlicIrqIdI2c2UnexpStop, - kTopEarlgreyPlicIrqIdI2c2HostTimeout}}}; + kTopEarlgreyPlicIrqIdI2c2HostTimeout}}, + {.base_addr = TOP_EARLGREY_I2C3_BASE_ADDR, + .i2c_irq_fmt_threshold_id = kTopEarlgreyPlicIrqIdI2c3FmtThreshold, + .plic_irqs = {kTopEarlgreyPlicIrqIdI2c3CmdComplete, + kTopEarlgreyPlicIrqIdI2c3TxStretch, + kTopEarlgreyPlicIrqIdI2c3TxOverflow, + kTopEarlgreyPlicIrqIdI2c3AcqFull, + kTopEarlgreyPlicIrqIdI2c3UnexpStop, + kTopEarlgreyPlicIrqIdI2c3HostTimeout}}}; /** * Provides external irq handling for this test. diff --git a/sw/device/tests/sim_dv/i2c_host_tx_rx_test.c b/sw/device/tests/sim_dv/i2c_host_tx_rx_test.c index b99897e4e8cb19..2d3ad0843f2f63 100644 --- a/sw/device/tests/sim_dv/i2c_host_tx_rx_test.c +++ b/sw/device/tests/sim_dv/i2c_host_tx_rx_test.c @@ -221,6 +221,37 @@ void config_i2c_with_index(void) { kTopEarlgreyPinmuxMioOutIob12, kTopEarlgreyPinmuxOutselI2c2Sda)); break; + case 3: + i2c_base_addr = TOP_EARLGREY_I2C3_BASE_ADDR; + i2c_irq_fmt_threshold_id = kTopEarlgreyPlicIrqIdI2c3FmtThreshold; + + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3FmtThreshold; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3RxThreshold; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3FmtOverflow; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3RxOverflow; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3Nak; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3SclInterference; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3SdaInterference; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3StretchTimeout; + // TODO, leave out sda unstable for now until DV side is improved. Sda + // instability during the high cycle is intentionally being introduced + // right now. + // plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3SdaUnstable; + plic_irqs[i++] = kTopEarlgreyPlicIrqIdI2c3CmdComplete; + + CHECK_DIF_OK(dif_pinmux_input_select( + &pinmux, kTopEarlgreyPinmuxPeripheralInI2c3Scl, + kTopEarlgreyPinmuxInselIoc10)); + CHECK_DIF_OK(dif_pinmux_input_select( + &pinmux, kTopEarlgreyPinmuxPeripheralInI2c3Sda, + kTopEarlgreyPinmuxInselIoc11)); + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, + kTopEarlgreyPinmuxMioOutIoc10, + kTopEarlgreyPinmuxOutselI2c3Scl)); + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, + kTopEarlgreyPinmuxMioOutIoc11, + kTopEarlgreyPinmuxOutselI2c3Sda)); + break; default: LOG_FATAL("Unsupported i2c index %d", kI2cIdx); } diff --git a/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs b/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs index 21c0c0fbf71072..4188302244fd87 100644 --- a/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs +++ b/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs @@ -51,26 +51,28 @@ with_unknown! { I2c1Scl = 35, I2c2Sda = 36, I2c2Scl = 37, - SpiHost1Sd0 = 38, - SpiHost1Sd1 = 39, - SpiHost1Sd2 = 40, - SpiHost1Sd3 = 41, - Uart0Rx = 42, - Uart1Rx = 43, - Uart2Rx = 44, - Uart3Rx = 45, - SpiDeviceTpmCsb = 46, - FlashCtrlTck = 47, - FlashCtrlTms = 48, - FlashCtrlTdi = 49, - SysrstCtrlAonAcPresent = 50, - SysrstCtrlAonKey0In = 51, - SysrstCtrlAonKey1In = 52, - SysrstCtrlAonKey2In = 53, - SysrstCtrlAonPwrbIn = 54, - SysrstCtrlAonLidOpen = 55, - UsbdevSense = 56, - End = 57, + I2c3Sda = 38, + I2c3Scl = 39, + SpiHost1Sd0 = 40, + SpiHost1Sd1 = 41, + SpiHost1Sd2 = 42, + SpiHost1Sd3 = 43, + Uart0Rx = 44, + Uart1Rx = 45, + Uart2Rx = 46, + Uart3Rx = 47, + SpiDeviceTpmCsb = 48, + FlashCtrlTck = 49, + FlashCtrlTms = 50, + FlashCtrlTdi = 51, + SysrstCtrlAonAcPresent = 52, + SysrstCtrlAonKey0In = 53, + SysrstCtrlAonKey1In = 54, + SysrstCtrlAonKey2In = 55, + SysrstCtrlAonPwrbIn = 56, + SysrstCtrlAonLidOpen = 57, + UsbdevSense = 58, + End = 59, } pub enum PinmuxInsel: u32 [default = Self::End] { @@ -219,44 +221,46 @@ with_unknown! { I2c1Scl = 38, I2c2Sda = 39, I2c2Scl = 40, - SpiHost1Sd0 = 41, - SpiHost1Sd1 = 42, - SpiHost1Sd2 = 43, - SpiHost1Sd3 = 44, - Uart0Tx = 45, - Uart1Tx = 46, - Uart2Tx = 47, - Uart3Tx = 48, - PattgenPda0Tx = 49, - PattgenPcl0Tx = 50, - PattgenPda1Tx = 51, - PattgenPcl1Tx = 52, - SpiHost1Sck = 53, - SpiHost1Csb = 54, - FlashCtrlTdo = 55, - SensorCtrlAonAstDebugOut0 = 56, - SensorCtrlAonAstDebugOut1 = 57, - SensorCtrlAonAstDebugOut2 = 58, - SensorCtrlAonAstDebugOut3 = 59, - SensorCtrlAonAstDebugOut4 = 60, - SensorCtrlAonAstDebugOut5 = 61, - SensorCtrlAonAstDebugOut6 = 62, - SensorCtrlAonAstDebugOut7 = 63, - SensorCtrlAonAstDebugOut8 = 64, - PwmAonPwm0 = 65, - PwmAonPwm1 = 66, - PwmAonPwm2 = 67, - PwmAonPwm3 = 68, - PwmAonPwm4 = 69, - PwmAonPwm5 = 70, - OtpCtrlTest0 = 71, - SysrstCtrlAonBatDisable = 72, - SysrstCtrlAonKey0Out = 73, - SysrstCtrlAonKey1Out = 74, - SysrstCtrlAonKey2Out = 75, - SysrstCtrlAonPwrbOut = 76, - SysrstCtrlAonZ3Wakeup = 77, - End = 78, + I2c3Sda = 41, + I2c3Scl = 42, + SpiHost1Sd0 = 43, + SpiHost1Sd1 = 44, + SpiHost1Sd2 = 45, + SpiHost1Sd3 = 46, + Uart0Tx = 47, + Uart1Tx = 48, + Uart2Tx = 49, + Uart3Tx = 50, + PattgenPda0Tx = 51, + PattgenPcl0Tx = 52, + PattgenPda1Tx = 53, + PattgenPcl1Tx = 54, + SpiHost1Sck = 55, + SpiHost1Csb = 56, + FlashCtrlTdo = 57, + SensorCtrlAonAstDebugOut0 = 58, + SensorCtrlAonAstDebugOut1 = 59, + SensorCtrlAonAstDebugOut2 = 60, + SensorCtrlAonAstDebugOut3 = 61, + SensorCtrlAonAstDebugOut4 = 62, + SensorCtrlAonAstDebugOut5 = 63, + SensorCtrlAonAstDebugOut6 = 64, + SensorCtrlAonAstDebugOut7 = 65, + SensorCtrlAonAstDebugOut8 = 66, + PwmAonPwm0 = 67, + PwmAonPwm1 = 68, + PwmAonPwm2 = 69, + PwmAonPwm3 = 70, + PwmAonPwm4 = 71, + PwmAonPwm5 = 72, + OtpCtrlTest0 = 73, + SysrstCtrlAonBatDisable = 74, + SysrstCtrlAonKey0Out = 75, + SysrstCtrlAonKey1Out = 76, + SysrstCtrlAonKey2Out = 77, + SysrstCtrlAonPwrbOut = 78, + SysrstCtrlAonZ3Wakeup = 79, + End = 80, } pub enum DirectPads: u32 [default = Self::End] { diff --git a/sw/host/opentitanlib/src/otp/alert_handler.rs b/sw/host/opentitanlib/src/otp/alert_handler.rs index d9c6011583f8db..dcf0c5cafafa82 100644 --- a/sw/host/opentitanlib/src/otp/alert_handler.rs +++ b/sw/host/opentitanlib/src/otp/alert_handler.rs @@ -372,7 +372,7 @@ mod test { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, - 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, ], en: [ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -384,7 +384,7 @@ mod test { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, ], class: [ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -396,7 +396,7 @@ mod test { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, ], loc_regwen: [ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, diff --git a/sw/host/opentitanlib/src/otp/alert_handler_regs.rs b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs index 4bf11df79e1de0..7ec81122a84a33 100644 --- a/sw/host/opentitanlib/src/otp/alert_handler_regs.rs +++ b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs @@ -2,10 +2,10 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -/* automatically generated by rust-bindgen 0.60.1 */ +/* automatically generated by rust-bindgen 0.68.1 */ -pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 65; -pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 22; +pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 66; +pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 25; pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5; pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32; pub const ALERT_HANDLER_PARAM_ACCU_CNT_DW: u32 = 16; @@ -58,7 +58,7 @@ pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET: u32 = 20; pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 65; +pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 66; pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET: u32 = 24; pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; @@ -254,206 +254,212 @@ pub const ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET: u32 = 280; pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_REGWEN_65_REG_OFFSET: u32 = 284; +pub const ALERT_HANDLER_ALERT_REGWEN_65_REG_RESVAL: u32 = 1; +pub const ALERT_HANDLER_ALERT_REGWEN_65_EN_65_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 65; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 284; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 66; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 288; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 288; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 292; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 292; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 296; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 296; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 300; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 300; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 304; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 304; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 308; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 308; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 312; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 312; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 316; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 316; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 320; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 320; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 324; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 324; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 328; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 328; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 332; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 332; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 336; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 336; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 340; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 340; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 344; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 344; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 348; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 348; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 352; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 352; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 356; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 356; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 360; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 360; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 364; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 364; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 368; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 368; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 372; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 372; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 376; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 376; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 380; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 380; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 384; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 384; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 388; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 388; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 392; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 392; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 396; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 396; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 400; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 400; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 404; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 404; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 408; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 408; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 412; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 412; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 416; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 416; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 420; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 420; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 424; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 424; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 428; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 428; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 432; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 432; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 436; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 436; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 440; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 440; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 444; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 444; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 448; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 448; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 452; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 452; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 456; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 456; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 460; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 460; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 464; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 464; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 468; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 468; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 472; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 472; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 476; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 476; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 480; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 480; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 484; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 484; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 488; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 488; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 492; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 492; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 496; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 496; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 500; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 500; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 504; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 504; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 508; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 508; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 512; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 512; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 516; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 516; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 520; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 520; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 524; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 524; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 528; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 528; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 532; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 532; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 536; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 536; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 540; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: u32 = 540; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: u32 = 544; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_OFFSET: u32 = 548; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_EN_A_65_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH: u32 = 2; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 65; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 544; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 66; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 552; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET: u32 = 0; @@ -461,508 +467,515 @@ pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB: u32 = 1; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC: u32 = 2; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 548; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 556; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 552; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 560; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 556; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 564; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 560; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 568; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 564; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 572; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 568; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 576; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 572; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 580; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 576; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 584; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 580; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 588; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 584; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 592; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 588; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 596; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 592; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 600; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 596; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 604; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 600; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 608; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 604; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 612; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 608; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 616; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 612; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 620; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 616; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 624; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 620; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 628; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 624; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 632; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 628; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 636; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 632; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 640; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 636; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 644; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 640; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 648; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 644; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 652; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 648; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 656; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 652; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 660; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 656; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 664; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 660; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 668; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 664; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 672; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 668; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 676; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 672; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 680; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 676; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 684; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 680; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 688; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 684; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 692; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 688; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 696; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 692; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 700; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 696; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 704; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 700; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 708; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 704; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 712; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 708; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 716; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 712; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 720; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 716; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 724; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 720; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 728; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 724; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 732; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 728; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 736; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 732; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 740; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 736; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 744; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 740; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 748; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 744; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 752; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 748; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 756; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 752; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 760; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 756; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 764; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 760; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 768; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 764; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 772; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 768; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 776; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 772; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 780; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 776; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 784; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 780; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 788; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 784; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 792; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 788; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 796; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 792; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 800; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 796; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 804; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: u32 = 800; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: u32 = 808; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_OFFSET: u32 = 812; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK: u32 = 3; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 65; -pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 804; +pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 66; +pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 816; pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 808; +pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 820; pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 812; +pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 824; pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 816; +pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 828; pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 820; +pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 832; pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 824; +pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 836; pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 828; +pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 840; pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 832; +pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 844; pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 836; +pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 848; pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 840; +pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 852; pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 844; +pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 856; pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 848; +pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 860; pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 852; +pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 864; pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 856; +pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 868; pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 860; +pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 872; pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 864; +pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 876; pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 868; +pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 880; pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 872; +pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 884; pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 876; +pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 888; pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 880; +pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 892; pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 884; +pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 896; pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 888; +pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 900; pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 892; +pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 904; pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 896; +pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 908; pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 900; +pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 912; pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 904; +pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 916; pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 908; +pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 920; pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 912; +pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 924; pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 916; +pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 928; pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 920; +pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 932; pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 924; +pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 936; pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 928; +pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 940; pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 932; +pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 944; pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 936; +pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 948; pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 940; +pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 952; pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 944; +pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 956; pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 948; +pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 960; pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 952; +pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 964; pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 956; +pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 968; pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 960; +pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 972; pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 964; +pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 976; pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 968; +pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 980; pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 972; +pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 984; pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 976; +pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 988; pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 980; +pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 992; pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 984; +pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 996; pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 988; +pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 1000; pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 992; +pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 1004; pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 996; +pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 1008; pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 1000; +pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 1012; pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 1004; +pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 1016; pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 1008; +pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 1020; pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1012; +pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1024; pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1016; +pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1028; pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1020; +pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1032; pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1024; +pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1036; pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1028; +pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1040; pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1032; +pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1044; pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1036; +pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1048; pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1040; +pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1052; pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1044; +pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1056; pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1048; +pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1060; pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1052; +pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1064; pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1056; +pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1068; pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: u32 = 1060; +pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: u32 = 1072; pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_65_REG_OFFSET: u32 = 1076; +pub const ALERT_HANDLER_ALERT_CAUSE_65_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_65_A_65_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1064; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1080; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1068; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1084; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1072; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1088; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1076; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1092; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1080; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1096; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1084; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1100; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1088; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1104; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1092; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1108; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1096; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1112; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1100; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1116; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1104; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1120; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1108; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1124; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1112; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1128; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1116; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1132; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH: u32 = 2; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1120; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1136; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET: u32 = 0; @@ -970,57 +983,57 @@ pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA: u32 pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC: u32 = 2; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD: u32 = 3; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1124; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1140; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1128; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1144; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1132; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1148; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1136; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1152; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1140; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1156; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1144; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1160; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1148; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1164; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1152; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1168; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1156; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1172; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1160; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1176; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1164; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1180; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1168; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1184; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1172; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1188; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1176; +pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1192; pub const ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1180; +pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1196; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1036,38 +1049,38 @@ pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1184; +pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1200; pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1188; +pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1204; pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1192; +pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1208; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1196; +pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1212; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1200; +pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1216; pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1204; +pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1220; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1208; +pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1224; pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1212; +pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1228; pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1216; +pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1232; pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1220; +pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1236; pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1224; +pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1240; pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1228; +pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1244; pub const ALERT_HANDLER_CLASSA_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET: u32 = 0; @@ -1079,10 +1092,10 @@ pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1232; +pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1248; pub const ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1236; +pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1252; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1098,38 +1111,38 @@ pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1240; +pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1256; pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1244; +pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1260; pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1248; +pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1264; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1252; +pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1268; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1256; +pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1272; pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1260; +pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1276; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1264; +pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1280; pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1268; +pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1284; pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1272; +pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1288; pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1276; +pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1292; pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1280; +pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1296; pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1284; +pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1300; pub const ALERT_HANDLER_CLASSB_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET: u32 = 0; @@ -1141,10 +1154,10 @@ pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1288; +pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1304; pub const ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1292; +pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1308; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1160,38 +1173,38 @@ pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1296; +pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1312; pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1300; +pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1316; pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1304; +pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1320; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1308; +pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1324; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1312; +pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1328; pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1316; +pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1332; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1320; +pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1336; pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1324; +pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1340; pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1328; +pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1344; pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1332; +pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1348; pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1336; +pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1352; pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1340; +pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1356; pub const ALERT_HANDLER_CLASSC_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET: u32 = 0; @@ -1203,10 +1216,10 @@ pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1344; +pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1360; pub const ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1348; +pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1364; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1222,38 +1235,38 @@ pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1352; +pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1368; pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1356; +pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1372; pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1360; +pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1376; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1364; +pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1380; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1368; +pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1384; pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1372; +pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1388; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1376; +pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1392; pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1380; +pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1396; pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1384; +pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1400; pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1388; +pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1404; pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1392; +pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1408; pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1396; +pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1412; pub const ALERT_HANDLER_CLASSD_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET: u32 = 0;