diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson
index 56df3596e3d75..69932cf889acb 100644
--- a/hw/top_earlgrey/data/chip_testplan.hjson
+++ b/hw/top_earlgrey/data/chip_testplan.hjson
@@ -507,7 +507,8 @@
             host (SV testbench) performs these stimulus / checks.
             '''
       stage: V2
-      tests: ["chip_tap_straps_dev", "chip_tap_straps_prod", "chip_tap_straps_rma"]
+      tests: ["chip_tap_straps_dev", "chip_tap_straps_prod", "chip_tap_straps_rma",
+              "chip_tap_straps_testunlock0"]
     }
 
     // PATTGEN (pre-verified IP) integration tests:
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 803a7db812b70..cac301d553597 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -1621,6 +1621,12 @@
       run_opts: ["+use_otp_image=OtpTypeLcStDev"]
       run_timeout_mins: 120
     }
+    {
+      name: chip_tap_straps_testunlock0
+      uvm_test_seq: chip_tap_straps_vseq
+      en_run_modes: ["strap_tests_mode"]
+      run_opts: ["+use_otp_image=OtpTypeLcStTestUnlocked0"]
+    }
     {
       name: chip_tap_straps_rma
       uvm_test_seq: chip_tap_straps_vseq