[edn] Move prim_edn_req out of prim

This package doesn't fit all that well in prim. Apart from anything else, it depends on edn_pkg (which doesn't live in prim). Move the code out of hw/ip/prim and put it in hw/ip/edn instead. The module that generates the requests is renamed from prim_edn_req to edn_requester (to avoid the "prim" in the name). Signed-off-by: Rupert Swarbrick <[email protected]>
lowRISC · Jan 18, 2024 · 3b4e36e · 3b4e36e
1 parent ad83b93
commit 3b4e36e
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Showing 21 changed files with 28 additions and 30 deletions.
diff --git a/hw/ip/prim/prim_edn_req.core → hw/ip/edn/edn_requester.core b/hw/ip/prim/prim_edn_req.core → hw/ip/edn/edn_requester.core
@@ -3,7 +3,7 @@ CAPI=2:
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-name: "lowrisc:prim:edn_req:0.1"
+name: "lowrisc:ip:edn_requester:0.1"
 description: "EDN synchronization and word packing IP."
 filesets:
   files_rtl:
@@ -12,7 +12,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:ip:edn_pkg
     files:
-      - rtl/prim_edn_req.sv
+      - rtl/edn_requester.sv
     file_type: systemVerilogSource
 
 targets:

diff --git a/hw/ip/prim/rtl/prim_edn_req.sv → hw/ip/edn/rtl/edn_requester.sv b/hw/ip/prim/rtl/prim_edn_req.sv → hw/ip/edn/rtl/edn_requester.sv
@@ -13,7 +13,7 @@
 
 `include "prim_assert.sv"
 
-module prim_edn_req
+module edn_requester
   import prim_alert_pkg::*;
 #(
   parameter int OutWidth = 32,
@@ -212,4 +212,4 @@ module prim_edn_req
   assign unused_param_maxlatency = ^MaxLatency;
 `endif // SYNTHESIS
 
-endmodule : prim_edn_req
+endmodule : edn_requester
diff --git a/hw/ip/keymgr/dv/cov/keymgr_cov_excl.el b/hw/ip/keymgr/dv/cov/keymgr_cov_excl.el
@@ -17,7 +17,7 @@ Fsm state_q "3597806508"
 Transition StIdle->StTxLast "930->320"
 CHECKSUM: "4091831965"
 INSTANCE: tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo
-ANNOTATION: "[UNR] rready_i is tied to 1 from prim_edn_req module."
+ANNOTATION: "[UNR] rready_i is tied to 1 from edn requester module."
 Assert DataOStableWhenPending_A "assertion"
-ANNOTATION: "[UNR] rready_i is tied to 1 from prim_edn_req module."
+ANNOTATION: "[UNR] rready_i is tied to 1 from edn requester module."
 Assert ValidOPairedWithReadyI_A "assertion"
diff --git a/hw/ip/keymgr/keymgr.core b/hw/ip/keymgr/keymgr.core
@@ -10,14 +10,14 @@ filesets:
     depend:
       - lowrisc:prim:all
       - lowrisc:prim:count
-      - lowrisc:prim:edn_req
       - lowrisc:prim:lc_sync
       - lowrisc:prim:lfsr
       - lowrisc:prim:msb_extend
       - lowrisc:prim:mubi
       - lowrisc:prim:sec_anchor
       - lowrisc:prim:secded
       - lowrisc:prim:sparse_fsm
+      - lowrisc:ip:edn_requester
       - lowrisc:ip:flash_ctrl_pkg
       - lowrisc:ip:keymgr_pkg
       - lowrisc:ip:kmac_pkg

diff --git a/hw/ip/keymgr/rtl/keymgr_reseed_ctrl.sv b/hw/ip/keymgr/rtl/keymgr_reseed_ctrl.sv
@@ -57,7 +57,7 @@ module keymgr_reseed_ctrl import keymgr_pkg::*; (
   assign seed_en_o = edn_ack;
   assign reseed_ack_o = reseed_req_i & edn_ack;
 
-  prim_edn_req #(
+  edn_requester #(
     .OutWidth(LfsrWidth)
   ) u_edn_req (
     .clk_i,

diff --git a/hw/ip/kmac/dv/env/kmac_scoreboard.sv b/hw/ip/kmac/dv/env/kmac_scoreboard.sv
@@ -218,7 +218,7 @@ class kmac_scoreboard extends cip_base_scoreboard #(
       `DV_SPINWAIT_EXIT(
           forever begin
             @(posedge in_edn_fetch);
-            // Entropy interface is native 32 bits - prim_edn_req component internally
+            // Entropy interface is native 32 bits - edn_requester component internally
             // does as many EDN fetches as necessary to fill up the required data bus size
             // of the "host".
             repeat (kmac_reg_pkg::NumSeedsEntropyLfsr) begin

diff --git a/hw/ip/kmac/kmac.core b/hw/ip/kmac/kmac.core
@@ -19,7 +19,7 @@ filesets:
       - lowrisc:ip:keymgr_pkg
       - lowrisc:ip:sha3
       - lowrisc:ip:edn_pkg
-      - lowrisc:prim:edn_req
+      - lowrisc:ip:edn_requester
       - lowrisc:ip:kmac_pkg
       - lowrisc:ip:lc_ctrl_pkg
       - lowrisc:prim:lc_sync

diff --git a/hw/ip/kmac/pre_syn/syn_yosys.sh b/hw/ip/kmac/pre_syn/syn_yosys.sh
@@ -86,7 +86,6 @@ OT_DEP_SOURCES=(
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_keccak.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_slicer.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_intr_hw.sv
-    "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_edn_req.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_fifo_sync.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_arbiter_fixed.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_packer.sv

diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_urnd_err_vseq.sv b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_urnd_err_vseq.sv
@@ -10,7 +10,7 @@ class otbn_urnd_err_vseq extends otbn_base_vseq;
   `uvm_object_new
 
   task body();
-    // Inject error on signal after `prim_edn_req`, which may at some point implement its own
+    // Inject error on signal after `edn_requester, which may at some point implement its own
     // countermeasure against spurious ACKs.
     string err_path = "tb.dut.edn_urnd_ack";
     bit skip_err_injection = 1'b0;

diff --git a/hw/ip/otbn/otbn.core b/hw/ip/otbn/otbn.core
@@ -53,7 +53,7 @@ filesets:
       - lowrisc:prim:ram_1p_scr
       - lowrisc:prim:lc_sync
       - lowrisc:ip:edn_pkg
-      - lowrisc:prim:edn_req
+      - lowrisc:ip:edn_requester
       - lowrisc:ip:otbn_pkg
       - lowrisc:ip:otp_ctrl_pkg
     files:

diff --git a/hw/ip/otbn/pre_syn/syn_yosys.sh b/hw/ip/otbn/pre_syn/syn_yosys.sh
@@ -84,7 +84,6 @@ OT_DEP_SOURCES=(
     "$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_err_resp.sv
     "$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_fifo_sync.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_intr_hw.sv
-    "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_edn_req.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_fifo_sync.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_arbiter_fixed.sv
     "$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_packer.sv

diff --git a/hw/ip/otbn/rtl/otbn.sv b/hw/ip/otbn/rtl/otbn.sv
@@ -1016,12 +1016,12 @@ module otbn
   // These synchronize the data coming from EDN and stack the 32 bit EDN words to achieve an
   // internal entropy width of 256 bit.
 
-  prim_edn_req #(
+  edn_requester #(
     .EnRstChks(1'b1),
     .OutWidth(EdnDataWidth),
     // SEC_CM: RND.BUS.CONSISTENCY
     .RepCheck(1'b1)
-  ) u_prim_edn_rnd_req (
+  ) u_edn_rnd_requester (
     .clk_i,
     .rst_ni     ( rst_n        ),
     .req_chk_i  ( 1'b1         ),
@@ -1036,10 +1036,10 @@ module otbn
     .edn_i      ( edn_rnd_i )
   );
 
-  prim_edn_req #(
+  edn_requester #(
     .EnRstChks(1'b1),
     .OutWidth(EdnDataWidth)
-  ) u_prim_edn_urnd_req (
+  ) u_edn_urnd_requester (
     .clk_i,
     .rst_ni     ( rst_n         ),
     .req_chk_i  ( 1'b1          ),

diff --git a/hw/ip/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el b/hw/ip/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el
@@ -81,7 +81,7 @@ INSTANCE: tb.dut.u_tlul_adapter_sram
 ANNOTATION: "VC_COV_UNR"
 Block 20 "3478134645" "d_valid = 1'b1;"
 CHECKSUM: "3839527590 2385261621"
-INSTANCE: tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack
+INSTANCE: tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack
 ANNOTATION: "VC_COV_UNR"
 Block 11 "170878399" ";"
 ANNOTATION: "VC_COV_UNR"
@@ -489,7 +489,7 @@ Condition 6 "2745829604" "(vld_rd_rsp && reqfifo_rdata.error) 1 -1" (3 "11")
 ANNOTATION: "VC_COV_UNR"
 Condition 5 "800561441" "((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_data : (vld_rd_rsp ? rspfifo_rdata.data : '0)) 1 -1" (2 "1")
 CHECKSUM: "4013022403 3210232798"
-INSTANCE: tb.dut.u_prim_edn_req.u_prim_packer_fifo
+INSTANCE: tb.dut.u_edn_req.u_prim_packer_fifo
 ANNOTATION: "VC_COV_UNR"
 Condition 10 "2853235687" "((depth_q == FullDepth) && ((!clr_q))) 1 -1" (2 "10")
 CHECKSUM: "739651683 1037342755"
@@ -531,7 +531,7 @@ INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_tlul_adapter_sram.u_sramreqf
 ANNOTATION: "VC_COV_UNR"
 Condition 2 "1926118060" "((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))) 1 -1" (1 "0")
 CHECKSUM: "3839527590 2212754372"
-INSTANCE: tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack
+INSTANCE: tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack
 ANNOTATION: "VC_COV_UNR"
 Branch 1 "814912860" "dst_fsm_cs" (4) "dst_fsm_cs default,-,-"
 ANNOTATION: "VC_COV_UNR"

diff --git a/hw/ip/otp_ctrl/otp_ctrl.core b/hw/ip/otp_ctrl/otp_ctrl.core
@@ -20,7 +20,7 @@ filesets:
       - lowrisc:prim:buf
       - lowrisc:prim:flop
       - lowrisc:prim:secded
-      - lowrisc:prim:edn_req
+      - lowrisc:ip:edn_requester
       - lowrisc:prim:sec_anchor
       - lowrisc:ip:pwrmgr_pkg
       - lowrisc:ip:edn_pkg

diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
@@ -671,9 +671,9 @@ module otp_ctrl
 
   // This synchronizes the data coming from EDN and stacks the
   // 32bit EDN words to achieve an internal entropy width of 64bit.
-  prim_edn_req #(
+  edn_requester #(
     .OutWidth(EdnDataWidth)
-  ) u_prim_edn_req (
+  ) u_edn_req (
     .clk_i,
     .rst_ni,
     .req_chk_i ( ~lc_escalate_en_any ),

diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -814,7 +814,7 @@ module rv_core_ibex
 
   assign edn_req = ~rnd_valid_q;
 
-  prim_edn_req #(
+  edn_requester #(
     .OutWidth(32)
   ) u_edn_if (
     .clk_i,

diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core
@@ -8,6 +8,7 @@ filesets:
   files_rtl:
     depend:
       - lowrisc:ibex:ibex_top
+      - lowrisc:ip:edn_requester
       - lowrisc:ip:lc_ctrl_pkg
       - lowrisc:ip:otp_ctrl_pkg
       - lowrisc:ip:pwrmgr_pkg
@@ -16,7 +17,6 @@ filesets:
       - lowrisc:ip_interfaces:alert_handler_reg
       - lowrisc:prim:all
       - lowrisc:prim:clock_gating
-      - lowrisc:prim:edn_req
       - lowrisc:prim:esc
       - lowrisc:prim:lc_sync
       - lowrisc:prim:lc_sender

diff --git a/hw/ip_templates/alert_handler/alert_handler_component.core b/hw/ip_templates/alert_handler/alert_handler_component.core
@@ -8,12 +8,12 @@ description: "Alert Handler component without the CSRs"
 filesets:
   files_rtl:
     depend:
+      - lowrisc:ip:edn_requester
       - lowrisc:ip:tlul
       - lowrisc:prim:all
       - lowrisc:prim:esc
       - lowrisc:prim:double_lfsr
       - lowrisc:prim:count
-      - lowrisc:prim:edn_req
       - lowrisc:prim:buf
       - lowrisc:prim:mubi
       - lowrisc:prim:sparse_fsm

diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler.sv b/hw/ip_templates/alert_handler/rtl/alert_handler.sv
@@ -98,7 +98,7 @@ module alert_handler
   logic edn_req, edn_ack;
   logic [LfsrWidth-1:0] edn_data;
 
-  prim_edn_req #(
+  edn_requester #(
     .OutWidth(LfsrWidth)
   ) u_edn_req (
     // Alert handler side

diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler_component.core b/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler_component.core
@@ -8,12 +8,12 @@ description: "Alert Handler component without the CSRs"
 filesets:
   files_rtl:
     depend:
+      - lowrisc:ip:edn_requester
       - lowrisc:ip:tlul
       - lowrisc:prim:all
       - lowrisc:prim:esc
       - lowrisc:prim:double_lfsr
       - lowrisc:prim:count
-      - lowrisc:prim:edn_req
       - lowrisc:prim:buf
       - lowrisc:prim:mubi
       - lowrisc:prim:sparse_fsm

diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler.sv
@@ -98,7 +98,7 @@ module alert_handler
   logic edn_req, edn_ack;
   logic [LfsrWidth-1:0] edn_data;
 
-  prim_edn_req #(
+  edn_requester #(
     .OutWidth(LfsrWidth)
   ) u_edn_req (
     // Alert handler side