[bazel] Build non-scrambled VMEM images

1. Define a basic CW305 exec_env.The build/release pipeline expects to find cw305 artifacts for the test_rom. 2. The englishbreakfast verilator model does not understand ROM scrambling, so we also create a non-scrambled VMEM file. Signed-off-by: Chris Frantz <[email protected]>
lowRISC · Oct 5, 2023 · 2161256 · 2161256
1 parent b2cf961
commit 2161256
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Showing 9 changed files with 85 additions and 4 deletions.
diff --git a/azure-pipelines.yml b/azure-pipelines.yml
@@ -351,9 +351,12 @@ jobs:
   - bash: |
       . util/build_consts.sh
       mkdir -p "$BIN_DIR/sw/device/lib/testing/test_rom"
-      cp $(ci/scripts/target-location.sh //sw/device/lib/testing/test_rom:test_rom_fpga_cw305_vmem) \
+      cp $(ci/scripts/target-location.sh \
+          //sw/device/lib/testing/test_rom:test_rom_fpga_cw305 \
+          --features=-rv32_bitmanip \
+          --copt=-DOT_IS_ENGLISH_BREAKFAST_REDUCED_SUPPORT_FOR_INTERNAL_USE_ONLY_) \
         "$BIN_DIR/sw/device/lib/testing/test_rom"
-    displayName: Copy test_rom_fpga_cw305_vmem to $BIN_DIR
+    displayName: Copy test_rom_fpga_cw305 to $BIN_DIR
   - template: ci/upload-artifacts-template.yml
     parameters:
       includePatterns:

diff --git a/hw/top_earlgrey/BUILD b/hw/top_earlgrey/BUILD
@@ -9,6 +9,7 @@ load(
     "//rules/opentitan:defs.bzl",
     "DEFAULT_TEST_FAILURE_MSG",
     "DEFAULT_TEST_SUCCESS_MSG",
+    "fpga_cw305",
     "fpga_cw310",
     "fpga_cw340",
     "sim_dv",
@@ -90,6 +91,23 @@ fpga_cw310(
     rsa_key = {"//sw/device/silicon_creator/rom/keys/fake/rsa:test_private_key_0": "test_key_0"},
 )
 
+###########################################################################
+# FPGA CW305 Environments
+#
+# TODO(opentitan#19493): Determine whether the `fpga_cw310` infrastructure
+# should become a more generic `fpga_chipwhisperer` infrastruture able to
+# handle multiple CW-type boards.
+###########################################################################
+fpga_cw305(
+    name = "fpga_cw305",
+    design = "earlgrey",
+    exec_env = "fpga_cw305",
+    lib = "//sw/device/lib/arch:fpga_cw305",
+    linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_a",
+    rom_scramble_config = "//hw/top_earlgrey/data:autogen/top_earlgrey.gen.hjson",
+    test_cmd = "testing-not-supported",
+)
+
 ###########################################################################
 # FPGA CW340 Environments
 #

diff --git a/rules/opentitan/cc.bzl b/rules/opentitan/cc.bzl
@@ -228,6 +228,12 @@ def _opentitan_binary(ctx):
         # the DefaultInfo provider.
         if "logs" in provides:
             default_info.extend(provides["logs"])
+
+        # FIXME(cfrantz): Special case: The englishbreakfast verilator model
+        # requires a non-scrambled ROM image.
+        if provides.get("rom32"):
+            default_info.append(provides["rom32"])
+
         groups.update(_as_group_info(exec_env.exec_env, signed))
         groups.update(_as_group_info(exec_env.exec_env, provides))
 

diff --git a/rules/opentitan/defs.bzl b/rules/opentitan/defs.bzl
@@ -16,6 +16,7 @@ load(
 load(
     "@lowrisc_opentitan//rules/opentitan:fpga_cw310.bzl",
     _cw310_params = "cw310_params",
+    _fpga_cw305 = "fpga_cw305",
     _fpga_cw310 = "fpga_cw310",
     _fpga_cw340 = "fpga_cw340",
 )
@@ -40,6 +41,7 @@ opentitan_transition = _opentitan_transition
 
 opentitan_binary = _opentitan_binary
 fpga_cw310 = _fpga_cw310
+fpga_cw305 = _fpga_cw305
 fpga_cw340 = _fpga_cw340
 cw310_params = _cw310_params
 

diff --git a/rules/opentitan/fpga_cw310.bzl b/rules/opentitan/fpga_cw310.bzl
@@ -2,7 +2,13 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-load("@lowrisc_opentitan//rules/opentitan:providers.bzl", "Cw310BinaryInfo", "Cw340BinaryInfo", "get_one_binary_file")
+load(
+    "@lowrisc_opentitan//rules/opentitan:providers.bzl",
+    "Cw305BinaryInfo",
+    "Cw310BinaryInfo",
+    "Cw340BinaryInfo",
+    "get_one_binary_file",
+)
 load("@lowrisc_opentitan//rules/opentitan:util.bzl", "get_fallback", "get_files")
 load(
     "//rules/opentitan:exec_env.bzl",
@@ -13,6 +19,7 @@ load(
 load(
     "@lowrisc_opentitan//rules/opentitan:transform.bzl",
     "convert_to_scrambled_rom_vmem",
+    "convert_to_vmem",
 )
 
 _TEST_SCRIPT = """#!/bin/bash
@@ -47,10 +54,20 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
             rom_scramble_config = exec_env.rom_scramble_config,
             rom_scramble_tool = ctx.executable.rom_scramble_tool,
         )
+
+        # The englishbreakfast verilator model does not understand ROM
+        # scrambling, so we also create a non-scrambled VMEM file.
+        rom32 = convert_to_vmem(
+            ctx,
+            name = name,
+            src = binary,
+            word_size = 32,
+        )
         default = rom
     elif ctx.attr.kind == "flash":
         default = signed_bin if signed_bin else binary
         rom = None
+        rom32 = None
     else:
         fail("Not implemented: kind ==", ctx.attr.kind)
 
@@ -59,6 +76,7 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
         "binary": binary,
         "default": default,
         "rom": rom,
+        "rom32": rom32,
         "signed_bin": signed_bin,
         "disassembly": disassembly,
         "mapfile": mapfile,
@@ -150,6 +168,20 @@ fpga_cw310 = rule(
     attrs = exec_env_common_attrs(),
 )
 
+def _fpga_cw305(ctx):
+    fields = exec_env_as_dict(ctx)
+    return ExecEnvInfo(
+        provider = Cw305BinaryInfo,
+        test_dispatch = _test_dispatch,
+        transform = _transform,
+        **fields
+    )
+
+fpga_cw305 = rule(
+    implementation = _fpga_cw305,
+    attrs = exec_env_common_attrs(),
+)
+
 def _fpga_cw340(ctx):
     fields = exec_env_as_dict(ctx)
     return ExecEnvInfo(

diff --git a/rules/opentitan/legacy.bzl b/rules/opentitan/legacy.bzl
@@ -16,7 +16,10 @@ def legacy_rom_targets(target, suffixes):
         native.filegroup(
             name = "{}_{}".format(target, suffix),
             srcs = [":{}".format(target)],
-            output_group = "{}_rom".format(suffix),
+            output_group = select({
+                "//sw/device:is_english_breakfast": "{}_rom32".format(suffix),
+                "//conditions:default": "{}_rom".format(suffix),
+            }),
         )
         native.alias(
             name = "{}_{}_scr_vmem".format(target, suffix),

diff --git a/rules/opentitan/providers.bzl b/rules/opentitan/providers.bzl
@@ -8,6 +8,10 @@ Cw310BinaryInfo = provider(
     doc = "CW310 Binary Info",
 )
 
+Cw305BinaryInfo = provider(
+    doc = "CW305 Binary Info",
+)
+
 Cw340BinaryInfo = provider(
     doc = "CW340 Binary Info",
 )

diff --git a/rules/opentitan/sim_verilator.bzl b/rules/opentitan/sim_verilator.bzl
@@ -47,6 +47,15 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
             rom_scramble_config = exec_env.rom_scramble_config,
             rom_scramble_tool = ctx.executable.rom_scramble_tool,
         )
+
+        # The englishbreakfast verilator model does not understand ROM
+        # scrambling, so we also create a non-scrambled VMEM file.
+        rom32 = convert_to_vmem(
+            ctx,
+            name = name,
+            src = binary,
+            word_size = 32,
+        )
         default = rom
         vmem = rom
     elif ctx.attr.kind == "flash":
@@ -58,6 +67,7 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
         )
         default = vmem
         rom = None
+        rom32 = None
     else:
         fail("Not implemented: kind ==", ctx.attr.kind)
 
@@ -70,6 +80,7 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
         "disassembly": disassembly,
         "mapfile": mapfile,
         "vmem": vmem,
+        "rom32": rom32,
     }
 
 def _test_dispatch(ctx, exec_env, provider):

diff --git a/sw/device/lib/testing/test_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD
@@ -30,6 +30,7 @@ opentitan_binary(
     name = "test_rom",
     exec_env = [
         "//hw/top_earlgrey:fpga_cw310",
+        "//hw/top_earlgrey:fpga_cw305",
         "//hw/top_earlgrey:fpga_cw340",
         "//hw/top_earlgrey:sim_dv_base",
         "//hw/top_earlgrey:sim_verilator_base",
@@ -46,6 +47,7 @@ opentitan_binary(
 legacy_rom_targets(
     suffixes = [
         "fpga_cw310",
+        "fpga_cw305",
         "fpga_cw340",
         "sim_dv",
         "sim_verilator",