[sw/tests] Mark more tests as broken in SiVal ROM_EXT

The following tests also seem to be part of issue #21706:
- //sw/device/tests:pwrmgr_all_reset_reqs_test
- //sw/device/tests:pwrmgr_random_sleep_all_reset_reqs_test

Thus this commit marks them as broken in SiVal ROM_EXT.

This should contribute to fixing the currently failing CI checks on
`master`.

Signed-off-by: Andreas Kurth <[email protected]>

sw/device/tests/BUILD

@@ -2538,10 +2538,12 @@ cc_library(
 opentitan_test(
     name = "pwrmgr_all_reset_reqs_test",
     srcs = ["pwrmgr_all_reset_reqs_test.c"],
+    broken = new_cw310_params(tags = ["broken"]),
     exec_env = dicts.add(
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
         {
-            "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": "test_harness",
+            # FIXME broken in sival ROM_EXT, remove this line when fixed. See #21706.
+            "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": "broken",
             "//hw/top_earlgrey:fpga_cw310_sival": "test_harness",
             "//hw/top_earlgrey:fpga_cw310_test_rom": "test_harness",
             "//hw/top_earlgrey:silicon_creator": None,
@@ -2575,11 +2577,13 @@ opentitan_test(
 opentitan_test(
     name = "pwrmgr_random_sleep_all_reset_reqs_test",
     srcs = ["pwrmgr_random_sleep_all_reset_reqs_test.c"],
+    broken = new_cw310_params(tags = ["broken"]),
     exec_env = dicts.add(
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
         {
             "//hw/top_earlgrey:fpga_cw310_sival": "test_harness",
-            "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": "test_harness",
+            # FIXME broken in sival ROM_EXT, remove this line when fixed. See #21706.
+            "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": "broken",
             "//hw/top_earlgrey:fpga_cw310_test_rom": "test_harness",
             "//hw/top_earlgrey:silicon_creator": None,
             "//hw/top_earlgrey:sim_dv": None,