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Cleanup x86_mmx after removing IR type #100646

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merged 4 commits into from
Jul 28, 2024
Merged

Cleanup x86_mmx after removing IR type #100646

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61098c3
Replace x86_mmx in tests.
jyknight Jul 25, 2024
aac0bdf
Remove IR parser support for x86_mmx keyword.
jyknight Jul 25, 2024
5b92dfc
Manual test updates:
jyknight Jul 25, 2024
9bc2e86
Remove bitcasts from <1 x i64> to itself.
jyknight Jul 27, 2024
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2 changes: 0 additions & 2 deletions llvm/lib/AsmParser/LLLexer.cpp
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Expand Up @@ -838,8 +838,6 @@ lltok::Kind LLLexer::LexIdentifier() {
TYPEKEYWORD("ppc_fp128", Type::getPPC_FP128Ty(Context));
TYPEKEYWORD("label", Type::getLabelTy(Context));
TYPEKEYWORD("metadata", Type::getMetadataTy(Context));
TYPEKEYWORD("x86_mmx", llvm::FixedVectorType::get(
llvm::IntegerType::get(Context, 64), 1));
TYPEKEYWORD("x86_amx", Type::getX86_AMXTy(Context));
TYPEKEYWORD("token", Type::getTokenTy(Context));
TYPEKEYWORD("ptr", PointerType::getUnqual(Context));
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Bindings/llvm-c/echo.ll
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Expand Up @@ -70,7 +70,7 @@ define void @types() {
%9 = alloca [3 x i22], align 4
%10 = alloca ptr addrspace(5), align 8
%11 = alloca <5 x ptr>, align 64
%12 = alloca x86_mmx, align 8
%12 = alloca <1 x i64>, align 8
ret void
}

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2 changes: 0 additions & 2 deletions llvm/test/Bitcode/compatibility.ll
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Expand Up @@ -1112,8 +1112,6 @@ define void @typesystem() {
; CHECK: %t5 = alloca x86_fp80
%t6 = alloca ppc_fp128
; CHECK: %t6 = alloca ppc_fp128
%t7 = alloca x86_mmx
; CHECK: %t7 = alloca <1 x i64>
%t8 = alloca ptr
; CHECK: %t8 = alloca ptr
%t9 = alloca <4 x i32>
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll
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Expand Up @@ -25,10 +25,10 @@ define void @test(<1 x i64> %c64, <1 x i64> %mask1, ptr %P) {
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
entry:
%tmp4 = bitcast <1 x i64> %mask1 to x86_mmx ; <x86_mmx> [#uses=1]
%tmp6 = bitcast <1 x i64> %c64 to x86_mmx ; <x86_mmx> [#uses=1]
tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp4, x86_mmx %tmp6, ptr %P )
%tmp4 = bitcast <1 x i64> %mask1 to <1 x i64> ; <<1 x i64>> [#uses=1]
%tmp6 = bitcast <1 x i64> %c64 to <1 x i64> ; <<1 x i64>> [#uses=1]
tail call void @llvm.x86.mmx.maskmovq( <1 x i64> %tmp4, <1 x i64> %tmp6, ptr %P )
ret void
}

declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, ptr)
declare void @llvm.x86.mmx.maskmovq(<1 x i64>, <1 x i64>, ptr)
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | FileCheck %s

@R = external global x86_mmx ; <ptr> [#uses=1]
@R = external global <1 x i64> ; <ptr> [#uses=1]

define void @foo(<1 x i64> %A, <1 x i64> %B) nounwind {
; CHECK-LABEL: foo:
Expand All @@ -14,13 +14,13 @@ define void @foo(<1 x i64> %A, <1 x i64> %B) nounwind {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%tmp4 = bitcast <1 x i64> %B to x86_mmx ; <<4 x i16>> [#uses=1]
%tmp6 = bitcast <1 x i64> %A to x86_mmx ; <<4 x i16>> [#uses=1]
%tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w( x86_mmx %tmp6, x86_mmx %tmp4 ) ; <x86_mmx> [#uses=1]
store x86_mmx %tmp7, ptr @R
%tmp4 = bitcast <1 x i64> %B to <1 x i64> ; <<4 x i16>> [#uses=1]
%tmp6 = bitcast <1 x i64> %A to <1 x i64> ; <<4 x i16>> [#uses=1]
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Can we remove such bitcast <1 x i64>.*to <1 x i64>?

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There's indeed a lot of extraneous bitcast throughout all these modified tests, many where it's casting through a series of different types and back to the first. I started to look at cleaning it up, but since the plan is actually to delete the MMX intrinsics in the IR, and mostly the bitcast mess is around MMX IR intrinsics, I put that aside.

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My concern is the future developer may be confused by the code and think it's intended for some purpose. It should be fine just clean up the specific <1 x i64> to <1 x i64> bitcast, which don't look many too me.

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No, not too many just for that. Done.

%tmp7 = tail call <1 x i64> @llvm.x86.mmx.paddus.w( <1 x i64> %tmp6, <1 x i64> %tmp4 ) ; <<1 x i64>> [#uses=1]
store <1 x i64> %tmp7, ptr @R
tail call void @llvm.x86.mmx.emms( )
ret void
}

declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
declare <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64>, <1 x i64>)
declare void @llvm.x86.mmx.emms()
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll
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Expand Up @@ -5,15 +5,15 @@ entry:
tail call void asm sideeffect "# top of block", "~{dirflag},~{fpsr},~{flags},~{di},~{si},~{dx},~{cx},~{ax}"( ) nounwind
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
tail call void asm sideeffect ".line 8", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
%tmp1 = tail call x86_mmx asm sideeffect "movd $1, $0", "=={mm4},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( i32 undef ) nounwind ; <x86_mmx> [#uses=1]
%tmp1 = tail call <1 x i64> asm sideeffect "movd $1, $0", "=={mm4},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( i32 undef ) nounwind ; <<1 x i64>> [#uses=1]
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
tail call void asm sideeffect ".line 9", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
%tmp3 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm3},~{dirflag},~{fpsr},~{flags},~{memory}"( x86_mmx undef ) nounwind ; <i32> [#uses=1]
%tmp3 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm3},~{dirflag},~{fpsr},~{flags},~{memory}"( <1 x i64> undef ) nounwind ; <i32> [#uses=1]
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
tail call void asm sideeffect ".line 10", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
tail call void asm sideeffect "movntq $0, 0($1,$2)", "{mm0},{di},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( x86_mmx undef, i32 undef, i32 %tmp3 ) nounwind
tail call void asm sideeffect "movntq $0, 0($1,$2)", "{mm0},{di},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( <1 x i64> undef, i32 undef, i32 %tmp3 ) nounwind
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
tail call void asm sideeffect ".line 11", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
%tmp8 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm4},~{dirflag},~{fpsr},~{flags},~{memory}"( x86_mmx %tmp1 ) nounwind ; <i32> [#uses=0]
%tmp8 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm4},~{dirflag},~{fpsr},~{flags},~{memory}"( <1 x i64> %tmp1 ) nounwind ; <i32> [#uses=0]
ret i32 undef
}
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll
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Expand Up @@ -17,13 +17,13 @@ entry:
br i1 false, label %bb.nph144.split, label %bb133

bb.nph144.split: ; preds = %entry
%tmp = bitcast <8 x i8> zeroinitializer to x86_mmx
%tmp2 = bitcast <8 x i8> zeroinitializer to x86_mmx
tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp, x86_mmx %tmp2, ptr null ) nounwind
%tmp = bitcast <8 x i8> zeroinitializer to <1 x i64>
%tmp2 = bitcast <8 x i8> zeroinitializer to <1 x i64>
tail call void @llvm.x86.mmx.maskmovq( <1 x i64> %tmp, <1 x i64> %tmp2, ptr null ) nounwind
unreachable

bb133: ; preds = %entry
ret void
}

declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, ptr) nounwind
declare void @llvm.x86.mmx.maskmovq(<1 x i64>, <1 x i64>, ptr) nounwind
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll
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Expand Up @@ -26,7 +26,7 @@ entry:

; This is how to get MMX instructions.

define <2 x double> @a2(x86_mmx %x) nounwind {
define <2 x double> @a2(<1 x i64> %x) nounwind {
; CHECK-LABEL: a2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
Expand All @@ -42,11 +42,11 @@ define <2 x double> @a2(x86_mmx %x) nounwind {
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry:
%y = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx %x)
%y = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %x)
ret <2 x double> %y
}

define x86_mmx @b2(<2 x double> %x) nounwind {
define <1 x i64> @b2(<2 x double> %x) nounwind {
; CHECK-LABEL: b2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
Expand All @@ -61,9 +61,9 @@ define x86_mmx @b2(<2 x double> %x) nounwind {
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry:
%y = tail call x86_mmx @llvm.x86.sse.cvttpd2pi (<2 x double> %x)
ret x86_mmx %y
%y = tail call <1 x i64> @llvm.x86.sse.cvttpd2pi (<2 x double> %x)
ret <1 x i64> %y
}

declare <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx)
declare x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double>)
declare <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64>)
declare <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double>)
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/2011-06-14-mmx-inlineasm.ll
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Expand Up @@ -3,22 +3,22 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
target triple = "i386-apple-macosx10.6.6"

%0 = type { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx }
%0 = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }

define i32 @pixman_fill_mmx(ptr nocapture %bits, i32 %stride, i32 %bpp, i32 %x, i32 %y, i32 %width, i32 %height, i32 %xor) nounwind ssp {
entry:
%conv = zext i32 %xor to i64
%shl = shl nuw i64 %conv, 32
%or = or i64 %shl, %conv
%0 = bitcast i64 %or to x86_mmx
%0 = bitcast i64 %or to <1 x i64>
; CHECK: movq [[MMXR:%mm[0-7],]] {{%mm[0-7]}}
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
%1 = tail call %0 asm "movq\09\09$7,\09$0\0Amovq\09\09$7,\09$1\0Amovq\09\09$7,\09$2\0Amovq\09\09$7,\09$3\0Amovq\09\09$7,\09$4\0Amovq\09\09$7,\09$5\0Amovq\09\09$7,\09$6\0A", "=&y,=&y,=&y,=&y,=&y,=&y,=y,y,~{dirflag},~{fpsr},~{flags}"(x86_mmx %0) nounwind, !srcloc !0
%1 = tail call %0 asm "movq\09\09$7,\09$0\0Amovq\09\09$7,\09$1\0Amovq\09\09$7,\09$2\0Amovq\09\09$7,\09$3\0Amovq\09\09$7,\09$4\0Amovq\09\09$7,\09$5\0Amovq\09\09$7,\09$6\0A", "=&y,=&y,=&y,=&y,=&y,=&y,=y,y,~{dirflag},~{fpsr},~{flags}"(<1 x i64> %0) nounwind, !srcloc !0
%asmresult = extractvalue %0 %1, 0
%asmresult6 = extractvalue %0 %1, 1
%asmresult7 = extractvalue %0 %1, 2
Expand All @@ -34,7 +34,7 @@ entry:
; CHECK-NEXT: movq {{%mm[0-7]}},
; CHECK-NEXT: movq {{%mm[0-7]}},
; CHECK-NEXT: movq {{%mm[0-7]}},
tail call void asm sideeffect "movq\09$1,\09 ($0)\0Amovq\09$2,\09 8($0)\0Amovq\09$3,\0916($0)\0Amovq\09$4,\0924($0)\0Amovq\09$5,\0932($0)\0Amovq\09$6,\0940($0)\0Amovq\09$7,\0948($0)\0Amovq\09$8,\0956($0)\0A", "r,y,y,y,y,y,y,y,y,~{memory},~{dirflag},~{fpsr},~{flags}"(ptr undef, x86_mmx %0, x86_mmx %asmresult, x86_mmx %asmresult6, x86_mmx %asmresult7, x86_mmx %asmresult8, x86_mmx %asmresult9, x86_mmx %asmresult10, x86_mmx %asmresult11) nounwind, !srcloc !1
tail call void asm sideeffect "movq\09$1,\09 ($0)\0Amovq\09$2,\09 8($0)\0Amovq\09$3,\0916($0)\0Amovq\09$4,\0924($0)\0Amovq\09$5,\0932($0)\0Amovq\09$6,\0940($0)\0Amovq\09$7,\0948($0)\0Amovq\09$8,\0956($0)\0A", "r,y,y,y,y,y,y,y,y,~{memory},~{dirflag},~{fpsr},~{flags}"(ptr undef, <1 x i64> %0, <1 x i64> %asmresult, <1 x i64> %asmresult6, <1 x i64> %asmresult7, <1 x i64> %asmresult8, <1 x i64> %asmresult9, <1 x i64> %asmresult10, <1 x i64> %asmresult11) nounwind, !srcloc !1
tail call void @llvm.x86.mmx.emms() nounwind
ret i32 1
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/avx-vbroadcast.ll
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Expand Up @@ -1011,7 +1011,7 @@ define float @broadcast_lifetime() nounwind {
ret float %7
}

define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
define <8 x i16> @broadcast_x86_mmx(<1 x i64> %tmp) nounwind {
; X86-LABEL: broadcast_x86_mmx:
; X86: ## %bb.0: ## %bb
; X86-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Expand All @@ -1023,7 +1023,7 @@ define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; X64-NEXT: retq
bb:
%tmp1 = bitcast x86_mmx %tmp to i64
%tmp1 = bitcast <1 x i64> %tmp to i64
%tmp2 = insertelement <2 x i64> undef, i64 %tmp1, i32 0
%tmp3 = bitcast <2 x i64> %tmp2 to <8 x i16>
%tmp4 = shufflevector <8 x i16> %tmp3, <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/avx2-vbroadcast.ll
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Expand Up @@ -1449,7 +1449,7 @@ eintry:
ret void
}

define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
define <8 x i16> @broadcast_x86_mmx(<1 x i64> %tmp) nounwind {
; X86-LABEL: broadcast_x86_mmx:
; X86: ## %bb.0: ## %bb
; X86-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Expand All @@ -1466,7 +1466,7 @@ define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
; X64-AVX512VL-NEXT: vpbroadcastq %rdi, %xmm0
; X64-AVX512VL-NEXT: retq
bb:
%tmp1 = bitcast x86_mmx %tmp to i64
%tmp1 = bitcast <1 x i64> %tmp to i64
%tmp2 = insertelement <2 x i64> undef, i64 %tmp1, i32 0
%tmp3 = bitcast <2 x i64> %tmp2 to <8 x i16>
%tmp4 = shufflevector <8 x i16> %tmp3, <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
Expand Down
34 changes: 17 additions & 17 deletions llvm/test/CodeGen/X86/bitcast-mmx.ll
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Expand Up @@ -17,9 +17,9 @@ define i32 @t0(i64 %x) nounwind {
; X64-NEXT: retq
entry:
%0 = bitcast i64 %x to <4 x i16>
%1 = bitcast <4 x i16> %0 to x86_mmx
%2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18)
%3 = bitcast x86_mmx %2 to <4 x i16>
%1 = bitcast <4 x i16> %0 to <1 x i64>
%2 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %1, i8 -18)
%3 = bitcast <1 x i64> %2 to <4 x i16>
%4 = bitcast <4 x i16> %3 to <1 x i64>
%5 = extractelement <1 x i64> %4, i32 0
%6 = bitcast i64 %5 to <2 x i32>
Expand Down Expand Up @@ -52,9 +52,9 @@ define i64 @t1(i64 %x, i32 %n) nounwind {
; X64-NEXT: movq %mm0, %rax
; X64-NEXT: retq
entry:
%0 = bitcast i64 %x to x86_mmx
%1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n)
%2 = bitcast x86_mmx %1 to i64
%0 = bitcast i64 %x to <1 x i64>
%1 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %0, i32 %n)
%2 = bitcast <1 x i64> %1 to i64
ret i64 %2
}

Expand Down Expand Up @@ -88,11 +88,11 @@ define i64 @t2(i64 %x, i32 %n, i32 %w) nounwind {
entry:
%0 = insertelement <2 x i32> undef, i32 %w, i32 0
%1 = insertelement <2 x i32> %0, i32 0, i32 1
%2 = bitcast <2 x i32> %1 to x86_mmx
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n)
%4 = bitcast i64 %x to x86_mmx
%5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3)
%6 = bitcast x86_mmx %5 to i64
%2 = bitcast <2 x i32> %1 to <1 x i64>
%3 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %2, i32 %n)
%4 = bitcast i64 %x to <1 x i64>
%5 = tail call <1 x i64> @llvm.x86.mmx.por(<1 x i64> %4, <1 x i64> %3)
%6 = bitcast <1 x i64> %5 to i64
ret i64 %6
}

Expand Down Expand Up @@ -123,14 +123,14 @@ define i64 @t3(ptr %y, ptr %n) nounwind {
; X64-NEXT: movq %mm0, %rax
; X64-NEXT: retq
entry:
%0 = load x86_mmx, ptr %y, align 8
%0 = load <1 x i64>, ptr %y, align 8
%1 = load i32, ptr %n, align 4
%2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %1)
%3 = bitcast x86_mmx %2 to i64
%2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %0, i32 %1)
%3 = bitcast <1 x i64> %2 to i64
ret i64 %3
}

declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx)
declare <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64>, i8)
declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)
declare <1 x i64> @llvm.x86.mmx.por(<1 x i64>, <1 x i64>)

6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/expand-vr64-gr64-copy.mir
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Expand Up @@ -6,9 +6,9 @@

define <2 x i32> @test_paddw(<2 x i32> %a) nounwind readnone {
entry:
%0 = bitcast <2 x i32> %a to x86_mmx
%1 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %0, x86_mmx %0)
%2 = bitcast x86_mmx %1 to <2 x i32>
%0 = bitcast <2 x i32> %a to <1 x i64>
%1 = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> %0, <1 x i64> %0)
%2 = bitcast <1 x i64> %1 to <2 x i32>
ret <2 x i32> %2
}

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/fast-isel-bc.ll
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Expand Up @@ -4,7 +4,7 @@

; PR4684

declare void @func2(x86_mmx)
declare void @func2(<1 x i64>)

; This isn't spectacular, but it's MMX code at -O0...

Expand All @@ -28,7 +28,7 @@ define void @func1() nounwind {
; X64-NEXT: callq _func2
; X64-NEXT: popq %rax
; X64-NEXT: retq
%tmp0 = bitcast <2 x i32> <i32 0, i32 2> to x86_mmx
call void @func2(x86_mmx %tmp0)
%tmp0 = bitcast <2 x i32> <i32 0, i32 2> to <1 x i64>
call void @func2(<1 x i64> %tmp0)
ret void
}
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/fast-isel-nontemporal.ll
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Expand Up @@ -104,12 +104,12 @@ define void @test_mmx(ptr nocapture %a0, ptr nocapture %a1) {
; ALL-NEXT: movntq %mm0, (%rsi)
; ALL-NEXT: retq
entry:
%0 = load x86_mmx, ptr %a0
%1 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %0, i32 3)
store x86_mmx %1, ptr %a1, align 8, !nontemporal !1
%0 = load <1 x i64>, ptr %a0
%1 = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %0, i32 3)
store <1 x i64> %1, ptr %a1, align 8, !nontemporal !1
ret void
}
declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone
declare <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64>, i32) nounwind readnone

;
; 128-bit Vector Stores
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14 changes: 7 additions & 7 deletions llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
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Expand Up @@ -14,12 +14,12 @@ define void @t3() nounwind {
; X86-64-NEXT: xorl %eax, %eax
; X86-64-NEXT: jmp _pass_v8qi ## TAILCALL
%tmp3 = load <8 x i8>, ptr @g_v8qi, align 8
%tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
%tmp4 = tail call i32 (...) @pass_v8qi( x86_mmx %tmp3a ) nounwind
%tmp3a = bitcast <8 x i8> %tmp3 to <1 x i64>
%tmp4 = tail call i32 (...) @pass_v8qi( <1 x i64> %tmp3a ) nounwind
ret void
}

define void @t4(x86_mmx %v1, x86_mmx %v2) nounwind {
define void @t4(<1 x i64> %v1, <1 x i64> %v2) nounwind {
; X86-64-LABEL: t4:
; X86-64: ## %bb.0:
; X86-64-NEXT: movq %rdi, %xmm0
Expand All @@ -28,11 +28,11 @@ define void @t4(x86_mmx %v1, x86_mmx %v2) nounwind {
; X86-64-NEXT: movq %xmm1, %rdi
; X86-64-NEXT: xorl %eax, %eax
; X86-64-NEXT: jmp _pass_v8qi ## TAILCALL
%v1a = bitcast x86_mmx %v1 to <8 x i8>
%v2b = bitcast x86_mmx %v2 to <8 x i8>
%v1a = bitcast <1 x i64> %v1 to <8 x i8>
%v2b = bitcast <1 x i64> %v2 to <8 x i8>
%tmp3 = add <8 x i8> %v1a, %v2b
%tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
%tmp4 = tail call i32 (...) @pass_v8qi( x86_mmx %tmp3a ) nounwind
%tmp3a = bitcast <8 x i8> %tmp3 to <1 x i64>
%tmp4 = tail call i32 (...) @pass_v8qi( <1 x i64> %tmp3a ) nounwind
ret void
}

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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/mmx-arg-passing.ll
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Expand Up @@ -8,9 +8,9 @@
; On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.

@u1 = external global x86_mmx
@u1 = external global <1 x i64>

define void @t1(x86_mmx %v1) nounwind {
define void @t1(<1 x i64> %v1) nounwind {
; X86-32-LABEL: t1:
; X86-32: ## %bb.0:
; X86-32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -25,11 +25,11 @@ define void @t1(x86_mmx %v1) nounwind {
; X86-64-NEXT: movq _u1@GOTPCREL(%rip), %rax
; X86-64-NEXT: movq %rdi, (%rax)
; X86-64-NEXT: retq
store x86_mmx %v1, ptr @u1, align 8
store <1 x i64> %v1, ptr @u1, align 8
ret void
}

@u2 = external global x86_mmx
@u2 = external global <1 x i64>

define void @t2(<1 x i64> %v1) nounwind {
; X86-32-LABEL: t2:
Expand All @@ -46,7 +46,7 @@ define void @t2(<1 x i64> %v1) nounwind {
; X86-64-NEXT: movq _u2@GOTPCREL(%rip), %rax
; X86-64-NEXT: movq %rdi, (%rax)
; X86-64-NEXT: retq
%tmp = bitcast <1 x i64> %v1 to x86_mmx
store x86_mmx %tmp, ptr @u2, align 8
%tmp = bitcast <1 x i64> %v1 to <1 x i64>
store <1 x i64> %tmp, ptr @u2, align 8
ret void
}
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