diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index 8c27be43f4a23c9..94e0fa2404d6fc6 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -161,11 +161,6 @@ namespace llvm {
     /// DisableFramePointerElim - This returns true if frame pointer elimination
     /// optimization should be disabled for the given machine function.
     bool DisableFramePointerElim(const MachineFunction &MF) const;
-    
-    /// DisableLeafFramePointerElim - This returns true if leaf frame pointer
-    /// elimination optimization should be disabled for the given machine
-    /// function.
-    bool DisableLeafFramePointerElim(const MachineFunction &MF) const;
 
     /// FramePointerIsReserved - This returns true if the frame pointer must
     /// always either point to a new frame record or be un-modified in the given
diff --git a/llvm/lib/CodeGen/TargetOptionsImpl.cpp b/llvm/lib/CodeGen/TargetOptionsImpl.cpp
index dda9118c87ffeae..15afe0072366526 100644
--- a/llvm/lib/CodeGen/TargetOptionsImpl.cpp
+++ b/llvm/lib/CodeGen/TargetOptionsImpl.cpp
@@ -22,10 +22,6 @@ using namespace llvm;
 /// DisableFramePointerElim - This returns true if frame pointer elimination
 /// optimization should be disabled for the given machine function.
 bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
-  // Check to see if the target want to forcibly keep frame pointer.
-  if (MF.getSubtarget().getFrameLowering()->keepFramePointer(MF))
-    return true;
-
   const Function &F = MF.getFunction();
 
   if (!F.hasFnAttribute("frame-pointer"))
@@ -40,20 +36,6 @@ bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
   llvm_unreachable("unknown frame pointer flag");
 }
 
-/// DisableLeafFramePointerElim - This returns true if leaf frame pointer
-/// elimination optimization should be disabled for the given machine function.
-bool TargetOptions::DisableLeafFramePointerElim(
-    const MachineFunction &MF) const {
-  const Function &F = MF.getFunction();
-
-  if (!F.hasFnAttribute("frame-pointer"))
-    return false;
-  StringRef FP = F.getFnAttribute("frame-pointer").getValueAsString();
-  if (FP == "all")
-    return true;
-  return false;
-}
-
 bool TargetOptions::FramePointerIsReserved(const MachineFunction &MF) const {
   // Check to see if the target want to forcibly keep frame pointer.
   if (MF.getSubtarget().getFrameLowering()->keepFramePointer(MF))
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 95deaffba1e506d..7e8febd1cc218ed 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -2270,9 +2270,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
   // to take advantage the eliminateFrameIndex machinery. This also ensures it
   // is spilled in the order specified by getCalleeSavedRegs() to make it easier
   // to combine multiple loads / stores.
-  bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF));
-  bool CanEliminateLeafFrame = 
-      !MF.getTarget().Options.DisableLeafFramePointerElim(MF);
+  bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF)) &&
+                          !MF.getTarget().Options.DisableFramePointerElim(MF);
   bool CS1Spilled = false;
   bool LRSpilled = false;
   unsigned NumGPRSpills = 0;
@@ -2514,8 +2513,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
                     << "; EstimatedStack: " << EstimatedStackSize
                     << "; EstimatedFPStack: " << MaxFixedOffset - MaxFPOffset
                     << "; BigFrameOffsets: " << BigFrameOffsets << "\n");
-  if (BigFrameOffsets || !CanEliminateFrame ||
-      RegInfo->cannotEliminateFrame(MF) || !CanEliminateLeafFrame) {
+  if (BigFrameOffsets ||
+      !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
     AFI->setHasStackFrame(true);
 
     if (HasFP) {
diff --git a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
index 6728b9d4584c267..af6ccdc8f4e191f 100644
--- a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
+++ b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
@@ -3,7 +3,7 @@
 ; Radar 10567930: Make sure that all the caller-saved registers are saved and
 ; restored in a function with setjmp/longjmp EH.  In particular, r6 was not
 ; being saved here.
-; CHECK: push {r4, r5, r6, r7, lr}
+; CHECK: push.w {r4, r5, r6, r7, r8, r10, r11, lr}
 
 %0 = type opaque
 %struct.NSConstantString = type { ptr, i32, ptr, i32 }
diff --git a/llvm/test/CodeGen/ARM/atomic-load-store.ll b/llvm/test/CodeGen/ARM/atomic-load-store.ll
index 14e49bf3c9376ae..22b9bcef03b6577 100644
--- a/llvm/test/CodeGen/ARM/atomic-load-store.ll
+++ b/llvm/test/CodeGen/ARM/atomic-load-store.ll
@@ -324,18 +324,17 @@ define void @test_old_store_64bit(ptr %p, i64 %v) {
 ;
 ; ARMOPTNONE-LABEL: test_old_store_64bit:
 ; ARMOPTNONE:       @ %bb.0:
-; ARMOPTNONE-NEXT:    push {r4, r5, r7, lr}
-; ARMOPTNONE-NEXT:    add r7, sp, #8
-; ARMOPTNONE-NEXT:    push {r8, r10, r11}
-; ARMOPTNONE-NEXT:    sub sp, sp, #24
-; ARMOPTNONE-NEXT:    str r0, [sp, #4] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r2, [sp, #8] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r1, [sp, #12] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    dmb ish
-; ARMOPTNONE-NEXT:    ldr r1, [r0]
-; ARMOPTNONE-NEXT:    ldr r0, [r0, #4]
-; ARMOPTNONE-NEXT:    str r1, [sp, #16] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    push	{r4, r5, r7, r8, r10, r11, lr}
+; ARMOPTNONE-NEXT:    add	r7, sp, #20
+; ARMOPTNONE-NEXT:    sub	sp, sp, #20
+; ARMOPTNONE-NEXT:    str	r0, [sp] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r2, [sp, #4] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r1, [sp, #8] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    dmb	ish
+; ARMOPTNONE-NEXT:    ldr	r1, [r0]
+; ARMOPTNONE-NEXT:    ldr	r0, [r0, #4]
+; ARMOPTNONE-NEXT:    str	r1, [sp, #12] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r0, [sp, #16] @ 4-byte Spill
 ; ARMOPTNONE-NEXT:    b LBB5_1
 ; ARMOPTNONE-NEXT:  LBB5_1: @ %atomicrmw.start
 ; ARMOPTNONE-NEXT:    @ =>This Loop Header: Depth=1
@@ -382,8 +381,7 @@ define void @test_old_store_64bit(ptr %p, i64 %v) {
 ; ARMOPTNONE-NEXT:  LBB5_5: @ %atomicrmw.end
 ; ARMOPTNONE-NEXT:    dmb ish
 ; ARMOPTNONE-NEXT:    sub sp, r7, #20
-; ARMOPTNONE-NEXT:    pop {r8, r10, r11}
-; ARMOPTNONE-NEXT:    pop {r4, r5, r7, pc}
+; ARMOPTNONE-NEXT:    pop	{r4, r5, r7, r8, r10, r11, pc}
 ;
 ; THUMBTWO-LABEL: test_old_store_64bit:
 ; THUMBTWO:       @ %bb.0:
diff --git a/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll b/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
index e29ddd52f3d024c..8a7bfbe4290026f 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
@@ -16,7 +16,7 @@ entry:
 ; DARWIN-THUMB2: mov r0, r7
 
 ; LINUX-ARM-LABEL: frameaddr_index0:
-; LINUX-ARM: push {r11, lr}
+; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
 ; LINUX-ARM: mov r0, r11
 
@@ -42,7 +42,7 @@ entry:
 ; DARWIN-THUMB2: ldr r0, [r7]
 
 ; LINUX-ARM-LABEL: frameaddr_index1:
-; LINUX-ARM: push {r11, lr}
+; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
 ; LINUX-ARM: ldr r0, [r11]
 
@@ -73,7 +73,7 @@ entry:
 ; DARWIN-THUMB2: ldr r0, [r0]
 
 ; LINUX-ARM-LABEL: frameaddr_index3:
-; LINUX-ARM: push {r11, lr}
+; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
 ; LINUX-ARM: ldr r0, [r11]
 ; LINUX-ARM: ldr r0, [r0]
diff --git a/llvm/test/CodeGen/ARM/swifterror.ll b/llvm/test/CodeGen/ARM/swifterror.ll
index 4f950ba68760802..f002c54fc60c0f6 100644
--- a/llvm/test/CodeGen/ARM/swifterror.ll
+++ b/llvm/test/CodeGen/ARM/swifterror.ll
@@ -79,18 +79,17 @@ define float @caller(ptr %error_ref) {
 ;
 ; CHECK-O0-LABEL: caller:
 ; CHECK-O0:       @ %bb.0: @ %entry
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r8}
-; CHECK-O0-NEXT:    sub sp, sp, #12
+; CHECK-O0-NEXT:    push	{r7, r8, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
+; CHECK-O0-NEXT:    sub	sp, sp, #12
 ; CHECK-O0-NEXT:    @ implicit-def: $r1
-; CHECK-O0-NEXT:    str r0, [sp] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r8, #0
-; CHECK-O0-NEXT:    bl _foo
-; CHECK-O0-NEXT:    str r8, [sp, #4] @ 4-byte Spill
-; CHECK-O0-NEXT:    movw r0, #0
-; CHECK-O0-NEXT:    cmp r8, r0
-; CHECK-O0-NEXT:    bne LBB1_2
+; CHECK-O0-NEXT:    str	r0, [sp]                        @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r8, #0
+; CHECK-O0-NEXT:    bl	_foo
+; CHECK-O0-NEXT:    str	r8, [sp, #4]                    @ 4-byte Spill
+; CHECK-O0-NEXT:    movw	r0, #0
+; CHECK-O0-NEXT:    cmp	r8, r0
+; CHECK-O0-NEXT:    bne	LBB1_2
 ; CHECK-O0-NEXT:  @ %bb.1: @ %cont
 ; CHECK-O0-NEXT:    ldr r1, [sp] @ 4-byte Reload
 ; CHECK-O0-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
@@ -101,8 +100,7 @@ define float @caller(ptr %error_ref) {
 ; CHECK-O0-NEXT:    bl _free
 ; CHECK-O0-NEXT:    mov r0, #1065353216
 ; CHECK-O0-NEXT:    sub sp, r7, #4
-; CHECK-O0-NEXT:    pop {r8}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    pop	{r7, r8, pc}
 ;
 ; CHECK-ANDROID-LABEL: caller:
 ; CHECK-ANDROID:       @ %bb.0: @ %entry
@@ -176,12 +174,11 @@ define float @caller2(ptr %error_ref) {
 ;
 ; CHECK-O0-LABEL: caller2:
 ; CHECK-O0:       @ %bb.0: @ %entry
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r8}
-; CHECK-O0-NEXT:    sub sp, sp, #16
+; CHECK-O0-NEXT:    push	{r7, r8, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
+; CHECK-O0-NEXT:    sub	sp, sp, #16
 ; CHECK-O0-NEXT:    @ implicit-def: $r1
-; CHECK-O0-NEXT:    str r0, [sp, #8] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r0, [sp, #8] @ 4-byte Spill
 ; CHECK-O0-NEXT:  LBB2_1: @ %bb_loop
 ; CHECK-O0-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-O0-NEXT:    mov r8, #0
@@ -209,8 +206,7 @@ define float @caller2(ptr %error_ref) {
 ; CHECK-O0-NEXT:    bl _free
 ; CHECK-O0-NEXT:    mov r0, #1065353216
 ; CHECK-O0-NEXT:    sub sp, r7, #4
-; CHECK-O0-NEXT:    pop {r8}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    pop	{r7, r8, pc}
 ;
 ; CHECK-ANDROID-LABEL: caller2:
 ; CHECK-ANDROID:       @ %bb.0: @ %entry
@@ -585,21 +581,20 @@ define float @caller3(ptr %error_ref) {
 ;
 ; CHECK-O0-LABEL: caller3:
 ; CHECK-O0:       @ %bb.0: @ %entry
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r8}
-; CHECK-O0-NEXT:    sub sp, sp, #44
-; CHECK-O0-NEXT:    bfc sp, #0, #3
+; CHECK-O0-NEXT:    push	{r7, r8, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
+; CHECK-O0-NEXT:    sub	sp, sp, #44
+; CHECK-O0-NEXT:    bfc	sp, #0, #3
 ; CHECK-O0-NEXT:    @ implicit-def: $r1
-; CHECK-O0-NEXT:    str r0, [sp, #4] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r8, #0
-; CHECK-O0-NEXT:    add r0, sp, #16
-; CHECK-O0-NEXT:    mov r1, #1
-; CHECK-O0-NEXT:    bl _foo_sret
-; CHECK-O0-NEXT:    str r8, [sp, #8] @ 4-byte Spill
-; CHECK-O0-NEXT:    movw r0, #0
-; CHECK-O0-NEXT:    cmp r8, r0
-; CHECK-O0-NEXT:    bne LBB6_2
+; CHECK-O0-NEXT:    str	r0, [sp, #4] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r8, #0
+; CHECK-O0-NEXT:    add	r0, sp, #16
+; CHECK-O0-NEXT:    mov	r1, #1
+; CHECK-O0-NEXT:    bl	_foo_sret
+; CHECK-O0-NEXT:    str	r8, [sp, #8] @ 4-byte Spill
+; CHECK-O0-NEXT:    movw	r0, #0
+; CHECK-O0-NEXT:    cmp	r8, r0
+; CHECK-O0-NEXT:    bne	LBB6_2
 ; CHECK-O0-NEXT:  @ %bb.1: @ %cont
 ; CHECK-O0-NEXT:    ldr r1, [sp, #4] @ 4-byte Reload
 ; CHECK-O0-NEXT:    ldr r0, [sp, #8] @ 4-byte Reload
@@ -610,8 +605,7 @@ define float @caller3(ptr %error_ref) {
 ; CHECK-O0-NEXT:    bl _free
 ; CHECK-O0-NEXT:    mov r0, #1065353216
 ; CHECK-O0-NEXT:    sub sp, r7, #4
-; CHECK-O0-NEXT:    pop {r8}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    pop	{r7, r8, pc}
 ;
 ; CHECK-ANDROID-LABEL: caller3:
 ; CHECK-ANDROID:       @ %bb.0: @ %entry
@@ -809,27 +803,26 @@ define float @caller4(ptr %error_ref) {
 ;
 ; CHECK-O0-LABEL: caller4:
 ; CHECK-O0:       @ %bb.0: @ %entry
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r8}
-; CHECK-O0-NEXT:    sub sp, sp, #24
+; CHECK-O0-NEXT:    push	{r7, r8, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
+; CHECK-O0-NEXT:    sub	sp, sp, #24
 ; CHECK-O0-NEXT:    @ implicit-def: $r1
-; CHECK-O0-NEXT:    str r0, [sp] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r8, #0
-; CHECK-O0-NEXT:    mov r0, #10
-; CHECK-O0-NEXT:    str r0, [r7, #-12]
-; CHECK-O0-NEXT:    mov r0, #11
-; CHECK-O0-NEXT:    str r0, [sp, #12]
-; CHECK-O0-NEXT:    mov r0, #12
-; CHECK-O0-NEXT:    str r0, [sp, #8]
-; CHECK-O0-NEXT:    ldr r0, [r7, #-12]
-; CHECK-O0-NEXT:    ldr r1, [sp, #12]
-; CHECK-O0-NEXT:    ldr r2, [sp, #8]
-; CHECK-O0-NEXT:    bl _foo_vararg
-; CHECK-O0-NEXT:    str r8, [sp, #4] @ 4-byte Spill
-; CHECK-O0-NEXT:    movw r0, #0
-; CHECK-O0-NEXT:    cmp r8, r0
-; CHECK-O0-NEXT:    bne LBB8_2
+; CHECK-O0-NEXT:    str	r0, [sp] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r8, #0
+; CHECK-O0-NEXT:    mov	r0, #10
+; CHECK-O0-NEXT:    str	r0, [r7, #-12]
+; CHECK-O0-NEXT:    mov	r0, #11
+; CHECK-O0-NEXT:    str	r0, [sp, #12]
+; CHECK-O0-NEXT:    mov	r0, #12
+; CHECK-O0-NEXT:    str	r0, [sp, #8]
+; CHECK-O0-NEXT:    ldr	r0, [r7, #-12]
+; CHECK-O0-NEXT:    ldr	r1, [sp, #12]
+; CHECK-O0-NEXT:    ldr	r2, [sp, #8]
+; CHECK-O0-NEXT:    bl	_foo_vararg
+; CHECK-O0-NEXT:    str	r8, [sp, #4] @ 4-byte Spill
+; CHECK-O0-NEXT:    movw	r0, #0
+; CHECK-O0-NEXT:    cmp	r8, r0
+; CHECK-O0-NEXT:    bne	LBB8_2
 ; CHECK-O0-NEXT:  @ %bb.1: @ %cont
 ; CHECK-O0-NEXT:    ldr r1, [sp] @ 4-byte Reload
 ; CHECK-O0-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
@@ -840,8 +833,7 @@ define float @caller4(ptr %error_ref) {
 ; CHECK-O0-NEXT:    bl _free
 ; CHECK-O0-NEXT:    mov r0, #1065353216
 ; CHECK-O0-NEXT:    sub sp, r7, #4
-; CHECK-O0-NEXT:    pop {r8}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    pop	{r7, r8, pc}
 ;
 ; CHECK-ANDROID-LABEL: caller4:
 ; CHECK-ANDROID:       @ %bb.0: @ %entry
@@ -995,14 +987,12 @@ define swiftcc void @swifterror_reg_clobber(ptr nocapture %err) {
 ;
 ; CHECK-O0-LABEL: swifterror_reg_clobber:
 ; CHECK-O0:       @ %bb.0:
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r8}
+; CHECK-O0-NEXT:    push	{r7, r8, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
 ; CHECK-O0-NEXT:    @ InlineAsm Start
 ; CHECK-O0-NEXT:    nop
 ; CHECK-O0-NEXT:    @ InlineAsm End
-; CHECK-O0-NEXT:    pop {r8}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    pop	{r7, r8, pc}
 ;
 ; CHECK-ANDROID-LABEL: swifterror_reg_clobber:
 ; CHECK-ANDROID:       @ %bb.0:
@@ -1048,36 +1038,34 @@ define swiftcc void @params_in_reg(i32, i32, i32, i32, ptr swiftself, ptr nocapt
 ;
 ; CHECK-O0-LABEL: params_in_reg:
 ; CHECK-O0:       @ %bb.0:
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r10}
-; CHECK-O0-NEXT:    sub sp, sp, #28
-; CHECK-O0-NEXT:    bfc sp, #0, #3
-; CHECK-O0-NEXT:    str r8, [sp, #20] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r10, [sp] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r3, [sp, #16] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r2, [sp, #12] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r1, [sp, #8] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r0, [sp, #4] @ 4-byte Spill
+; CHECK-O0-NEXT:    push	{r7, r10, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
+; CHECK-O0-NEXT:    sub	sp, sp, #28
+; CHECK-O0-NEXT:    bfc	sp, #0, #3
+; CHECK-O0-NEXT:    str	r8, [sp, #20] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r10, [sp] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r3, [sp, #16] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r2, [sp, #12] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r1, [sp, #8] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r0, [sp, #4] @ 4-byte Spill
 ; CHECK-O0-NEXT:    @ implicit-def: $r0
-; CHECK-O0-NEXT:    mov r8, #0
-; CHECK-O0-NEXT:    mov r0, #1
-; CHECK-O0-NEXT:    mov r1, #2
-; CHECK-O0-NEXT:    mov r2, #3
-; CHECK-O0-NEXT:    mov r3, #4
-; CHECK-O0-NEXT:    mov r10, r8
-; CHECK-O0-NEXT:    bl _params_in_reg2
-; CHECK-O0-NEXT:    ldr r10, [sp] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r1, [sp, #8] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r2, [sp, #12] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r3, [sp, #16] @ 4-byte Reload
-; CHECK-O0-NEXT:    mov r9, r8
-; CHECK-O0-NEXT:    ldr r8, [sp, #20] @ 4-byte Reload
-; CHECK-O0-NEXT:    bl _params_in_reg2
-; CHECK-O0-NEXT:    sub sp, r7, #4
-; CHECK-O0-NEXT:    pop {r10}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    mov	r8, #0
+; CHECK-O0-NEXT:    mov	r0, #1
+; CHECK-O0-NEXT:    mov	r1, #2
+; CHECK-O0-NEXT:    mov	r2, #3
+; CHECK-O0-NEXT:    mov	r3, #4
+; CHECK-O0-NEXT:    mov	r10, r8
+; CHECK-O0-NEXT:    bl	_params_in_reg2
+; CHECK-O0-NEXT:    ldr	r10, [sp] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r0, [sp, #4] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r1, [sp, #8] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r2, [sp, #12] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r3, [sp, #16] @ 4-byte Reload
+; CHECK-O0-NEXT:    mov	r9, r8
+; CHECK-O0-NEXT:    ldr	r8, [sp, #20] @ 4-byte Reload
+; CHECK-O0-NEXT:    bl	_params_in_reg2
+; CHECK-O0-NEXT:    sub	sp, r7, #4
+; CHECK-O0-NEXT:    pop	{r7, r10, pc}
 ;
 ; CHECK-ANDROID-LABEL: params_in_reg:
 ; CHECK-ANDROID:       @ %bb.0:
@@ -1165,65 +1153,63 @@ define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i3
 ;
 ; CHECK-O0-LABEL: params_and_return_in_reg:
 ; CHECK-O0:       @ %bb.0:
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r10}
-; CHECK-O0-NEXT:    sub sp, sp, #76
-; CHECK-O0-NEXT:    bfc sp, #0, #3
-; CHECK-O0-NEXT:    str r8, [sp, #24] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r10, [sp, #4] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r3, [sp, #20] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r2, [sp, #16] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r1, [sp, #12] @ 4-byte Spill
-; CHECK-O0-NEXT:    str r0, [sp, #8] @ 4-byte Spill
+; CHECK-O0-NEXT:    push	{r7, r10, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
+; CHECK-O0-NEXT:    sub	sp, sp, #76
+; CHECK-O0-NEXT:    bfc	sp, #0, #3
+; CHECK-O0-NEXT:    str	r8, [sp, #24] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r10, [sp, #4] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r3, [sp, #20] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r2, [sp, #16] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r1, [sp, #12] @ 4-byte Spill
+; CHECK-O0-NEXT:    str	r0, [sp, #8] @ 4-byte Spill
 ; CHECK-O0-NEXT:    @ implicit-def: $r0
-; CHECK-O0-NEXT:    mov r8, #0
-; CHECK-O0-NEXT:    str r8, [sp, #28] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r0, #1
-; CHECK-O0-NEXT:    str r0, [sp, #32] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r1, #2
-; CHECK-O0-NEXT:    str r1, [sp, #36] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r2, #3
-; CHECK-O0-NEXT:    str r2, [sp, #40] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r3, #4
-; CHECK-O0-NEXT:    str r3, [sp, #44] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r10, r8
-; CHECK-O0-NEXT:    bl _params_in_reg2
-; CHECK-O0-NEXT:    ldr r10, [sp, #4] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r0, [sp, #8] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r1, [sp, #12] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r2, [sp, #16] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r3, [sp, #20] @ 4-byte Reload
-; CHECK-O0-NEXT:    mov r9, r8
-; CHECK-O0-NEXT:    ldr r8, [sp, #24] @ 4-byte Reload
-; CHECK-O0-NEXT:    str r9, [sp, #48] @ 4-byte Spill
-; CHECK-O0-NEXT:    bl _params_and_return_in_reg2
-; CHECK-O0-NEXT:    ldr r10, [sp, #28] @ 4-byte Reload
-; CHECK-O0-NEXT:    mov r9, r0
-; CHECK-O0-NEXT:    ldr r0, [sp, #32] @ 4-byte Reload
-; CHECK-O0-NEXT:    str r9, [sp, #52] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r9, r1
-; CHECK-O0-NEXT:    ldr r1, [sp, #36] @ 4-byte Reload
-; CHECK-O0-NEXT:    str r9, [sp, #56] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r9, r2
-; CHECK-O0-NEXT:    ldr r2, [sp, #40] @ 4-byte Reload
-; CHECK-O0-NEXT:    str r9, [sp, #60] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r9, r3
-; CHECK-O0-NEXT:    ldr r3, [sp, #44] @ 4-byte Reload
-; CHECK-O0-NEXT:    str r9, [sp, #64] @ 4-byte Spill
-; CHECK-O0-NEXT:    mov r9, r8
-; CHECK-O0-NEXT:    ldr r8, [sp, #48] @ 4-byte Reload
-; CHECK-O0-NEXT:    str r9, [sp, #68] @ 4-byte Spill
-; CHECK-O0-NEXT:    bl _params_in_reg2
-; CHECK-O0-NEXT:    ldr r0, [sp, #52] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r1, [sp, #56] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r2, [sp, #60] @ 4-byte Reload
-; CHECK-O0-NEXT:    ldr r3, [sp, #64] @ 4-byte Reload
-; CHECK-O0-NEXT:    mov r9, r8
-; CHECK-O0-NEXT:    ldr r8, [sp, #68] @ 4-byte Reload
-; CHECK-O0-NEXT:    sub sp, r7, #4
-; CHECK-O0-NEXT:    pop {r10}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    mov	r8, #0
+; CHECK-O0-NEXT:    str	r8, [sp, #28] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r0, #1
+; CHECK-O0-NEXT:    str	r0, [sp, #32] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r1, #2
+; CHECK-O0-NEXT:    str	r1, [sp, #36] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r2, #3
+; CHECK-O0-NEXT:    str	r2, [sp, #40] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r3, #4
+; CHECK-O0-NEXT:    str	r3, [sp, #44] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r10, r8
+; CHECK-O0-NEXT:    bl	_params_in_reg2
+; CHECK-O0-NEXT:    ldr	r10, [sp, #4] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r0, [sp, #8] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r1, [sp, #12] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r2, [sp, #16] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r3, [sp, #20] @ 4-byte Reload
+; CHECK-O0-NEXT:    mov	r9, r8
+; CHECK-O0-NEXT:    ldr	r8, [sp, #24] @ 4-byte Reload
+; CHECK-O0-NEXT:    str	r9, [sp, #48] @ 4-byte Spill
+; CHECK-O0-NEXT:    bl	_params_and_return_in_reg2
+; CHECK-O0-NEXT:    ldr	r10, [sp, #28] @ 4-byte Reload
+; CHECK-O0-NEXT:    mov	r9, r0
+; CHECK-O0-NEXT:    ldr	r0, [sp, #32] @ 4-byte Reload
+; CHECK-O0-NEXT:    str	r9, [sp, #52] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r9, r1
+; CHECK-O0-NEXT:    ldr	r1, [sp, #36] @ 4-byte Reload
+; CHECK-O0-NEXT:    str	r9, [sp, #56] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r9, r2
+; CHECK-O0-NEXT:    ldr	r2, [sp, #40] @ 4-byte Reload
+; CHECK-O0-NEXT:    str	r9, [sp, #60] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r9, r3
+; CHECK-O0-NEXT:    ldr	r3, [sp, #44] @ 4-byte Reload
+; CHECK-O0-NEXT:    str	r9, [sp, #64] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r9, r8
+; CHECK-O0-NEXT:    ldr	r8, [sp, #48] @ 4-byte Reload
+; CHECK-O0-NEXT:    str	r9, [sp, #68] @ 4-byte Spill
+; CHECK-O0-NEXT:    bl	_params_in_reg2
+; CHECK-O0-NEXT:    ldr	r0, [sp, #52] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r1, [sp, #56] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r2, [sp, #60] @ 4-byte Reload
+; CHECK-O0-NEXT:    ldr	r3, [sp, #64] @ 4-byte Reload
+; CHECK-O0-NEXT:    mov	r9, r8
+; CHECK-O0-NEXT:    ldr	r8, [sp, #68] @ 4-byte Reload
+; CHECK-O0-NEXT:    sub	sp, r7, #4
+; CHECK-O0-NEXT:    pop	{r7, r10, pc}
 ;
 ; CHECK-ANDROID-LABEL: params_and_return_in_reg:
 ; CHECK-ANDROID:       @ %bb.0:
@@ -1339,19 +1325,17 @@ define swiftcc ptr @testAssign(ptr %error_ref) {
 ;
 ; CHECK-O0-LABEL: testAssign:
 ; CHECK-O0:       @ %bb.0: @ %entry
-; CHECK-O0-NEXT:    push {r7, lr}
-; CHECK-O0-NEXT:    mov r7, sp
-; CHECK-O0-NEXT:    push {r8}
-; CHECK-O0-NEXT:    sub sp, sp, #8
+; CHECK-O0-NEXT:    push	{r7, r8, lr}
+; CHECK-O0-NEXT:    add	r7, sp, #4
+; CHECK-O0-NEXT:    sub	sp, sp, #8
 ; CHECK-O0-NEXT:    @ implicit-def: $r1
-; CHECK-O0-NEXT:    mov r8, #0
-; CHECK-O0-NEXT:    bl _foo2
-; CHECK-O0-NEXT:    str r8, [sp] @ 4-byte Spill
+; CHECK-O0-NEXT:    mov	r8, #0
+; CHECK-O0-NEXT:    bl	_foo2
+; CHECK-O0-NEXT:    str	r8, [sp] @ 4-byte Spill
 ; CHECK-O0-NEXT:  @ %bb.1: @ %a
 ; CHECK-O0-NEXT:    ldr r0, [sp] @ 4-byte Reload
 ; CHECK-O0-NEXT:    sub sp, r7, #4
-; CHECK-O0-NEXT:    pop {r8}
-; CHECK-O0-NEXT:    pop {r7, pc}
+; CHECK-O0-NEXT:    pop	{r7, r8, pc}
 ;
 ; CHECK-ANDROID-LABEL: testAssign:
 ; CHECK-ANDROID:       @ %bb.0: @ %entry