[ImportVerilog] Insert missing conversions around instance ports #7647
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Add a `moore.builtin.clog2` op and use it to convert `$clog2` calls in ImportVerilog.
Allow `'{...}` assignment patterns to be used to assign integer values.
Slang already computes the value for each element in the resulting type.
All that's needed is a concat with the right operand order.
In certain corner cases, Slang does not insert the necessary conversion AST nodes around instance ports. This can be problematic if an input or output port is connected to a cast-compatible type (e.g. `i32` and `array<1 x i32>`). To fix this, always insert conversions if the types of a port and the connected value differ.
maerhart
approved these changes
Sep 28, 2024
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In certain corner cases, Slang does not insert the necessary conversion AST nodes around instance ports. This can be problematic if an input or output port is connected to a cast-compatible type (e.g.
i32andarray<1 x i32>). To fix this, always insert conversions if the types of a port and the connected value differ.